Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T16,T8
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T13,T16,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T13,T16,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T13,T16,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T16,T8
1	0	Covered	T16,T8,T10
1	1	Covered	T13,T16,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T8
0	1	Covered	T13,T8,T10
1	0	Covered	T8,T10,T38

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T39,T28
0	1	Covered	T16,T28,T30
1	0	Covered	T38,T83,T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T38,T39
1	-	Covered	T16,T28,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T16,T8
DetectSt	168	Covered	T13,T16,T8
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T16,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T16,T8
DebounceSt->IdleSt	163	Covered	T215,T78,T50
DetectSt->IdleSt	186	Covered	T13,T8,T10
DetectSt->StableSt	191	Covered	T16,T38,T39
IdleSt->DebounceSt	148	Covered	T13,T16,T8
StableSt->IdleSt	206	Covered	T16,T38,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T16,T8
0	1	Covered	T13,T16,T8
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T16,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T13,T16,T8
IdleSt	0	-	-	-	-	-	-	Covered	T13,T16,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T16,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T215,T78,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T16,T8
DetectSt	-	-	-	-	1	-	-	Covered	T13,T8,T10
DetectSt	-	-	-	-	0	1	-	Covered	T16,T38,T39
DetectSt	-	-	-	-	0	0	-	Covered	T13,T16,T8
StableSt	-	-	-	-	-	-	1	Covered	T16,T38,T28
StableSt	-	-	-	-	-	-	0	Covered	T16,T39,T28
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	3235	0	0
CntIncr_A	8235605	112394	0	0
CntNoWrap_A	8235605	7594810	0	0
DetectStDropOut_A	8235605	489	0	0
DetectedOut_A	8235605	78247	0	0
DetectedPulseOut_A	8235605	922	0	0
DisabledIdleSt_A	8235605	7136533	0	0
DisabledNoDetection_A	8235605	7138710	0	0
EnterDebounceSt_A	8235605	1631	0	0
EnterDetectSt_A	8235605	1604	0	0
EnterStableSt_A	8235605	922	0	0
PulseIsPulse_A	8235605	922	0	0
StayInStableSt	8235605	77231	0	0
gen_high_event_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_high_level_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	814	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	3235	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	16	0	0
T9	608	0	0	0
T10	0	46	0	0
T13	5766	28	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	52	0	0
T28	0	60	0	0
T30	0	28	0	0
T38	0	50	0	0
T39	0	2	0	0
T41	0	46	0	0
T42	0	40	0	0
T49	658	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	112394	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	1276	0	0
T9	608	0	0	0
T10	0	956	0	0
T13	5766	874	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	1872	0	0
T28	0	1800	0	0
T30	0	1176	0	0
T38	0	1982	0	0
T39	0	21	0	0
T41	0	1013	0	0
T42	0	1254	0	0
T49	658	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7594810	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5337	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	489	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	1	0	0
T9	608	0	0	0
T10	0	10	0	0
T13	5766	14	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T38	0	13	0	0
T41	0	23	0	0
T42	0	4	0	0
T49	658	0	0	0
T96	0	27	0	0
T247	0	25	0	0
T266	0	30	0	0
T267	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	78247	0	0
T8	22766	0	0	0
T9	608	0	0	0
T16	19907	711	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	1656	0	0
T29	0	3009	0	0
T30	0	1422	0	0
T38	0	4	0	0
T39	0	37	0	0
T49	658	0	0	0
T64	502	0	0	0
T82	0	3141	0	0
T91	0	1092	0	0
T93	421	0	0	0
T95	0	919	0	0
T128	0	1367	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	922	0	0
T8	22766	0	0	0
T9	608	0	0	0
T16	19907	26	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	30	0	0
T29	0	27	0	0
T30	0	14	0	0
T38	0	4	0	0
T39	0	1	0	0
T49	658	0	0	0
T64	502	0	0	0
T82	0	26	0	0
T91	0	7	0	0
T93	421	0	0	0
T95	0	6	0	0
T128	0	17	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7136533	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	2014	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7138710	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	2014	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	1631	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	8	0	0
T9	608	0	0	0
T10	0	23	0	0
T13	5766	14	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	26	0	0
T28	0	30	0	0
T30	0	14	0	0
T38	0	25	0	0
T39	0	1	0	0
T41	0	23	0	0
T42	0	20	0	0
T49	658	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	1604	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	8	0	0
T9	608	0	0	0
T10	0	23	0	0
T13	5766	14	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	26	0	0
T28	0	30	0	0
T30	0	14	0	0
T38	0	25	0	0
T39	0	1	0	0
T41	0	23	0	0
T42	0	20	0	0
T49	658	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	922	0	0
T8	22766	0	0	0
T9	608	0	0	0
T16	19907	26	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	30	0	0
T29	0	27	0	0
T30	0	14	0	0
T38	0	4	0	0
T39	0	1	0	0
T49	658	0	0	0
T64	502	0	0	0
T82	0	26	0	0
T91	0	7	0	0
T93	421	0	0	0
T95	0	6	0	0
T128	0	17	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	922	0	0
T8	22766	0	0	0
T9	608	0	0	0
T16	19907	26	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	30	0	0
T29	0	27	0	0
T30	0	14	0	0
T38	0	4	0	0
T39	0	1	0	0
T49	658	0	0	0
T64	502	0	0	0
T82	0	26	0	0
T91	0	7	0	0
T93	421	0	0	0
T95	0	6	0	0
T128	0	17	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	77231	0	0
T8	22766	0	0	0
T9	608	0	0	0
T16	19907	681	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	1626	0	0
T29	0	2977	0	0
T30	0	1406	0	0
T39	0	35	0	0
T49	658	0	0	0
T64	502	0	0	0
T82	0	3115	0	0
T83	0	102	0	0
T91	0	1083	0	0
T93	421	0	0	0
T95	0	913	0	0
T128	0	1348	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	814	0	0
T8	22766	0	0	0
T9	608	0	0	0
T16	19907	22	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	30	0	0
T29	0	22	0	0
T30	0	12	0	0
T49	658	0	0	0
T64	502	0	0	0
T82	0	26	0	0
T91	0	5	0	0
T93	421	0	0	0
T95	0	6	0	0
T110	0	3	0	0
T113	0	21	0	0
T128	0	15	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T13,T16
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T16
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T16,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T16,T39

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T16,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T16,T38
1	0	Covered	T2,T13,T6
1	1	Covered	T2,T16,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T16,T28
0	1	Covered	T97,T98,T99
1	0	Covered	T78,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T16,T28
0	1	Covered	T2,T28,T30
1	0	Covered	T79,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T16,T28
1	-	Covered	T2,T28,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T16,T39
DetectSt	168	Covered	T2,T16,T28
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T16,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T16,T28
DebounceSt->IdleSt	163	Covered	T39,T30,T43
DetectSt->IdleSt	186	Covered	T97,T98,T99
DetectSt->StableSt	191	Covered	T2,T16,T28
IdleSt->DebounceSt	148	Covered	T2,T16,T39
StableSt->IdleSt	206	Covered	T2,T16,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T16,T39
0	1	Covered	T2,T16,T39
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T16,T28
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T16,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T16,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T30,T43
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T16,T39
DetectSt	-	-	-	-	1	-	-	Covered	T97,T98,T99
DetectSt	-	-	-	-	0	1	-	Covered	T2,T16,T28
DetectSt	-	-	-	-	0	0	-	Covered	T2,T16,T28
StableSt	-	-	-	-	-	-	1	Covered	T2,T28,T30
StableSt	-	-	-	-	-	-	0	Covered	T2,T16,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	955	0	0
CntIncr_A	8235605	55044	0	0
CntNoWrap_A	8235605	7597090	0	0
DetectStDropOut_A	8235605	57	0	0
DetectedOut_A	8235605	13673	0	0
DetectedPulseOut_A	8235605	374	0	0
DisabledIdleSt_A	8235605	7211112	0	0
DisabledNoDetection_A	8235605	7212712	0	0
EnterDebounceSt_A	8235605	523	0	0
EnterDetectSt_A	8235605	435	0	0
EnterStableSt_A	8235605	374	0	0
PulseIsPulse_A	8235605	374	0	0
StayInStableSt	8235605	13267	0	0
gen_high_level_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	338	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	955	0	0
T2	33179	26	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	8	0	0
T28	0	2	0	0
T29	0	10	0	0
T30	0	7	0	0
T32	0	16	0	0
T39	0	1	0	0
T43	0	1	0	0
T76	0	4	0	0
T91	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	55044	0	0
T2	33179	1560	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	164	0	0
T28	0	61	0	0
T29	0	315	0	0
T30	0	193	0	0
T32	0	1099	0	0
T39	0	20	0	0
T43	0	20	0	0
T76	0	50	0	0
T91	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597090	0	0
T1	1121	720	0	0
T2	33179	32661	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	57	0	0
T97	9482	7	0	0
T98	0	8	0	0
T99	0	5	0	0
T100	0	1	0	0
T101	0	6	0	0
T102	0	7	0	0
T103	0	3	0	0
T105	0	3	0	0
T107	0	10	0	0
T108	0	4	0	0
T118	422	0	0	0
T119	493	0	0	0
T120	522	0	0	0
T121	527	0	0	0
T122	444	0	0	0
T123	415	0	0	0
T124	184249	0	0	0
T125	496	0	0	0
T126	531	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	13673	0	0
T2	33179	395	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	150	0	0
T28	0	56	0	0
T29	0	272	0	0
T30	0	208	0	0
T32	0	488	0	0
T55	0	9	0	0
T76	0	12	0	0
T91	0	121	0	0
T127	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	374	0	0
T2	33179	13	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	4	0	0
T28	0	1	0	0
T29	0	5	0	0
T30	0	3	0	0
T32	0	7	0	0
T55	0	2	0	0
T76	0	2	0	0
T91	0	2	0	0
T127	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7211112	0	0
T1	1121	720	0	0
T2	33179	28203	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7212712	0	0
T1	1121	721	0	0
T2	33179	28203	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	523	0	0
T2	33179	13	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	4	0	0
T28	0	1	0	0
T29	0	5	0	0
T30	0	4	0	0
T32	0	9	0	0
T39	0	1	0	0
T43	0	1	0	0
T76	0	2	0	0
T91	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	435	0	0
T2	33179	13	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	4	0	0
T28	0	1	0	0
T29	0	5	0	0
T30	0	3	0	0
T32	0	7	0	0
T55	0	2	0	0
T76	0	2	0	0
T91	0	2	0	0
T127	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	374	0	0
T2	33179	13	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	4	0	0
T28	0	1	0	0
T29	0	5	0	0
T30	0	3	0	0
T32	0	7	0	0
T55	0	2	0	0
T76	0	2	0	0
T91	0	2	0	0
T127	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	374	0	0
T2	33179	13	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	4	0	0
T28	0	1	0	0
T29	0	5	0	0
T30	0	3	0	0
T32	0	7	0	0
T55	0	2	0	0
T76	0	2	0	0
T91	0	2	0	0
T127	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	13267	0	0
T2	33179	382	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	142	0	0
T28	0	55	0	0
T29	0	267	0	0
T30	0	205	0	0
T32	0	481	0	0
T55	0	7	0	0
T76	0	10	0	0
T91	0	117	0	0
T127	0	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	338	0	0
T2	33179	13	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T28	0	1	0	0
T29	0	5	0	0
T30	0	3	0	0
T32	0	7	0	0
T55	0	2	0	0
T71	0	1	0	0
T76	0	2	0	0
T127	0	1	0	0
T128	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T16,T8
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T13,T16,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T13,T16,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T13,T16,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T16,T8
1	0	Covered	T16,T8,T10
1	1	Covered	T13,T16,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T8
0	1	Covered	T13,T41,T91
1	0	Covered	T38,T83,T113

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T8,T10
0	1	Covered	T16,T8,T10
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T8,T10
1	-	Covered	T16,T8,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T16,T8
DetectSt	168	Covered	T13,T16,T8
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T16,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T16,T8
DebounceSt->IdleSt	163	Covered	T215,T78,T50
DetectSt->IdleSt	186	Covered	T13,T38,T41
DetectSt->StableSt	191	Covered	T16,T8,T10
IdleSt->DebounceSt	148	Covered	T13,T16,T8
StableSt->IdleSt	206	Covered	T16,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T16,T8
0	1	Covered	T13,T16,T8
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T16,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T13,T16,T8
IdleSt	0	-	-	-	-	-	-	Covered	T13,T16,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T16,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T215,T78,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T16,T8
DetectSt	-	-	-	-	1	-	-	Covered	T13,T38,T41
DetectSt	-	-	-	-	0	1	-	Covered	T16,T8,T10
DetectSt	-	-	-	-	0	0	-	Covered	T13,T16,T8
StableSt	-	-	-	-	-	-	1	Covered	T16,T8,T10
StableSt	-	-	-	-	-	-	0	Covered	T16,T8,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	3271	0	0
CntIncr_A	8235605	109452	0	0
CntNoWrap_A	8235605	7594774	0	0
DetectStDropOut_A	8235605	433	0	0
DetectedOut_A	8235605	78447	0	0
DetectedPulseOut_A	8235605	973	0	0
DisabledIdleSt_A	8235605	7138504	0	0
DisabledNoDetection_A	8235605	7140658	0	0
EnterDebounceSt_A	8235605	1648	0	0
EnterDetectSt_A	8235605	1623	0	0
EnterStableSt_A	8235605	973	0	0
PulseIsPulse_A	8235605	973	0	0
StayInStableSt	8235605	77357	0	0
gen_high_event_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_high_level_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	855	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	3271	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	12	0	0
T9	608	0	0	0
T10	0	48	0	0
T13	5766	26	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	18	0	0
T28	0	16	0	0
T29	0	48	0	0
T30	0	20	0	0
T38	0	28	0	0
T41	0	24	0	0
T42	0	34	0	0
T49	658	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	109452	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	546	0	0
T9	608	0	0	0
T10	0	960	0	0
T13	5766	813	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	648	0	0
T28	0	336	0	0
T29	0	1560	0	0
T30	0	670	0	0
T38	0	1116	0	0
T41	0	524	0	0
T42	0	697	0	0
T49	658	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7594774	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5339	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	433	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T13	5766	13	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T41	0	12	0	0
T49	658	0	0	0
T91	0	4	0	0
T96	0	21	0	0
T113	0	8	0	0
T211	0	15	0	0
T247	0	4	0	0
T266	0	27	0	0
T267	0	7	0	0
T268	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	78447	0	0
T8	22766	942	0	0
T9	608	0	0	0
T10	0	1156	0	0
T16	19907	44	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	322	0	0
T29	0	2250	0	0
T30	0	665	0	0
T42	0	1620	0	0
T49	658	0	0	0
T51	0	367	0	0
T64	502	0	0	0
T82	0	862	0	0
T93	421	0	0	0
T95	0	930	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	973	0	0
T8	22766	6	0	0
T9	608	0	0	0
T10	0	24	0	0
T16	19907	9	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	8	0	0
T29	0	24	0	0
T30	0	10	0	0
T42	0	17	0	0
T49	658	0	0	0
T51	0	6	0	0
T64	502	0	0	0
T82	0	12	0	0
T93	421	0	0	0
T95	0	18	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7138504	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	2014	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7140658	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	2014	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	1648	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	6	0	0
T9	608	0	0	0
T10	0	24	0	0
T13	5766	13	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	9	0	0
T28	0	8	0	0
T29	0	24	0	0
T30	0	10	0	0
T38	0	14	0	0
T41	0	12	0	0
T42	0	17	0	0
T49	658	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	1623	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	6	0	0
T9	608	0	0	0
T10	0	24	0	0
T13	5766	13	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	9	0	0
T28	0	8	0	0
T29	0	24	0	0
T30	0	10	0	0
T38	0	14	0	0
T41	0	12	0	0
T42	0	17	0	0
T49	658	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	973	0	0
T8	22766	6	0	0
T9	608	0	0	0
T10	0	24	0	0
T16	19907	9	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	8	0	0
T29	0	24	0	0
T30	0	10	0	0
T42	0	17	0	0
T49	658	0	0	0
T51	0	6	0	0
T64	502	0	0	0
T82	0	12	0	0
T93	421	0	0	0
T95	0	18	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	973	0	0
T8	22766	6	0	0
T9	608	0	0	0
T10	0	24	0	0
T16	19907	9	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	8	0	0
T29	0	24	0	0
T30	0	10	0	0
T42	0	17	0	0
T49	658	0	0	0
T51	0	6	0	0
T64	502	0	0	0
T82	0	12	0	0
T93	421	0	0	0
T95	0	18	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	77357	0	0
T8	22766	934	0	0
T9	608	0	0	0
T10	0	1130	0	0
T16	19907	35	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	314	0	0
T29	0	2223	0	0
T30	0	653	0	0
T42	0	1603	0	0
T49	658	0	0	0
T51	0	359	0	0
T64	502	0	0	0
T82	0	849	0	0
T93	421	0	0	0
T95	0	912	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	855	0	0
T8	22766	4	0	0
T9	608	0	0	0
T10	0	22	0	0
T16	19907	9	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	8	0	0
T29	0	21	0	0
T30	0	8	0	0
T42	0	17	0	0
T49	658	0	0	0
T51	0	4	0	0
T64	502	0	0	0
T82	0	11	0	0
T93	421	0	0	0
T95	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T13,T16
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T16
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T16,T8
1	0	Covered	T2,T13,T6
1	1	Covered	T2,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T10
0	1	Covered	T31,T77,T269
1	0	Covered	T78,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T10
0	1	Covered	T2,T10,T30
1	0	Covered	T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T10
1	-	Covered	T2,T10,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T10
DetectSt	168	Covered	T2,T8,T10
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T10
DebounceSt->IdleSt	163	Covered	T32,T95,T77
DetectSt->IdleSt	186	Covered	T31,T77,T269
DetectSt->StableSt	191	Covered	T2,T8,T10
IdleSt->DebounceSt	148	Covered	T2,T8,T10
StableSt->IdleSt	206	Covered	T2,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T10
0	1	Covered	T2,T8,T10
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T10
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T95,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T31,T77,T269
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T10
DetectSt	-	-	-	-	0	0	-	Covered	T2,T8,T10
StableSt	-	-	-	-	-	-	1	Covered	T2,T10,T30
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	905	0	0
CntIncr_A	8235605	52057	0	0
CntNoWrap_A	8235605	7597140	0	0
DetectStDropOut_A	8235605	69	0	0
DetectedOut_A	8235605	14208	0	0
DetectedPulseOut_A	8235605	358	0	0
DisabledIdleSt_A	8235605	7214603	0	0
DisabledNoDetection_A	8235605	7216234	0	0
EnterDebounceSt_A	8235605	477	0	0
EnterDetectSt_A	8235605	429	0	0
EnterStableSt_A	8235605	358	0	0
PulseIsPulse_A	8235605	358	0	0
StayInStableSt	8235605	13826	0	0
gen_high_level_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	331	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	905	0	0
T2	33179	12	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	4	0	0
T9	608	0	0	0
T10	0	4	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T29	0	4	0	0
T30	0	2	0	0
T32	0	5	0	0
T42	0	2	0	0
T51	0	4	0	0
T76	0	12	0	0
T95	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	52057	0	0
T2	33179	762	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	144	0	0
T9	608	0	0	0
T10	0	142	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T29	0	112	0	0
T30	0	55	0	0
T32	0	366	0	0
T42	0	59	0	0
T51	0	78	0	0
T76	0	156	0	0
T95	0	34	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597140	0	0
T1	1121	720	0	0
T2	33179	32675	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	69	0	0
T31	16707	1	0	0
T77	17097	12	0	0
T78	0	1	0	0
T81	0	7	0	0
T97	9482	0	0	0
T103	0	5	0	0
T105	0	4	0	0
T118	422	0	0	0
T119	493	0	0	0
T196	691	0	0	0
T213	0	4	0	0
T269	0	3	0	0
T270	0	4	0	0
T271	0	9	0	0
T272	14124	0	0	0
T273	834	0	0	0
T274	667	0	0	0
T275	436	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	14208	0	0
T2	33179	132	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	110	0	0
T9	608	0	0	0
T10	0	114	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T29	0	122	0	0
T30	0	68	0	0
T32	0	51	0	0
T42	0	60	0	0
T51	0	122	0	0
T76	0	28	0	0
T127	0	22	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	358	0	0
T2	33179	6	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	2	0	0
T9	608	0	0	0
T10	0	2	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T32	0	1	0	0
T42	0	1	0	0
T51	0	2	0	0
T76	0	6	0	0
T127	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7214603	0	0
T1	1121	720	0	0
T2	33179	28203	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7216234	0	0
T1	1121	721	0	0
T2	33179	28203	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	477	0	0
T2	33179	6	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	2	0	0
T9	608	0	0	0
T10	0	2	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T32	0	4	0	0
T42	0	1	0	0
T51	0	2	0	0
T76	0	6	0	0
T95	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	429	0	0
T2	33179	6	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	2	0	0
T9	608	0	0	0
T10	0	2	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T32	0	1	0	0
T42	0	1	0	0
T51	0	2	0	0
T76	0	6	0	0
T127	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	358	0	0
T2	33179	6	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	2	0	0
T9	608	0	0	0
T10	0	2	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T32	0	1	0	0
T42	0	1	0	0
T51	0	2	0	0
T76	0	6	0	0
T127	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	358	0	0
T2	33179	6	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	2	0	0
T9	608	0	0	0
T10	0	2	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T32	0	1	0	0
T42	0	1	0	0
T51	0	2	0	0
T76	0	6	0	0
T127	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	13826	0	0
T2	33179	126	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	106	0	0
T9	608	0	0	0
T10	0	112	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T29	0	120	0	0
T30	0	67	0	0
T32	0	50	0	0
T42	0	59	0	0
T51	0	120	0	0
T76	0	22	0	0
T127	0	21	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	331	0	0
T2	33179	6	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T10	0	2	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T32	0	1	0	0
T42	0	1	0	0
T51	0	2	0	0
T76	0	5	0	0
T82	0	1	0	0
T127	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T16,T8
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T13,T16,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T13,T16,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T13,T16,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T16,T8
1	0	Covered	T16,T8,T10
1	1	Covered	T13,T16,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T8
0	1	Covered	T13,T10,T41
1	0	Covered	T10,T91,T82

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T8,T38
0	1	Covered	T16,T8,T38
1	0	Covered	T82,T83,T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T8,T38
1	-	Covered	T16,T8,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T16,T8
DetectSt	168	Covered	T13,T16,T8
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T16,T8,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T16,T8
DebounceSt->IdleSt	163	Covered	T215,T78,T50
DetectSt->IdleSt	186	Covered	T13,T10,T41
DetectSt->StableSt	191	Covered	T16,T8,T38
IdleSt->DebounceSt	148	Covered	T13,T16,T8
StableSt->IdleSt	206	Covered	T16,T8,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T16,T8
0	1	Covered	T13,T16,T8
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T16,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T13,T16,T8
IdleSt	0	-	-	-	-	-	-	Covered	T13,T16,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T16,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T215,T78,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T16,T8
DetectSt	-	-	-	-	1	-	-	Covered	T13,T10,T41
DetectSt	-	-	-	-	0	1	-	Covered	T16,T8,T38
DetectSt	-	-	-	-	0	0	-	Covered	T13,T16,T8
StableSt	-	-	-	-	-	-	1	Covered	T16,T8,T38
StableSt	-	-	-	-	-	-	0	Covered	T16,T8,T38
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	3128	0	0
CntIncr_A	8235605	113338	0	0
CntNoWrap_A	8235605	7594917	0	0
DetectStDropOut_A	8235605	496	0	0
DetectedOut_A	8235605	67106	0	0
DetectedPulseOut_A	8235605	828	0	0
DisabledIdleSt_A	8235605	7144653	0	0
DisabledNoDetection_A	8235605	7146826	0	0
EnterDebounceSt_A	8235605	1578	0	0
EnterDetectSt_A	8235605	1550	0	0
EnterStableSt_A	8235605	828	0	0
PulseIsPulse_A	8235605	828	0	0
StayInStableSt	8235605	66181	0	0
gen_high_event_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_high_level_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	720	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	3128	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	24	0	0
T9	608	0	0	0
T10	0	50	0	0
T13	5766	24	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	54	0	0
T28	0	50	0	0
T29	0	50	0	0
T30	0	44	0	0
T38	0	46	0	0
T41	0	46	0	0
T42	0	22	0	0
T49	658	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	113338	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	1008	0	0
T9	608	0	0	0
T10	0	1043	0	0
T13	5766	749	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	1809	0	0
T28	0	1525	0	0
T29	0	2075	0	0
T30	0	1672	0	0
T38	0	1587	0	0
T41	0	1013	0	0
T42	0	605	0	0
T49	658	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7594917	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5341	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	496	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T10	0	6	0	0
T13	5766	12	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T41	0	23	0	0
T49	658	0	0	0
T83	0	14	0	0
T91	0	10	0	0
T96	0	19	0	0
T115	0	6	0	0
T247	0	7	0	0
T266	0	26	0	0
T268	0	19	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	67106	0	0
T8	22766	1586	0	0
T9	608	0	0	0
T16	19907	1013	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	1164	0	0
T29	0	1990	0	0
T30	0	1332	0	0
T38	0	1872	0	0
T42	0	101	0	0
T49	658	0	0	0
T51	0	1631	0	0
T64	502	0	0	0
T82	0	3	0	0
T93	421	0	0	0
T95	0	1843	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	828	0	0
T8	22766	12	0	0
T9	608	0	0	0
T16	19907	27	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	25	0	0
T29	0	25	0	0
T30	0	22	0	0
T38	0	23	0	0
T42	0	11	0	0
T49	658	0	0	0
T51	0	14	0	0
T64	502	0	0	0
T82	0	3	0	0
T93	421	0	0	0
T95	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7144653	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	2014	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7146826	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	2014	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	1578	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	12	0	0
T9	608	0	0	0
T10	0	25	0	0
T13	5766	12	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	27	0	0
T28	0	25	0	0
T29	0	25	0	0
T30	0	22	0	0
T38	0	23	0	0
T41	0	23	0	0
T42	0	11	0	0
T49	658	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	1550	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	12	0	0
T9	608	0	0	0
T10	0	25	0	0
T13	5766	12	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	27	0	0
T28	0	25	0	0
T29	0	25	0	0
T30	0	22	0	0
T38	0	23	0	0
T41	0	23	0	0
T42	0	11	0	0
T49	658	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	828	0	0
T8	22766	12	0	0
T9	608	0	0	0
T16	19907	27	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	25	0	0
T29	0	25	0	0
T30	0	22	0	0
T38	0	23	0	0
T42	0	11	0	0
T49	658	0	0	0
T51	0	14	0	0
T64	502	0	0	0
T82	0	3	0	0
T93	421	0	0	0
T95	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	828	0	0
T8	22766	12	0	0
T9	608	0	0	0
T16	19907	27	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	25	0	0
T29	0	25	0	0
T30	0	22	0	0
T38	0	23	0	0
T42	0	11	0	0
T49	658	0	0	0
T51	0	14	0	0
T64	502	0	0	0
T82	0	3	0	0
T93	421	0	0	0
T95	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	66181	0	0
T8	22766	1573	0	0
T9	608	0	0	0
T16	19907	984	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	1137	0	0
T29	0	1962	0	0
T30	0	1305	0	0
T38	0	1849	0	0
T42	0	90	0	0
T49	658	0	0	0
T51	0	1613	0	0
T64	502	0	0	0
T93	421	0	0	0
T95	0	1817	0	0
T128	0	64	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	720	0	0
T8	22766	11	0	0
T9	608	0	0	0
T16	19907	25	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	23	0	0
T29	0	22	0	0
T30	0	17	0	0
T38	0	23	0	0
T42	0	11	0	0
T49	658	0	0	0
T51	0	10	0	0
T64	502	0	0	0
T93	421	0	0	0
T95	0	26	0	0
T128	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T13,T16
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T16
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T16,T8,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T16,T8,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T16,T8,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T16,T8
1	0	Covered	T2,T13,T6
1	1	Covered	T16,T8,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T8,T28
0	1	Covered	T76,T100,T101
1	0	Covered	T78,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T8,T28
0	1	Covered	T28,T30,T29
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T8,T28
1	-	Covered	T28,T30,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T8,T28
DetectSt	168	Covered	T16,T8,T28
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T16,T8,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T8,T28
DebounceSt->IdleSt	163	Covered	T51,T32,T95
DetectSt->IdleSt	186	Covered	T76,T100,T78
DetectSt->StableSt	191	Covered	T16,T8,T28
IdleSt->DebounceSt	148	Covered	T16,T8,T28
StableSt->IdleSt	206	Covered	T16,T8,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T8,T28
0	1	Covered	T16,T8,T28
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T8,T28
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T8,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T8,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T51,T32,T95
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T8,T28
DetectSt	-	-	-	-	1	-	-	Covered	T76,T100,T78
DetectSt	-	-	-	-	0	1	-	Covered	T16,T8,T28
DetectSt	-	-	-	-	0	0	-	Covered	T16,T8,T28
StableSt	-	-	-	-	-	-	1	Covered	T28,T30,T29
StableSt	-	-	-	-	-	-	0	Covered	T16,T8,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	786	0	0
CntIncr_A	8235605	47134	0	0
CntNoWrap_A	8235605	7597259	0	0
DetectStDropOut_A	8235605	63	0	0
DetectedOut_A	8235605	12886	0	0
DetectedPulseOut_A	8235605	306	0	0
DisabledIdleSt_A	8235605	7224555	0	0
DisabledNoDetection_A	8235605	7226212	0	0
EnterDebounceSt_A	8235605	414	0	0
EnterDetectSt_A	8235605	374	0	0
EnterStableSt_A	8235605	306	0	0
PulseIsPulse_A	8235605	306	0	0
StayInStableSt	8235605	12545	0	0
gen_high_level_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	269	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	786	0	0
T8	22766	2	0	0
T9	608	0	0	0
T16	19907	4	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	4	0	0
T29	0	8	0	0
T30	0	10	0	0
T32	0	5	0	0
T49	658	0	0	0
T51	0	9	0	0
T64	502	0	0	0
T76	0	2	0	0
T93	421	0	0	0
T95	0	1	0	0
T127	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	47134	0	0
T8	22766	60	0	0
T9	608	0	0	0
T16	19907	86	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	104	0	0
T29	0	264	0	0
T30	0	400	0	0
T32	0	294	0	0
T49	658	0	0	0
T51	0	248	0	0
T64	502	0	0	0
T76	0	31	0	0
T93	421	0	0	0
T95	0	34	0	0
T127	0	327	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597259	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	63	0	0
T46	699	0	0	0
T62	491	0	0	0
T76	17858	1	0	0
T81	0	5	0	0
T100	0	3	0	0
T101	0	11	0	0
T186	502	0	0	0
T201	0	1	0	0
T260	0	13	0	0
T276	0	12	0	0
T277	0	1	0	0
T278	0	6	0	0
T279	0	6	0	0
T280	422	0	0	0
T281	419	0	0	0
T282	413	0	0	0
T283	848	0	0	0
T284	502	0	0	0
T285	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	12886	0	0
T8	22766	68	0	0
T9	608	0	0	0
T16	19907	70	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	130	0	0
T29	0	206	0	0
T30	0	215	0	0
T31	0	33	0	0
T32	0	189	0	0
T49	658	0	0	0
T51	0	171	0	0
T64	502	0	0	0
T93	421	0	0	0
T110	0	150	0	0
T127	0	192	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	306	0	0
T8	22766	1	0	0
T9	608	0	0	0
T16	19907	2	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	2	0	0
T29	0	4	0	0
T30	0	5	0	0
T31	0	2	0	0
T32	0	2	0	0
T49	658	0	0	0
T51	0	4	0	0
T64	502	0	0	0
T93	421	0	0	0
T110	0	2	0	0
T127	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7224555	0	0
T1	1121	720	0	0
T2	33179	28203	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7226212	0	0
T1	1121	721	0	0
T2	33179	28203	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	414	0	0
T8	22766	1	0	0
T9	608	0	0	0
T16	19907	2	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	2	0	0
T29	0	4	0	0
T30	0	5	0	0
T32	0	3	0	0
T49	658	0	0	0
T51	0	5	0	0
T64	502	0	0	0
T76	0	1	0	0
T93	421	0	0	0
T95	0	1	0	0
T127	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	374	0	0
T8	22766	1	0	0
T9	608	0	0	0
T16	19907	2	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	2	0	0
T29	0	4	0	0
T30	0	5	0	0
T32	0	2	0	0
T49	658	0	0	0
T51	0	4	0	0
T64	502	0	0	0
T76	0	1	0	0
T93	421	0	0	0
T110	0	2	0	0
T127	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	306	0	0
T8	22766	1	0	0
T9	608	0	0	0
T16	19907	2	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	2	0	0
T29	0	4	0	0
T30	0	5	0	0
T31	0	2	0	0
T32	0	2	0	0
T49	658	0	0	0
T51	0	4	0	0
T64	502	0	0	0
T93	421	0	0	0
T110	0	2	0	0
T127	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	306	0	0
T8	22766	1	0	0
T9	608	0	0	0
T16	19907	2	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	2	0	0
T29	0	4	0	0
T30	0	5	0	0
T31	0	2	0	0
T32	0	2	0	0
T49	658	0	0	0
T51	0	4	0	0
T64	502	0	0	0
T93	421	0	0	0
T110	0	2	0	0
T127	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	12545	0	0
T8	22766	66	0	0
T9	608	0	0	0
T16	19907	66	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	128	0	0
T29	0	202	0	0
T30	0	210	0	0
T31	0	31	0	0
T32	0	187	0	0
T49	658	0	0	0
T51	0	164	0	0
T64	502	0	0	0
T93	421	0	0	0
T110	0	148	0	0
T127	0	189	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	269	0	0
T28	12283	2	0	0
T29	0	3	0	0
T30	19357	5	0	0
T31	0	2	0	0
T32	0	2	0	0
T40	707	0	0	0
T41	4817	0	0	0
T51	0	1	0	0
T67	502	0	0	0
T68	502	0	0	0
T77	0	2	0	0
T97	0	1	0	0
T110	0	2	0	0
T127	0	3	0	0
T129	424	0	0	0
T130	406	0	0	0
T286	409	0	0	0
T287	747	0	0	0