Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T16,T8
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T13,T16,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T13,T16,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T13,T16,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T16,T8
1	0	Covered	T16,T8,T10
1	1	Covered	T13,T16,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T8
0	1	Covered	T13,T38,T41
1	0	Covered	T38,T29,T51

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T8,T10
0	1	Covered	T16,T8,T10
1	0	Covered	T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T8,T10
1	-	Covered	T16,T8,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T16,T8
DetectSt	168	Covered	T13,T16,T8
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T16,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T16,T8
DebounceSt->IdleSt	163	Covered	T215,T78,T50
DetectSt->IdleSt	186	Covered	T13,T38,T41
DetectSt->StableSt	191	Covered	T16,T8,T10
IdleSt->DebounceSt	148	Covered	T13,T16,T8
StableSt->IdleSt	206	Covered	T16,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T16,T8
0	1	Covered	T13,T16,T8
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T16,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T13,T16,T8
IdleSt	0	-	-	-	-	-	-	Covered	T13,T16,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T16,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T215,T78,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T16,T8
DetectSt	-	-	-	-	1	-	-	Covered	T13,T38,T41
DetectSt	-	-	-	-	0	1	-	Covered	T16,T8,T10
DetectSt	-	-	-	-	0	0	-	Covered	T13,T16,T8
StableSt	-	-	-	-	-	-	1	Covered	T16,T8,T10
StableSt	-	-	-	-	-	-	0	Covered	T16,T8,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	2978	0	0
CntIncr_A	8235605	109633	0	0
CntNoWrap_A	8235605	7595067	0	0
DetectStDropOut_A	8235605	408	0	0
DetectedOut_A	8235605	82655	0	0
DetectedPulseOut_A	8235605	922	0	0
DisabledIdleSt_A	8235605	7130986	0	0
DisabledNoDetection_A	8235605	7133152	0	0
EnterDebounceSt_A	8235605	1504	0	0
EnterDetectSt_A	8235605	1474	0	0
EnterStableSt_A	8235605	922	0	0
PulseIsPulse_A	8235605	922	0	0
StayInStableSt	8235605	81629	0	0
gen_high_event_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_high_level_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	817	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	2978	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	56	0	0
T9	608	0	0	0
T10	0	26	0	0
T13	5766	28	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	8	0	0
T28	0	34	0	0
T29	0	30	0	0
T30	0	16	0	0
T38	0	58	0	0
T41	0	28	0	0
T42	0	20	0	0
T49	658	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	109633	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	2492	0	0
T9	608	0	0	0
T10	0	520	0	0
T13	5766	873	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	296	0	0
T28	0	816	0	0
T29	0	1883	0	0
T30	0	376	0	0
T38	0	2307	0	0
T41	0	608	0	0
T42	0	450	0	0
T49	658	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7595067	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5337	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	408	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T13	5766	14	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T38	0	13	0	0
T41	0	14	0	0
T49	658	0	0	0
T91	0	10	0	0
T96	0	27	0	0
T247	0	4	0	0
T266	0	6	0	0
T268	0	5	0	0
T272	0	8	0	0
T288	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	82655	0	0
T8	22766	3763	0	0
T9	608	0	0	0
T10	0	976	0	0
T16	19907	9	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	713	0	0
T30	0	781	0	0
T42	0	194	0	0
T49	658	0	0	0
T64	502	0	0	0
T82	0	3863	0	0
T83	0	1667	0	0
T93	421	0	0	0
T95	0	1073	0	0
T128	0	2460	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	922	0	0
T8	22766	28	0	0
T9	608	0	0	0
T10	0	13	0	0
T16	19907	4	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	17	0	0
T30	0	8	0	0
T42	0	10	0	0
T49	658	0	0	0
T64	502	0	0	0
T82	0	24	0	0
T83	0	26	0	0
T93	421	0	0	0
T95	0	24	0	0
T128	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7130986	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	2014	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7133152	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	2014	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	1504	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	28	0	0
T9	608	0	0	0
T10	0	13	0	0
T13	5766	14	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	4	0	0
T28	0	17	0	0
T29	0	15	0	0
T30	0	8	0	0
T38	0	29	0	0
T41	0	14	0	0
T42	0	10	0	0
T49	658	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	1474	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	28	0	0
T9	608	0	0	0
T10	0	13	0	0
T13	5766	14	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	4	0	0
T28	0	17	0	0
T29	0	15	0	0
T30	0	8	0	0
T38	0	29	0	0
T41	0	14	0	0
T42	0	10	0	0
T49	658	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	922	0	0
T8	22766	28	0	0
T9	608	0	0	0
T10	0	13	0	0
T16	19907	4	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	17	0	0
T30	0	8	0	0
T42	0	10	0	0
T49	658	0	0	0
T64	502	0	0	0
T82	0	24	0	0
T83	0	26	0	0
T93	421	0	0	0
T95	0	24	0	0
T128	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	922	0	0
T8	22766	28	0	0
T9	608	0	0	0
T10	0	13	0	0
T16	19907	4	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	17	0	0
T30	0	8	0	0
T42	0	10	0	0
T49	658	0	0	0
T64	502	0	0	0
T82	0	24	0	0
T83	0	26	0	0
T93	421	0	0	0
T95	0	24	0	0
T128	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	81629	0	0
T8	22766	3732	0	0
T9	608	0	0	0
T10	0	961	0	0
T16	19907	5	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	695	0	0
T30	0	770	0	0
T42	0	184	0	0
T49	658	0	0	0
T64	502	0	0	0
T82	0	3838	0	0
T83	0	1641	0	0
T93	421	0	0	0
T95	0	1049	0	0
T128	0	2435	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	817	0	0
T8	22766	25	0	0
T9	608	0	0	0
T10	0	11	0	0
T16	19907	4	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T28	0	16	0	0
T30	0	5	0	0
T42	0	10	0	0
T49	658	0	0	0
T64	502	0	0	0
T82	0	23	0	0
T83	0	26	0	0
T93	421	0	0	0
T95	0	24	0	0
T128	0	21	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T13,T16
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T16
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T16,T8
1	0	Covered	T2,T13,T6
1	1	Covered	T2,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T10
0	1	Covered	T98,T213,T78
1	0	Covered	T78,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T10
0	1	Covered	T2,T8,T10
1	0	Covered	T78,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T10
1	-	Covered	T2,T8,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T10
DetectSt	168	Covered	T2,T8,T10
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T10
DebounceSt->IdleSt	163	Covered	T2,T32,T115
DetectSt->IdleSt	186	Covered	T98,T213,T78
DetectSt->StableSt	191	Covered	T2,T8,T10
IdleSt->DebounceSt	148	Covered	T2,T8,T10
StableSt->IdleSt	206	Covered	T2,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T10
0	1	Covered	T2,T8,T10
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T10
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T32,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T98,T213,T78
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T10
DetectSt	-	-	-	-	0	0	-	Covered	T2,T8,T10
StableSt	-	-	-	-	-	-	1	Covered	T2,T8,T10
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	866	0	0
CntIncr_A	8235605	50172	0	0
CntNoWrap_A	8235605	7597179	0	0
DetectStDropOut_A	8235605	29	0	0
DetectedOut_A	8235605	16562	0	0
DetectedPulseOut_A	8235605	373	0	0
DisabledIdleSt_A	8235605	7209955	0	0
DisabledNoDetection_A	8235605	7211597	0	0
EnterDebounceSt_A	8235605	461	0	0
EnterDetectSt_A	8235605	406	0	0
EnterStableSt_A	8235605	373	0	0
PulseIsPulse_A	8235605	373	0	0
StayInStableSt	8235605	16163	0	0
gen_high_level_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	343	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	866	0	0
T2	33179	17	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	4	0	0
T9	608	0	0	0
T10	0	4	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T32	0	15	0	0
T55	0	2	0	0
T76	0	12	0	0
T82	0	6	0	0
T83	0	2	0	0
T127	0	2	0	0
T128	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	50172	0	0
T2	33179	993	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	172	0	0
T9	608	0	0	0
T10	0	86	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T32	0	1386	0	0
T55	0	90	0	0
T76	0	150	0	0
T82	0	219	0	0
T83	0	46	0	0
T127	0	100	0	0
T128	0	132	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597179	0	0
T1	1121	720	0	0
T2	33179	32670	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	29	0	0
T72	7179	0	0	0
T78	0	1	0	0
T98	104669	4	0	0
T99	34355	0	0	0
T213	0	2	0	0
T233	0	10	0	0
T266	5120	0	0	0
T279	0	6	0	0
T289	0	4	0	0
T290	0	1	0	0
T291	0	1	0	0
T292	2863	0	0	0
T293	412	0	0	0
T294	670	0	0	0
T295	648	0	0	0
T296	522	0	0	0
T297	702	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	16562	0	0
T2	33179	293	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	86	0	0
T9	608	0	0	0
T10	0	167	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T32	0	67	0	0
T55	0	66	0	0
T76	0	34	0	0
T82	0	649	0	0
T83	0	57	0	0
T127	0	73	0	0
T128	0	159	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	373	0	0
T2	33179	8	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	2	0	0
T9	608	0	0	0
T10	0	2	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T32	0	6	0	0
T55	0	1	0	0
T76	0	6	0	0
T82	0	3	0	0
T83	0	1	0	0
T127	0	1	0	0
T128	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7209955	0	0
T1	1121	720	0	0
T2	33179	28203	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7211597	0	0
T1	1121	721	0	0
T2	33179	28203	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	461	0	0
T2	33179	9	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	2	0	0
T9	608	0	0	0
T10	0	2	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T32	0	9	0	0
T55	0	1	0	0
T76	0	6	0	0
T82	0	3	0	0
T83	0	1	0	0
T127	0	1	0	0
T128	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	406	0	0
T2	33179	8	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	2	0	0
T9	608	0	0	0
T10	0	2	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T32	0	6	0	0
T55	0	1	0	0
T76	0	6	0	0
T82	0	3	0	0
T83	0	1	0	0
T127	0	1	0	0
T128	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	373	0	0
T2	33179	8	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	2	0	0
T9	608	0	0	0
T10	0	2	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T32	0	6	0	0
T55	0	1	0	0
T76	0	6	0	0
T82	0	3	0	0
T83	0	1	0	0
T127	0	1	0	0
T128	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	373	0	0
T2	33179	8	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	2	0	0
T9	608	0	0	0
T10	0	2	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T32	0	6	0	0
T55	0	1	0	0
T76	0	6	0	0
T82	0	3	0	0
T83	0	1	0	0
T127	0	1	0	0
T128	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	16163	0	0
T2	33179	285	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	84	0	0
T9	608	0	0	0
T10	0	165	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T32	0	61	0	0
T55	0	65	0	0
T76	0	28	0	0
T82	0	646	0	0
T83	0	56	0	0
T127	0	72	0	0
T128	0	157	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	343	0	0
T2	33179	8	0	0
T3	1059	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	2	0	0
T9	608	0	0	0
T10	0	2	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T32	0	6	0	0
T55	0	1	0	0
T76	0	5	0	0
T82	0	3	0	0
T83	0	1	0	0
T127	0	1	0	0
T128	0	2	0	0