Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T14
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T14
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T3,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T3,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T3,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T3
1	0	Covered	T1,T6,T14
1	1	Covered	T1,T3,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T91,T93,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T8
1	-	Covered	T1,T3,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T8
DetectSt	168	Covered	T1,T3,T8
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T3,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T8
DebounceSt->IdleSt	163	Covered	T9,T35,T37
DetectSt->IdleSt	186	Covered	T91,T93,T96
DetectSt->StableSt	191	Covered	T1,T3,T8
IdleSt->DebounceSt	148	Covered	T1,T3,T8
StableSt->IdleSt	206	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T35,T37
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T8
DetectSt	-	-	-	-	1	-	-	Covered	T91,T93,T96
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	266	0	0
CntIncr_A	7216696	113666	0	0
CntNoWrap_A	7216696	6550377	0	0
DetectStDropOut_A	7216696	4	0	0
DetectedOut_A	7216696	852	0	0
DetectedPulseOut_A	7216696	120	0	0
DisabledIdleSt_A	7216696	6430730	0	0
DisabledNoDetection_A	7216696	6433147	0	0
EnterDebounceSt_A	7216696	148	0	0
EnterDetectSt_A	7216696	124	0	0
EnterStableSt_A	7216696	120	0	0
PulseIsPulse_A	7216696	120	0	0
StayInStableSt	7216696	732	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7216696	6880	0	0
gen_low_level_sva.LowLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	120	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	266	0	0
T1	64534	4	0	0
T2	1898	0	0	0
T3	3483	2	0	0
T4	12671	0	0	0
T6	502	0	0	0
T8	0	2	0	0
T9	0	7	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T35	0	1	0	0
T36	0	4	0	0
T37	0	3	0	0
T40	0	2	0	0
T44	0	4	0	0
T59	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	113666	0	0
T1	64534	83	0	0
T2	1898	0	0	0
T3	3483	87	0	0
T4	12671	0	0	0
T6	502	0	0	0
T8	0	89	0	0
T9	0	206	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T35	0	48	0	0
T36	0	178	0	0
T37	0	20	0	0
T40	0	14	0	0
T44	0	48427	0	0
T59	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6550377	0	0
T1	64534	61970	0	0
T2	1898	1497	0	0
T3	3483	1076	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	4	0	0
T91	8059	1	0	0
T93	0	1	0	0
T96	0	1	0	0
T99	0	1	0	0
T104	19093	0	0	0
T105	192365	0	0	0
T106	1970	0	0	0
T107	509	0	0	0
T108	15049	0	0	0
T109	20944	0	0	0
T110	745	0	0	0
T111	2327	0	0	0
T112	688	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	852	0	0
T1	64534	23	0	0
T2	1898	0	0	0
T3	3483	8	0	0
T4	12671	0	0	0
T6	502	0	0	0
T8	0	7	0	0
T9	0	22	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T36	0	14	0	0
T37	0	2	0	0
T40	0	4	0	0
T44	0	10	0	0
T59	0	3	0	0
T114	0	2	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	120	0	0
T1	64534	2	0	0
T2	1898	0	0	0
T3	3483	1	0	0
T4	12671	0	0	0
T6	502	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T44	0	2	0	0
T59	0	1	0	0
T114	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6430730	0	0
T1	64534	61783	0	0
T2	1898	1497	0	0
T3	3483	950	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1271	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6433147	0	0
T1	64534	61808	0	0
T2	1898	1498	0	0
T3	3483	955	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1279	0	0
T16	22713	22274	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	148	0	0
T1	64534	2	0	0
T2	1898	0	0	0
T3	3483	1	0	0
T4	12671	0	0	0
T6	502	0	0	0
T8	0	1	0	0
T9	0	4	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	2	0	0
T40	0	1	0	0
T44	0	2	0	0
T59	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	124	0	0
T1	64534	2	0	0
T2	1898	0	0	0
T3	3483	1	0	0
T4	12671	0	0	0
T6	502	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T44	0	2	0	0
T59	0	1	0	0
T114	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	120	0	0
T1	64534	2	0	0
T2	1898	0	0	0
T3	3483	1	0	0
T4	12671	0	0	0
T6	502	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T44	0	2	0	0
T59	0	1	0	0
T114	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	120	0	0
T1	64534	2	0	0
T2	1898	0	0	0
T3	3483	1	0	0
T4	12671	0	0	0
T6	502	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T44	0	2	0	0
T59	0	1	0	0
T114	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	732	0	0
T1	64534	21	0	0
T2	1898	0	0	0
T3	3483	7	0	0
T4	12671	0	0	0
T6	502	0	0	0
T8	0	6	0	0
T9	0	19	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T36	0	12	0	0
T37	0	1	0	0
T40	0	3	0	0
T44	0	8	0	0
T59	0	2	0	0
T114	0	1	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6880	0	0
T1	64534	40	0	0
T2	1898	5	0	0
T3	3483	14	0	0
T4	12671	28	0	0
T6	502	6	0	0
T13	402	0	0	0
T14	437	3	0	0
T15	4238	0	0	0
T16	22713	40	0	0
T17	415	0	0	0
T24	0	5	0	0
T25	0	25	0	0
T45	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	120	0	0
T1	64534	2	0	0
T2	1898	0	0	0
T3	3483	1	0	0
T4	12671	0	0	0
T6	502	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T44	0	2	0	0
T59	0	1	0	0
T114	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T14
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T14
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T9,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T2,T9,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T50,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T21
1	0	Covered	T1,T6,T14
1	1	Covered	T2,T9,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T50,T33
0	1	Covered	T77,T81,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T50,T33
0	1	Unreachable
1	0	Covered	T2,T50,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T21
DetectSt	168	Covered	T2,T50,T33
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T50,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T50,T33
DebounceSt->IdleSt	163	Covered	T9,T21,T53
DetectSt->IdleSt	186	Covered	T77,T81,T82
DetectSt->StableSt	191	Covered	T2,T50,T33
IdleSt->DebounceSt	148	Covered	T2,T9,T21
StableSt->IdleSt	206	Covered	T2,T50,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T21
0	1	Covered	T2,T9,T21
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T50,T33
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T21
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T50,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T21,T53
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T21
DetectSt	-	-	-	-	1	-	-	Covered	T77,T81,T82
DetectSt	-	-	-	-	0	1	-	Covered	T2,T50,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T50,T33
StableSt	-	-	-	-	-	-	0	Covered	T2,T50,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	188	0	0
CntIncr_A	7216696	288627	0	0
CntNoWrap_A	7216696	6550455	0	0
DetectStDropOut_A	7216696	9	0	0
DetectedOut_A	7216696	33096	0	0
DetectedPulseOut_A	7216696	55	0	0
DisabledIdleSt_A	7216696	5327598	0	0
DisabledNoDetection_A	7216696	5330062	0	0
EnterDebounceSt_A	7216696	124	0	0
EnterDetectSt_A	7216696	64	0	0
EnterStableSt_A	7216696	55	0	0
PulseIsPulse_A	7216696	55	0	0
StayInStableSt	7216696	33041	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7216696	6880	0	0
gen_low_level_sva.LowLevelEvent_A	7216696	6553108	0	0
gen_sticky_sva.StableStDropOut_A	7216696	623868	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	188	0	0
T2	1898	4	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T9	0	8	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	1	0	0
T24	522	0	0	0
T25	7798	0	0	0
T33	0	2	0	0
T45	442	0	0	0
T50	0	4	0	0
T51	0	2	0	0
T53	0	2	0	0
T65	0	4	0	0
T66	0	8	0	0
T67	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	288627	0	0
T2	1898	180	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T9	0	600	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	98	0	0
T24	522	0	0	0
T25	7798	0	0	0
T33	0	73	0	0
T45	442	0	0	0
T50	0	46	0	0
T51	0	11	0	0
T53	0	17704	0	0
T65	0	58	0	0
T66	0	760	0	0
T67	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6550455	0	0
T1	64534	61974	0	0
T2	1898	1493	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	9	0	0
T77	87974	2	0	0
T81	0	3	0	0
T82	0	1	0	0
T120	0	3	0	0
T121	10897	0	0	0
T122	486	0	0	0
T123	524	0	0	0
T124	530	0	0	0
T125	6197	0	0	0
T126	13004	0	0	0
T127	292949	0	0	0
T128	18484	0	0	0
T129	1073	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	33096	0	0
T2	1898	673	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T33	0	453	0	0
T45	442	0	0	0
T50	0	198	0	0
T51	0	42	0	0
T65	0	195	0	0
T67	0	286	0	0
T72	0	40	0	0
T83	0	533	0	0
T115	0	368	0	0
T116	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	55	0	0
T2	1898	2	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T33	0	1	0	0
T45	442	0	0	0
T50	0	2	0	0
T51	0	1	0	0
T65	0	2	0	0
T67	0	1	0	0
T72	0	1	0	0
T83	0	2	0	0
T115	0	1	0	0
T116	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	5327598	0	0
T1	64534	61974	0	0
T2	1898	51	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	5330062	0	0
T1	64534	62000	0	0
T2	1898	52	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	124	0	0
T2	1898	2	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T9	0	8	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	1	0	0
T24	522	0	0	0
T25	7798	0	0	0
T33	0	1	0	0
T45	442	0	0	0
T50	0	2	0	0
T51	0	1	0	0
T53	0	2	0	0
T65	0	2	0	0
T66	0	8	0	0
T67	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	64	0	0
T2	1898	2	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T33	0	1	0	0
T45	442	0	0	0
T50	0	2	0	0
T51	0	1	0	0
T65	0	2	0	0
T67	0	1	0	0
T72	0	1	0	0
T83	0	2	0	0
T115	0	1	0	0
T116	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	55	0	0
T2	1898	2	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T33	0	1	0	0
T45	442	0	0	0
T50	0	2	0	0
T51	0	1	0	0
T65	0	2	0	0
T67	0	1	0	0
T72	0	1	0	0
T83	0	2	0	0
T115	0	1	0	0
T116	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	55	0	0
T2	1898	2	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T33	0	1	0	0
T45	442	0	0	0
T50	0	2	0	0
T51	0	1	0	0
T65	0	2	0	0
T67	0	1	0	0
T72	0	1	0	0
T83	0	2	0	0
T115	0	1	0	0
T116	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	33041	0	0
T2	1898	671	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T33	0	452	0	0
T45	442	0	0	0
T50	0	196	0	0
T51	0	41	0	0
T65	0	193	0	0
T67	0	285	0	0
T72	0	39	0	0
T83	0	531	0	0
T115	0	367	0	0
T116	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6880	0	0
T1	64534	40	0	0
T2	1898	5	0	0
T3	3483	14	0	0
T4	12671	28	0	0
T6	502	6	0	0
T13	402	0	0	0
T14	437	3	0	0
T15	4238	0	0	0
T16	22713	40	0	0
T17	415	0	0	0
T24	0	5	0	0
T25	0	25	0	0
T45	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	623868	0	0
T2	1898	328	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T33	0	26107	0	0
T45	442	0	0	0
T50	0	504	0	0
T51	0	391	0	0
T65	0	1179	0	0
T67	0	64	0	0
T72	0	66	0	0
T83	0	427	0	0
T115	0	22033	0	0
T116	0	29	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T14
1	1	Covered	T1,T6,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T9,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T2,T9,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T9,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T21
1	0	Covered	T1,T6,T14
1	1	Covered	T2,T9,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T21
0	1	Covered	T50,T66,T67
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T21
0	1	Unreachable
1	0	Covered	T2,T9,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T21
DetectSt	168	Covered	T2,T9,T21
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T9,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T21
DebounceSt->IdleSt	163	Covered	T50,T33,T66
DetectSt->IdleSt	186	Covered	T50,T66,T67
DetectSt->StableSt	191	Covered	T2,T9,T21
IdleSt->DebounceSt	148	Covered	T2,T9,T21
StableSt->IdleSt	206	Covered	T2,T9,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T21
0	1	Covered	T2,T9,T21
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T21
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T50,T33,T66
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T21
DetectSt	-	-	-	-	1	-	-	Covered	T50,T66,T67
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T21
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	217	0	0
CntIncr_A	7216696	186088	0	0
CntNoWrap_A	7216696	6550426	0	0
DetectStDropOut_A	7216696	24	0	0
DetectedOut_A	7216696	219531	0	0
DetectedPulseOut_A	7216696	59	0	0
DisabledIdleSt_A	7216696	5327598	0	0
DisabledNoDetection_A	7216696	5330062	0	0
EnterDebounceSt_A	7216696	134	0	0
EnterDetectSt_A	7216696	83	0	0
EnterStableSt_A	7216696	59	0	0
PulseIsPulse_A	7216696	59	0	0
StayInStableSt	7216696	219472	0	0
gen_high_level_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_sticky_sva.StableStDropOut_A	7216696	596901	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	217	0	0
T2	1898	4	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T9	0	4	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	2	0	0
T24	522	0	0	0
T25	7798	0	0	0
T33	0	4	0	0
T45	442	0	0	0
T50	0	9	0	0
T51	0	2	0	0
T53	0	2	0	0
T65	0	4	0	0
T66	0	15	0	0
T67	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	186088	0	0
T2	1898	150	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T9	0	107	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	95	0	0
T24	522	0	0	0
T25	7798	0	0	0
T33	0	26544	0	0
T45	442	0	0	0
T50	0	395	0	0
T51	0	58	0	0
T53	0	54	0	0
T65	0	76	0	0
T66	0	448	0	0
T67	0	294	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6550426	0	0
T1	64534	61974	0	0
T2	1898	1493	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	24	0	0
T30	2565	0	0	0
T33	117463	0	0	0
T50	1227	2	0	0
T51	894	0	0	0
T52	1510	0	0	0
T54	501	0	0	0
T66	0	6	0	0
T67	0	2	0	0
T78	0	2	0	0
T81	0	2	0	0
T100	23786	0	0	0
T101	509	0	0	0
T102	502	0	0	0
T103	423	0	0	0
T115	0	1	0	0
T130	0	2	0	0
T131	0	2	0	0
T132	0	3	0	0
T133	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	219531	0	0
T2	1898	580	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T9	0	491	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	32	0	0
T24	522	0	0	0
T25	7798	0	0	0
T45	442	0	0	0
T50	0	160	0	0
T51	0	164	0	0
T53	0	108	0	0
T65	0	512	0	0
T66	0	1	0	0
T83	0	527	0	0
T115	0	13447	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	59	0	0
T2	1898	2	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T9	0	2	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	1	0	0
T24	522	0	0	0
T25	7798	0	0	0
T45	442	0	0	0
T50	0	2	0	0
T51	0	1	0	0
T53	0	1	0	0
T65	0	2	0	0
T66	0	1	0	0
T83	0	2	0	0
T115	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	5327598	0	0
T1	64534	61974	0	0
T2	1898	51	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	5330062	0	0
T1	64534	62000	0	0
T2	1898	52	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	134	0	0
T2	1898	2	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T9	0	2	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	1	0	0
T24	522	0	0	0
T25	7798	0	0	0
T33	0	4	0	0
T45	442	0	0	0
T50	0	5	0	0
T51	0	1	0	0
T53	0	1	0	0
T65	0	2	0	0
T66	0	8	0	0
T67	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	83	0	0
T2	1898	2	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T9	0	2	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	1	0	0
T24	522	0	0	0
T25	7798	0	0	0
T45	442	0	0	0
T50	0	4	0	0
T51	0	1	0	0
T53	0	1	0	0
T65	0	2	0	0
T66	0	7	0	0
T67	0	2	0	0
T115	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	59	0	0
T2	1898	2	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T9	0	2	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	1	0	0
T24	522	0	0	0
T25	7798	0	0	0
T45	442	0	0	0
T50	0	2	0	0
T51	0	1	0	0
T53	0	1	0	0
T65	0	2	0	0
T66	0	1	0	0
T83	0	2	0	0
T115	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	59	0	0
T2	1898	2	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T9	0	2	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	1	0	0
T24	522	0	0	0
T25	7798	0	0	0
T45	442	0	0	0
T50	0	2	0	0
T51	0	1	0	0
T53	0	1	0	0
T65	0	2	0	0
T66	0	1	0	0
T83	0	2	0	0
T115	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	219472	0	0
T2	1898	578	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T9	0	489	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	31	0	0
T24	522	0	0	0
T25	7798	0	0	0
T45	442	0	0	0
T50	0	158	0	0
T51	0	163	0	0
T53	0	107	0	0
T65	0	510	0	0
T83	0	525	0	0
T115	0	13446	0	0
T134	0	22	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	596901	0	0
T2	1898	692	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T9	0	625	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	26	0	0
T24	522	0	0	0
T25	7798	0	0	0
T45	442	0	0	0
T50	0	109	0	0
T51	0	209	0	0
T53	0	162471	0	0
T65	0	842	0	0
T66	0	86	0	0
T83	0	445	0	0
T115	0	67	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T9,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T2,T9,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T21,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T21
1	0	Covered	T1,T6,T14
1	1	Covered	T2,T9,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T21,T50
0	1	Covered	T76,T77,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T21,T50
0	1	Unreachable
1	0	Covered	T9,T21,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T21
DetectSt	168	Covered	T9,T21,T50
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T9,T21,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T21,T50
DebounceSt->IdleSt	163	Covered	T2,T83,T72
DetectSt->IdleSt	186	Covered	T76,T77,T78
DetectSt->StableSt	191	Covered	T9,T21,T50
IdleSt->DebounceSt	148	Covered	T2,T9,T21
StableSt->IdleSt	206	Covered	T9,T21,T50

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T21
0	1	Covered	T2,T9,T21
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T21,T50
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T21,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T83,T72
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T21
DetectSt	-	-	-	-	1	-	-	Covered	T76,T77,T78
DetectSt	-	-	-	-	0	1	-	Covered	T9,T21,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T21,T50
StableSt	-	-	-	-	-	-	0	Covered	T9,T21,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	203	0	0
CntIncr_A	7216696	333457	0	0
CntNoWrap_A	7216696	6550440	0	0
DetectStDropOut_A	7216696	19	0	0
DetectedOut_A	7216696	186029	0	0
DetectedPulseOut_A	7216696	63	0	0
DisabledIdleSt_A	7216696	5327598	0	0
DisabledNoDetection_A	7216696	5330062	0	0
EnterDebounceSt_A	7216696	121	0	0
EnterDetectSt_A	7216696	82	0	0
EnterStableSt_A	7216696	63	0	0
PulseIsPulse_A	7216696	63	0	0
StayInStableSt	7216696	185966	0	0
gen_high_event_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_high_level_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_sticky_sva.StableStDropOut_A	7216696	473956	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	203	0	0
T2	1898	6	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T9	0	4	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	2	0	0
T24	522	0	0	0
T25	7798	0	0	0
T33	0	2	0	0
T45	442	0	0	0
T50	0	4	0	0
T51	0	2	0	0
T53	0	2	0	0
T65	0	4	0	0
T66	0	6	0	0
T67	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	333457	0	0
T2	1898	390	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T9	0	56	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	74	0	0
T24	522	0	0	0
T25	7798	0	0	0
T33	0	96	0	0
T45	442	0	0	0
T50	0	56	0	0
T51	0	89	0	0
T53	0	51650	0	0
T65	0	196	0	0
T66	0	33	0	0
T67	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6550440	0	0
T1	64534	61974	0	0
T2	1898	1491	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	19	0	0
T76	816	2	0	0
T77	0	3	0	0
T78	0	2	0	0
T120	0	3	0	0
T135	0	2	0	0
T136	0	3	0	0
T137	0	1	0	0
T138	0	3	0	0
T139	676	0	0	0
T140	524	0	0	0
T141	1953	0	0	0
T142	582	0	0	0
T143	434	0	0	0
T144	27770	0	0	0
T145	843	0	0	0
T146	431	0	0	0
T147	495	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	186029	0	0
T9	23434	268	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T21	0	3	0	0
T33	0	361	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T50	0	293	0	0
T51	0	320	0	0
T53	0	99349	0	0
T65	0	1170	0	0
T66	0	68	0	0
T67	0	234	0	0
T115	0	293	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	63	0	0
T9	23434	2	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T21	0	1	0	0
T33	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T50	0	2	0	0
T51	0	1	0	0
T53	0	1	0	0
T65	0	2	0	0
T66	0	3	0	0
T67	0	1	0	0
T115	0	1	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	5327598	0	0
T1	64534	61974	0	0
T2	1898	51	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	5330062	0	0
T1	64534	62000	0	0
T2	1898	52	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	121	0	0
T2	1898	6	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T9	0	2	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	1	0	0
T24	522	0	0	0
T25	7798	0	0	0
T33	0	1	0	0
T45	442	0	0	0
T50	0	2	0	0
T51	0	1	0	0
T53	0	1	0	0
T65	0	2	0	0
T66	0	3	0	0
T67	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	82	0	0
T9	23434	2	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T21	0	1	0	0
T33	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T50	0	2	0	0
T51	0	1	0	0
T53	0	1	0	0
T65	0	2	0	0
T66	0	3	0	0
T67	0	1	0	0
T115	0	1	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	63	0	0
T9	23434	2	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T21	0	1	0	0
T33	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T50	0	2	0	0
T51	0	1	0	0
T53	0	1	0	0
T65	0	2	0	0
T66	0	3	0	0
T67	0	1	0	0
T115	0	1	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	63	0	0
T9	23434	2	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T21	0	1	0	0
T33	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T50	0	2	0	0
T51	0	1	0	0
T53	0	1	0	0
T65	0	2	0	0
T66	0	3	0	0
T67	0	1	0	0
T115	0	1	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	185966	0	0
T9	23434	266	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T21	0	2	0	0
T33	0	360	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T50	0	291	0	0
T51	0	319	0	0
T53	0	99348	0	0
T65	0	1168	0	0
T66	0	65	0	0
T67	0	233	0	0
T115	0	292	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	473956	0	0
T9	23434	927	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T21	0	84	0	0
T33	0	26197	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T50	0	416	0	0
T51	0	38	0	0
T53	0	11635	0	0
T65	0	99	0	0
T66	0	1010	0	0
T67	0	164	0	0
T115	0	22170	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T8,T9,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T8,T9,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T8,T9,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T21
1	0	Covered	T5,T1,T6
1	1	Covered	T8,T9,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T23
0	1	Covered	T79,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T23
0	1	Covered	T9,T23,T28
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T23
1	-	Covered	T9,T23,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T23
DetectSt	168	Covered	T8,T9,T23
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T8,T9,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T23
DebounceSt->IdleSt	163	Covered	T9,T69,T70
DetectSt->IdleSt	186	Covered	T79,T80
DetectSt->StableSt	191	Covered	T8,T9,T23
IdleSt->DebounceSt	148	Covered	T8,T9,T23
StableSt->IdleSt	206	Covered	T8,T9,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T23
0	1	Covered	T8,T9,T23
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T23
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T23
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T9
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T23
DetectSt	-	-	-	-	1	-	-	Covered	T79,T80
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T23,T28
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	77	0	0
CntIncr_A	7216696	18959	0	0
CntNoWrap_A	7216696	6550566	0	0
DetectStDropOut_A	7216696	2	0	0
DetectedOut_A	7216696	2383	0	0
DetectedPulseOut_A	7216696	35	0	0
DisabledIdleSt_A	7216696	6454517	0	0
DisabledNoDetection_A	7216696	6456933	0	0
EnterDebounceSt_A	7216696	40	0	0
EnterDetectSt_A	7216696	37	0	0
EnterStableSt_A	7216696	35	0	0
PulseIsPulse_A	7216696	35	0	0
StayInStableSt	7216696	2331	0	0
gen_high_level_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	77	0	0
T8	3902	2	0	0
T9	23434	3	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T23	0	2	0	0
T28	0	4	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	2	0	0
T117	426	0	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	4	0	0
T152	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	18959	0	0
T8	3902	17	0	0
T9	23434	134	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T23	0	49	0	0
T28	0	34	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	17	0	0
T117	426	0	0	0
T148	0	63	0	0
T149	0	51	0	0
T150	0	55	0	0
T151	0	88	0	0
T152	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6550566	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	2	0	0
T79	27622	1	0	0
T80	0	1	0	0
T133	172667	0	0	0
T153	24035	0	0	0
T154	451	0	0	0
T155	433	0	0	0
T156	522	0	0	0
T157	421	0	0	0
T158	504	0	0	0
T159	608	0	0	0
T160	12331	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	2383	0	0
T8	3902	46	0	0
T9	23434	50	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T23	0	22	0	0
T28	0	104	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	54	0	0
T117	426	0	0	0
T148	0	42	0	0
T149	0	43	0	0
T150	0	43	0	0
T151	0	244	0	0
T152	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	35	0	0
T8	3902	1	0	0
T9	23434	1	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T23	0	1	0	0
T28	0	2	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T117	426	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6454517	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6456933	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	40	0	0
T8	3902	1	0	0
T9	23434	2	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T23	0	1	0	0
T28	0	2	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T117	426	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	37	0	0
T8	3902	1	0	0
T9	23434	1	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T23	0	1	0	0
T28	0	2	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T117	426	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	35	0	0
T8	3902	1	0	0
T9	23434	1	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T23	0	1	0	0
T28	0	2	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T117	426	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	35	0	0
T8	3902	1	0	0
T9	23434	1	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T23	0	1	0	0
T28	0	2	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T117	426	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	2331	0	0
T8	3902	44	0	0
T9	23434	49	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T23	0	21	0	0
T28	0	101	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	52	0	0
T117	426	0	0	0
T148	0	40	0	0
T149	0	42	0	0
T150	0	42	0	0
T151	0	241	0	0
T152	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	18	0	0
T9	23434	1	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T23	0	1	0	0
T28	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T32,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T7,T9,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T32,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T32
1	0	Covered	T1,T6,T14
1	1	Covered	T7,T9,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T32,T23
0	1	Covered	T165,T166
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T32,T23
0	1	Covered	T7,T32,T23
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T32,T23
1	-	Covered	T7,T32,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T32
DetectSt	168	Covered	T7,T32,T23
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T7,T32,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T32,T23
DebounceSt->IdleSt	163	Covered	T9,T162,T167
DetectSt->IdleSt	186	Covered	T165,T166
DetectSt->StableSt	191	Covered	T7,T32,T23
IdleSt->DebounceSt	148	Covered	T7,T9,T32
StableSt->IdleSt	206	Covered	T7,T32,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T32,T23
0	1	Covered	T7,T9,T32
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T32,T23
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T32
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T32,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T162,T167,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T32
DetectSt	-	-	-	-	1	-	-	Covered	T165,T166
DetectSt	-	-	-	-	0	1	-	Covered	T7,T32,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T32,T23
StableSt	-	-	-	-	-	-	0	Covered	T7,T32,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	141	0	0
CntIncr_A	7216696	195896	0	0
CntNoWrap_A	7216696	6550502	0	0
DetectStDropOut_A	7216696	2	0	0
DetectedOut_A	7216696	176683	0	0
DetectedPulseOut_A	7216696	66	0	0
DisabledIdleSt_A	7216696	5994219	0	0
DisabledNoDetection_A	7216696	5996630	0	0
EnterDebounceSt_A	7216696	74	0	0
EnterDetectSt_A	7216696	68	0	0
EnterStableSt_A	7216696	66	0	0
PulseIsPulse_A	7216696	66	0	0
StayInStableSt	7216696	176587	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7216696	2636	0	0
gen_low_level_sva.LowLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	141	0	0
T7	1020	4	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	4	0	0
T25	7798	0	0	0
T28	0	4	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	2	0	0
T151	0	4	0	0
T169	0	2	0	0
T170	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	195896	0	0
T7	1020	190	0	0
T8	3902	0	0	0
T9	23434	5491	0	0
T10	36864	0	0	0
T23	0	98	0	0
T25	7798	0	0	0
T28	0	34	0	0
T32	0	16	0	0
T33	0	45	0	0
T34	0	94	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	17	0	0
T169	0	10	0	0
T170	0	42	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6550502	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	2	0	0
T69	7726	0	0	0
T165	76038	1	0	0
T166	0	1	0	0
T171	405	0	0	0
T172	6034	0	0	0
T173	567	0	0	0
T174	415	0	0	0
T175	713	0	0	0
T176	146880	0	0	0
T177	496	0	0	0
T178	691	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	176683	0	0
T7	1020	252	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	77	0	0
T25	7798	0	0	0
T28	0	49	0	0
T32	0	11	0	0
T33	0	89	0	0
T34	0	41	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	73	0	0
T151	0	57	0	0
T169	0	45	0	0
T170	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	66	0	0
T7	1020	2	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	2	0	0
T25	7798	0	0	0
T28	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T151	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	5994219	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	5996630	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	74	0	0
T7	1020	2	0	0
T8	3902	0	0	0
T9	23434	1	0	0
T10	36864	0	0	0
T23	0	2	0	0
T25	7798	0	0	0
T28	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	68	0	0
T7	1020	2	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	2	0	0
T25	7798	0	0	0
T28	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T151	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	66	0	0
T7	1020	2	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	2	0	0
T25	7798	0	0	0
T28	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T151	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	66	0	0
T7	1020	2	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	2	0	0
T25	7798	0	0	0
T28	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T151	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	176587	0	0
T7	1020	249	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	74	0	0
T25	7798	0	0	0
T28	0	47	0	0
T32	0	10	0	0
T33	0	87	0	0
T34	0	39	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	72	0	0
T151	0	55	0	0
T169	0	43	0	0
T170	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	2636	0	0
T1	64534	4	0	0
T2	1898	0	0	0
T3	3483	8	0	0
T4	12671	0	0	0
T6	502	2	0	0
T7	0	2	0	0
T8	0	15	0	0
T9	0	21	0	0
T13	402	0	0	0
T14	437	4	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	1	0	0
T24	0	7	0	0
T45	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	36	0	0
T7	1020	1	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	1	0	0
T25	7798	0	0	0
T28	0	2	0	0
T32	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	1	0	0
T115	0	1	0	0
T142	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0
T179	0	1	0	0