Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.09	100.00	95.01		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	89.26	93.48	85.71		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	90.61	95.65	85.71		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	90.61	95.65	85.71		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	90.61	95.65	85.71		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	90.61	95.65	85.71		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	96.66	97.83	90.48		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	96.66	97.83	90.48		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
89.26	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
96.66	97.83

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
90.61	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
90.61	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
90.61	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
90.61	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
96.66	97.83

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T16
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T16
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T15,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T15,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T16,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T16
1	0	Covered	T1,T15,T16
1	1	Covered	T1,T15,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T3
0	1	Covered	T1,T33,T68
1	0	Covered	T69,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T3
0	1	Covered	T1,T16,T3
1	0	Covered	T69,T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T16,T3
1	-	Covered	T1,T16,T3

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
89.26	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
96.66	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T3
1	0	Covered	T1,T6,T14
1	1	Covered	T1,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T23,T71,T72
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T1,T3,T7
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T7
1	-	Covered	T1,T3,T7

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T4,T25
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T16,T4,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T16,T4,T25

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T16,T4,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T4,T25
1	0	Covered	T16,T4,T25
1	1	Covered	T16,T4,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T4,T25
0	1	Covered	T25,T38,T64
1	0	Covered	T25,T11,T38

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T4,T25
0	1	Covered	T16,T4,T25
1	0	Covered	T73,T74,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T4,T25
1	-	Covered	T16,T4,T25

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T9,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T9,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T21,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T21
1	0	Covered	T1,T6,T14
1	1	Covered	T2,T9,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T21,T50
0	1	Covered	T76,T77,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T21,T50
0	1	Unreachable
1	0	Covered	T9,T21,T50

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
90.61	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
90.61	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
90.61	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
90.61	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
96.66	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T5,T1,T6
1	1	Covered	T7,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T9,T79,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T9,T32
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T9
1	-	Covered	T7,T9,T32

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T14
1	1	Covered	T1,T6,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T9,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T9,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T9,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T21
1	0	Covered	T1,T6,T14
1	1	Covered	T2,T9,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T21
0	1	Covered	T50,T66,T67
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T21
0	1	Unreachable
1	0	Covered	T2,T9,T21

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T14
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T14
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T9,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T9,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T50,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T21
1	0	Covered	T1,T6,T14
1	1	Covered	T2,T9,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T50,T33
0	1	Covered	T77,T81,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T50,T33
0	1	Unreachable
1	0	Covered	T2,T50,T33

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T7
DetectSt	168	Covered	T1,T3,T7
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T7
DebounceSt->IdleSt	163	Covered	T9,T35,T37
DetectSt->IdleSt	186	Covered	T23,T50,T66
DetectSt->StableSt	191	Covered	T1,T3,T7
IdleSt->DebounceSt	148	Covered	T1,T3,T7
StableSt->IdleSt	206	Covered	T1,T3,T7

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.26	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
96.66	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
90.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
90.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
90.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
90.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
96.66	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T7
0	1	Covered	T1,T3,T7
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T35,T37
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T23,T50,T66
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T16,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T7
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T16,T4
0	1	Covered	T2,T16,T4
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T4,T25
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T16,T4
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T4,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T83,T72
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T16,T4
DetectSt	-	-	-	-	1	-	-	Covered	T25,T11,T38
DetectSt	-	-	-	-	0	1	-	Covered	T16,T4,T9
DetectSt	-	-	-	-	0	0	-	Covered	T16,T4,T25
StableSt	-	-	-	-	-	-	1	Covered	T16,T4,T9
StableSt	-	-	-	-	-	-	0	Covered	T16,T4,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	187634096	17519	0	0
CntIncr_A	187634096	2487591	0	0
CntNoWrap_A	187634096	170299199	0	0
DetectStDropOut_A	187634096	1863	0	0
DetectedOut_A	187634096	1636284	0	0
DetectedPulseOut_A	187634096	5792	0	0
DisabledIdleSt_A	187634096	159350747	0	0
DisabledNoDetection_A	187634096	159410150	0	0
EnterDebounceSt_A	187634096	9059	0	0
EnterDetectSt_A	187634096	8484	0	0
EnterStableSt_A	187634096	5792	0	0
PulseIsPulse_A	187634096	5792	0	0
StayInStableSt	187634096	1629611	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	64950264	51452	0	0
gen_high_event_sva.HighLevelEvent_A	36083480	32765540	0	0
gen_high_level_sva.HighLevelEvent_A	122683832	111402836	0	0
gen_low_level_sva.LowLevelEvent_A	64950264	58977972	0	0
gen_not_sticky_sva.StableStDropOut_A	165984008	4693	0	0
gen_sticky_sva.StableStDropOut_A	21650088	1694725	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187634096	17519	0	0
T1	322670	43	0	0
T2	9490	0	0	0
T3	31347	4	0	0
T4	114039	12	0	0
T6	2510	0	0	0
T7	5100	0	0	0
T8	19510	2	0	0
T9	23434	10	0	0
T10	0	14	0	0
T11	0	29	0	0
T12	0	26	0	0
T13	2010	0	0	0
T14	2185	0	0	0
T15	21190	1	0	0
T16	204417	60	0	0
T17	3735	0	0	0
T24	2088	0	0	0
T25	38990	30	0	0
T35	701	1	0	0
T36	732	4	0	0
T37	0	3	0	0
T38	0	16	0	0
T39	0	34	0	0
T40	0	2	0	0
T41	0	3	0	0
T42	0	38	0	0
T44	0	4	0	0
T45	1768	0	0	0
T46	3165	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T59	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187634096	2487591	0	0
T1	322670	3009	0	0
T2	9490	0	0	0
T3	31347	112	0	0
T4	114039	404	0	0
T6	2510	0	0	0
T7	5100	0	0	0
T8	19510	89	0	0
T9	23434	251	0	0
T10	0	810	0	0
T11	0	1334	0	0
T12	0	2444	0	0
T13	2010	0	0	0
T14	2185	0	0	0
T15	21190	20	0	0
T16	204417	2198	0	0
T17	3735	0	0	0
T24	2088	0	0	0
T25	38990	1091	0	0
T35	701	48	0	0
T36	732	178	0	0
T37	0	20	0	0
T38	0	526	0	0
T39	0	835	0	0
T40	0	14	0	0
T41	0	41	0	0
T42	0	1178	0	0
T44	0	48427	0	0
T45	1768	0	0	0
T46	3165	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T59	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187634096	170299199	0	0
T1	1677884	1611222	0	0
T2	49348	38908	0	0
T3	90558	28024	0	0
T5	10634	208	0	0
T6	13052	2626	0	0
T13	10452	26	0	0
T14	11362	936	0	0
T15	110188	33461	0	0
T16	590538	578804	0	0
T17	10790	364	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187634096	1863	0	0
T28	2869	0	0	0
T30	2565	0	0	0
T33	117463	3	0	0
T38	6087	6	0	0
T51	894	0	0	0
T52	1510	0	0	0
T55	495	0	0	0
T64	0	33	0	0
T68	0	3	0	0
T70	0	1	0	0
T84	0	12	0	0
T85	0	15	0	0
T86	0	17	0	0
T87	0	10	0	0
T88	0	5	0	0
T89	0	5	0	0
T90	0	10	0	0
T91	8059	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	5	0	0
T95	0	5	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	13	0	0
T99	0	1	0	0
T100	23786	0	0	0
T101	509	0	0	0
T102	502	0	0	0
T103	423	0	0	0
T104	19093	0	0	0
T105	192365	0	0	0
T106	1970	0	0	0
T107	509	0	0	0
T108	15049	0	0	0
T109	20944	0	0	0
T110	745	0	0	0
T111	2327	0	0	0
T112	688	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187634096	1636284	0	0
T1	322670	481	0	0
T2	9490	0	0	0
T3	31347	11	0	0
T4	114039	313	0	0
T6	2510	0	0	0
T7	5100	0	0	0
T8	19510	7	0	0
T9	23434	25	0	0
T10	0	145	0	0
T11	0	1764	0	0
T12	0	1173	0	0
T13	2010	0	0	0
T14	2185	0	0	0
T15	21190	0	0	0
T16	204417	2482	0	0
T17	3735	0	0	0
T21	0	85	0	0
T24	2088	0	0	0
T25	38990	0	0	0
T35	701	0	0	0
T36	732	14	0	0
T37	0	2	0	0
T39	0	1805	0	0
T40	0	4	0	0
T41	0	27	0	0
T42	0	2580	0	0
T43	0	440	0	0
T44	0	10	0	0
T45	1768	0	0	0
T46	3165	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T59	0	3	0	0
T113	0	1562	0	0
T114	0	2	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187634096	5792	0	0
T1	322670	20	0	0
T2	9490	0	0	0
T3	31347	2	0	0
T4	114039	6	0	0
T6	2510	0	0	0
T7	5100	0	0	0
T8	19510	1	0	0
T9	23434	4	0	0
T10	0	6	0	0
T11	0	14	0	0
T12	0	13	0	0
T13	2010	0	0	0
T14	2185	0	0	0
T15	21190	0	0	0
T16	204417	30	0	0
T17	3735	0	0	0
T21	0	3	0	0
T24	2088	0	0	0
T25	38990	0	0	0
T35	701	0	0	0
T36	732	2	0	0
T37	0	1	0	0
T39	0	17	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	20	0	0
T43	0	18	0	0
T44	0	2	0	0
T45	1768	0	0	0
T46	3165	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T59	0	1	0	0
T113	0	11	0	0
T114	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187634096	159350747	0	0
T1	1677884	1557815	0	0
T2	49348	34584	0	0
T3	90558	27814	0	0
T5	10634	208	0	0
T6	13052	2626	0	0
T13	10452	26	0	0
T14	11362	936	0	0
T15	110188	33412	0	0
T16	590538	546447	0	0
T17	10790	364	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187634096	159410150	0	0
T1	1677884	1558394	0	0
T2	49348	34610	0	0
T3	90558	27943	0	0
T5	10634	234	0	0
T6	13052	2652	0	0
T13	10452	52	0	0
T14	11362	962	0	0
T15	110188	33644	0	0
T16	590538	546601	0	0
T17	10790	390	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187634096	9059	0	0
T1	322670	23	0	0
T2	9490	0	0	0
T3	31347	2	0	0
T4	114039	6	0	0
T6	2510	0	0	0
T7	5100	0	0	0
T8	19510	1	0	0
T9	23434	6	0	0
T10	0	8	0	0
T11	0	15	0	0
T12	0	13	0	0
T13	2010	0	0	0
T14	2185	0	0	0
T15	21190	1	0	0
T16	204417	30	0	0
T17	3735	0	0	0
T24	2088	0	0	0
T25	38990	15	0	0
T35	701	1	0	0
T36	732	2	0	0
T37	0	2	0	0
T38	0	8	0	0
T39	0	17	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	19	0	0
T44	0	2	0	0
T45	1768	0	0	0
T46	3165	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T59	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187634096	8484	0	0
T1	322670	20	0	0
T2	9490	0	0	0
T3	31347	2	0	0
T4	114039	6	0	0
T6	2510	0	0	0
T7	5100	0	0	0
T8	19510	1	0	0
T9	23434	4	0	0
T10	0	6	0	0
T11	0	14	0	0
T12	0	13	0	0
T13	2010	0	0	0
T14	2185	0	0	0
T15	21190	0	0	0
T16	204417	30	0	0
T17	3735	0	0	0
T21	0	3	0	0
T24	2088	0	0	0
T25	38990	15	0	0
T35	701	0	0	0
T36	732	2	0	0
T37	0	1	0	0
T38	0	8	0	0
T39	0	17	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	20	0	0
T44	0	2	0	0
T45	1768	0	0	0
T46	3165	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T59	0	1	0	0
T114	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187634096	5792	0	0
T1	322670	20	0	0
T2	9490	0	0	0
T3	31347	2	0	0
T4	114039	6	0	0
T6	2510	0	0	0
T7	5100	0	0	0
T8	19510	1	0	0
T9	23434	4	0	0
T10	0	6	0	0
T11	0	14	0	0
T12	0	13	0	0
T13	2010	0	0	0
T14	2185	0	0	0
T15	21190	0	0	0
T16	204417	30	0	0
T17	3735	0	0	0
T21	0	3	0	0
T24	2088	0	0	0
T25	38990	0	0	0
T35	701	0	0	0
T36	732	2	0	0
T37	0	1	0	0
T39	0	17	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	20	0	0
T43	0	18	0	0
T44	0	2	0	0
T45	1768	0	0	0
T46	3165	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T59	0	1	0	0
T113	0	11	0	0
T114	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187634096	5792	0	0
T1	322670	20	0	0
T2	9490	0	0	0
T3	31347	2	0	0
T4	114039	6	0	0
T6	2510	0	0	0
T7	5100	0	0	0
T8	19510	1	0	0
T9	23434	4	0	0
T10	0	6	0	0
T11	0	14	0	0
T12	0	13	0	0
T13	2010	0	0	0
T14	2185	0	0	0
T15	21190	0	0	0
T16	204417	30	0	0
T17	3735	0	0	0
T21	0	3	0	0
T24	2088	0	0	0
T25	38990	0	0	0
T35	701	0	0	0
T36	732	2	0	0
T37	0	1	0	0
T39	0	17	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	20	0	0
T43	0	18	0	0
T44	0	2	0	0
T45	1768	0	0	0
T46	3165	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T59	0	1	0	0
T113	0	11	0	0
T114	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	187634096	1629611	0	0
T1	322670	461	0	0
T2	9490	0	0	0
T3	31347	9	0	0
T4	114039	306	0	0
T6	2510	0	0	0
T7	5100	0	0	0
T8	19510	6	0	0
T9	23434	21	0	0
T10	0	139	0	0
T11	0	1746	0	0
T12	0	1160	0	0
T13	2010	0	0	0
T14	2185	0	0	0
T15	21190	0	0	0
T16	204417	2443	0	0
T17	3735	0	0	0
T21	0	82	0	0
T24	2088	0	0	0
T25	38990	0	0	0
T35	701	0	0	0
T36	732	12	0	0
T37	0	1	0	0
T39	0	1786	0	0
T40	0	3	0	0
T41	0	25	0	0
T42	0	2557	0	0
T43	0	422	0	0
T44	0	8	0	0
T45	1768	0	0	0
T46	3165	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T59	0	2	0	0
T113	0	1548	0	0
T114	0	1	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64950264	51452	0	0
T1	580806	278	0	0
T2	17082	21	0	0
T3	31347	86	0	0
T4	114039	190	0	0
T6	4518	44	0	0
T7	0	4	0	0
T8	0	29	0	0
T9	0	21	0	0
T13	3618	0	0	0
T14	3933	34	0	0
T15	38142	9	0	0
T16	204417	239	0	0
T17	3735	4	0	0
T24	0	48	0	0
T25	0	97	0	0
T45	0	44	0	0
T46	0	6	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36083480	32765540	0	0
T1	322670	310000	0	0
T2	9490	7490	0	0
T3	17415	5415	0	0
T5	2045	45	0	0
T6	2510	510	0	0
T13	2010	10	0	0
T14	2185	185	0	0
T15	21190	6480	0	0
T16	113565	111370	0	0
T17	2075	75	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122683832	111402836	0	0
T1	1097078	1054000	0	0
T2	32266	25466	0	0
T3	59211	18411	0	0
T5	6953	153	0	0
T6	8534	1734	0	0
T13	6834	34	0	0
T14	7429	629	0	0
T15	72046	22032	0	0
T16	386121	378658	0	0
T17	7055	255	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64950264	58977972	0	0
T1	580806	558000	0	0
T2	17082	13482	0	0
T3	31347	9747	0	0
T5	3681	81	0	0
T6	4518	918	0	0
T13	3618	18	0	0
T14	3933	333	0	0
T15	38142	11664	0	0
T16	204417	200466	0	0
T17	3735	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165984008	4693	0	0
T1	322670	20	0	0
T2	9490	0	0	0
T3	31347	2	0	0
T4	114039	5	0	0
T6	2510	0	0	0
T7	5100	0	0	0
T8	19510	1	0	0
T9	23434	4	0	0
T10	0	6	0	0
T11	0	10	0	0
T12	0	13	0	0
T13	2010	0	0	0
T14	2185	0	0	0
T15	21190	0	0	0
T16	204417	21	0	0
T17	3735	0	0	0
T21	0	3	0	0
T24	2088	0	0	0
T25	38990	0	0	0
T33	0	14	0	0
T35	701	0	0	0
T36	732	2	0	0
T37	0	1	0	0
T39	0	15	0	0
T40	0	1	0	0
T42	0	17	0	0
T43	0	18	0	0
T44	0	2	0	0
T45	1768	0	0	0
T46	3165	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T59	0	1	0	0
T100	0	1	0	0
T114	0	1	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21650088	1694725	0	0
T2	3796	1020	0	0
T3	6966	0	0	0
T4	25342	0	0	0
T7	2040	0	0	0
T8	7804	0	0	0
T9	23434	1552	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T16	45426	0	0	0
T17	830	0	0	0
T21	0	110	0	0
T24	1044	0	0	0
T25	15596	0	0	0
T33	0	52304	0	0
T35	701	0	0	0
T36	732	0	0	0
T45	884	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T50	0	1029	0	0
T51	0	638	0	0
T53	0	174106	0	0
T65	0	2120	0	0
T66	0	1096	0	0
T67	0	228	0	0
T72	0	66	0	0
T83	0	872	0	0
T115	0	44270	0	0
T116	0	29	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0