Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T32,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T7,T32,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T32,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T32
1	0	Covered	T5,T1,T6
1	1	Covered	T7,T32,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T32,T23
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T32,T23
0	1	Covered	T7,T32,T151
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T32,T23
1	-	Covered	T7,T32,T151

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T32,T23
DetectSt	168	Covered	T7,T32,T23
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T7,T32,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T32,T23
DebounceSt->IdleSt	163	Covered	T28,T34,T69
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T32,T23
IdleSt->DebounceSt	148	Covered	T7,T32,T23
StableSt->IdleSt	206	Covered	T7,T32,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T32,T23
0	1	Covered	T7,T32,T23
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T32,T23
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T32,T23
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T32,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T34
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T32,T23
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T32,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T32,T151
StableSt	-	-	-	-	-	-	0	Covered	T7,T32,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	54	0	0
CntIncr_A	7216696	33220	0	0
CntNoWrap_A	7216696	6550589	0	0
DetectStDropOut_A	7216696	0	0	0
DetectedOut_A	7216696	2139	0	0
DetectedPulseOut_A	7216696	25	0	0
DisabledIdleSt_A	7216696	6268489	0	0
DisabledNoDetection_A	7216696	6270908	0	0
EnterDebounceSt_A	7216696	29	0	0
EnterDetectSt_A	7216696	25	0	0
EnterStableSt_A	7216696	25	0	0
PulseIsPulse_A	7216696	25	0	0
StayInStableSt	7216696	2100	0	0
gen_high_level_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	54	0	0
T7	1020	2	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	2	0	0
T25	7798	0	0	0
T28	0	1	0	0
T31	0	2	0	0
T32	0	2	0	0
T34	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	2	0	0
T115	0	2	0	0
T149	0	2	0	0
T151	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	33220	0	0
T7	1020	95	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	42	0	0
T25	7798	0	0	0
T28	0	17	0	0
T31	0	94	0	0
T32	0	16	0	0
T34	0	94	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	79	0	0
T115	0	54	0	0
T149	0	51	0	0
T151	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6550589	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	2139	0	0
T7	1020	71	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	80	0	0
T25	7798	0	0	0
T31	0	136	0	0
T32	0	81	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	124	0	0
T115	0	41	0	0
T141	0	14	0	0
T149	0	42	0	0
T151	0	108	0	0
T162	0	336	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	25	0	0
T7	1020	1	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	1	0	0
T25	7798	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	1	0	0
T115	0	1	0	0
T141	0	1	0	0
T149	0	1	0	0
T151	0	1	0	0
T162	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6268489	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6270908	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	29	0	0
T7	1020	1	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	1	0	0
T25	7798	0	0	0
T28	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	1	0	0
T115	0	1	0	0
T149	0	1	0	0
T151	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	25	0	0
T7	1020	1	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	1	0	0
T25	7798	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	1	0	0
T115	0	1	0	0
T141	0	1	0	0
T149	0	1	0	0
T151	0	1	0	0
T162	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	25	0	0
T7	1020	1	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	1	0	0
T25	7798	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	1	0	0
T115	0	1	0	0
T141	0	1	0	0
T149	0	1	0	0
T151	0	1	0	0
T162	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	25	0	0
T7	1020	1	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	1	0	0
T25	7798	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	1	0	0
T115	0	1	0	0
T141	0	1	0	0
T149	0	1	0	0
T151	0	1	0	0
T162	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	2100	0	0
T7	1020	70	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	78	0	0
T25	7798	0	0	0
T31	0	134	0	0
T32	0	80	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	123	0	0
T115	0	39	0	0
T141	0	13	0	0
T149	0	40	0	0
T151	0	107	0	0
T162	0	334	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	11	0	0
T7	1020	1	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T25	7798	0	0	0
T32	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T131	0	2	0	0
T141	0	1	0	0
T151	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T9,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T7,T9,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T9,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T21
1	0	Covered	T1,T6,T14
1	1	Covered	T7,T9,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T23
0	1	Covered	T72,T182
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T23
0	1	Covered	T7,T9,T23
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T23
1	-	Covered	T7,T9,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T21
DetectSt	168	Covered	T7,T9,T23
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T7,T9,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T23
DebounceSt->IdleSt	163	Covered	T9,T21,T72
DetectSt->IdleSt	186	Covered	T72,T182
DetectSt->StableSt	191	Covered	T7,T9,T23
IdleSt->DebounceSt	148	Covered	T7,T9,T21
StableSt->IdleSt	206	Covered	T7,T9,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T9,T23
0	1	Covered	T7,T9,T21
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T23
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T21
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T72
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T21
DetectSt	-	-	-	-	1	-	-	Covered	T72,T182
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T9,T23
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	118	0	0
CntIncr_A	7216696	74220	0	0
CntNoWrap_A	7216696	6550525	0	0
DetectStDropOut_A	7216696	2	0	0
DetectedOut_A	7216696	48248	0	0
DetectedPulseOut_A	7216696	55	0	0
DisabledIdleSt_A	7216696	6338269	0	0
DisabledNoDetection_A	7216696	6340686	0	0
EnterDebounceSt_A	7216696	62	0	0
EnterDetectSt_A	7216696	57	0	0
EnterStableSt_A	7216696	55	0	0
PulseIsPulse_A	7216696	55	0	0
StayInStableSt	7216696	48170	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7216696	2936	0	0
gen_low_level_sva.LowLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	118	0	0
T7	1020	4	0	0
T8	3902	0	0	0
T9	23434	3	0	0
T10	36864	0	0	0
T23	0	2	0	0
T25	7798	0	0	0
T28	0	4	0	0
T30	0	2	0	0
T34	0	4	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	2	0	0
T151	0	4	0	0
T169	0	2	0	0
T183	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	74220	0	0
T7	1020	190	0	0
T8	3902	0	0	0
T9	23434	134	0	0
T10	36864	0	0	0
T21	0	73	0	0
T23	0	42	0	0
T25	7798	0	0	0
T28	0	34	0	0
T30	0	72	0	0
T34	0	188	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	54	0	0
T169	0	10	0	0
T183	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6550525	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	2	0	0
T72	19272	1	0	0
T87	23902	0	0	0
T134	949	0	0	0
T161	962	0	0	0
T182	0	1	0	0
T184	506	0	0	0
T185	8855	0	0	0
T186	533	0	0	0
T187	503	0	0	0
T188	402	0	0	0
T189	3003	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	48248	0	0
T7	1020	78	0	0
T8	3902	0	0	0
T9	23434	78	0	0
T10	36864	0	0	0
T23	0	83	0	0
T25	7798	0	0	0
T28	0	79	0	0
T30	0	40	0	0
T34	0	194	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	10	0	0
T151	0	238	0	0
T169	0	46	0	0
T183	0	160	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	55	0	0
T7	1020	2	0	0
T8	3902	0	0	0
T9	23434	1	0	0
T10	36864	0	0	0
T23	0	1	0	0
T25	7798	0	0	0
T28	0	2	0	0
T30	0	1	0	0
T34	0	2	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T151	0	2	0	0
T169	0	1	0	0
T183	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6338269	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6340686	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	62	0	0
T7	1020	2	0	0
T8	3902	0	0	0
T9	23434	2	0	0
T10	36864	0	0	0
T21	0	1	0	0
T23	0	1	0	0
T25	7798	0	0	0
T28	0	2	0	0
T30	0	1	0	0
T34	0	2	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T169	0	1	0	0
T183	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	57	0	0
T7	1020	2	0	0
T8	3902	0	0	0
T9	23434	1	0	0
T10	36864	0	0	0
T23	0	1	0	0
T25	7798	0	0	0
T28	0	2	0	0
T30	0	1	0	0
T34	0	2	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T151	0	2	0	0
T169	0	1	0	0
T183	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	55	0	0
T7	1020	2	0	0
T8	3902	0	0	0
T9	23434	1	0	0
T10	36864	0	0	0
T23	0	1	0	0
T25	7798	0	0	0
T28	0	2	0	0
T30	0	1	0	0
T34	0	2	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T151	0	2	0	0
T169	0	1	0	0
T183	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	55	0	0
T7	1020	2	0	0
T8	3902	0	0	0
T9	23434	1	0	0
T10	36864	0	0	0
T23	0	1	0	0
T25	7798	0	0	0
T28	0	2	0	0
T30	0	1	0	0
T34	0	2	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T151	0	2	0	0
T169	0	1	0	0
T183	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	48170	0	0
T7	1020	75	0	0
T8	3902	0	0	0
T9	23434	77	0	0
T10	36864	0	0	0
T23	0	82	0	0
T25	7798	0	0	0
T28	0	76	0	0
T30	0	39	0	0
T34	0	191	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	9	0	0
T151	0	235	0	0
T169	0	45	0	0
T183	0	159	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	2936	0	0
T1	64534	2	0	0
T2	1898	0	0	0
T3	3483	7	0	0
T4	12671	0	0	0
T6	502	6	0	0
T7	0	2	0	0
T8	0	14	0	0
T13	402	0	0	0
T14	437	3	0	0
T15	4238	6	0	0
T16	22713	0	0	0
T17	415	0	0	0
T24	0	6	0	0
T45	0	3	0	0
T46	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	32	0	0
T7	1020	1	0	0
T8	3902	0	0	0
T9	23434	1	0	0
T10	36864	0	0	0
T23	0	1	0	0
T25	7798	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T34	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T151	0	1	0	0
T169	0	1	0	0
T183	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T14
1	1	Covered	T1,T6,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T21,T23,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T9,T21,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T21,T23,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T21,T23
1	0	Covered	T1,T6,T14
1	1	Covered	T9,T21,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T23,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T23,T33
0	1	Covered	T23,T28,T29
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T23,T33
1	-	Covered	T23,T28,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T21,T23
DetectSt	168	Covered	T21,T23,T33
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T21,T23,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T23,T33
DebounceSt->IdleSt	163	Covered	T9,T115,T69
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T21,T23,T33
IdleSt->DebounceSt	148	Covered	T9,T21,T23
StableSt->IdleSt	206	Covered	T21,T23,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T23,T33
0	1	Covered	T9,T21,T23
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T23,T33
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T21,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T23,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T115
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T21,T23
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T21,T23,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T28,T29
StableSt	-	-	-	-	-	-	0	Covered	T21,T23,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	109	0	0
CntIncr_A	7216696	163402	0	0
CntNoWrap_A	7216696	6550534	0	0
DetectStDropOut_A	7216696	0	0	0
DetectedOut_A	7216696	80685	0	0
DetectedPulseOut_A	7216696	53	0	0
DisabledIdleSt_A	7216696	5996136	0	0
DisabledNoDetection_A	7216696	5998549	0	0
EnterDebounceSt_A	7216696	57	0	0
EnterDetectSt_A	7216696	53	0	0
EnterStableSt_A	7216696	53	0	0
PulseIsPulse_A	7216696	53	0	0
StayInStableSt	7216696	80611	0	0
gen_high_level_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	109	0	0
T21	12106	2	0	0
T23	8336	2	0	0
T28	0	4	0	0
T29	0	2	0	0
T33	117463	2	0	0
T34	0	2	0	0
T49	528	0	0	0
T50	1227	0	0	0
T51	894	0	0	0
T52	1510	0	0	0
T54	501	0	0	0
T115	0	3	0	0
T149	0	2	0	0
T190	0	2	0	0
T191	0	4	0	0
T192	422	0	0	0
T193	442	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	163402	0	0
T9	23434	5491	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T21	0	99	0	0
T23	0	42	0	0
T28	0	34	0	0
T29	0	48	0	0
T33	0	45	0	0
T34	0	94	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0
T149	0	51	0	0
T190	0	75	0	0
T191	0	84	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6550534	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	80685	0	0
T21	12106	112	0	0
T23	8336	210	0	0
T28	0	57	0	0
T29	0	69	0	0
T33	117463	175	0	0
T34	0	302	0	0
T49	528	0	0	0
T50	1227	0	0	0
T51	894	0	0	0
T52	1510	0	0	0
T54	501	0	0	0
T115	0	13	0	0
T149	0	214	0	0
T190	0	41	0	0
T191	0	81	0	0
T192	422	0	0	0
T193	442	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	53	0	0
T21	12106	1	0	0
T23	8336	1	0	0
T28	0	2	0	0
T29	0	1	0	0
T33	117463	1	0	0
T34	0	1	0	0
T49	528	0	0	0
T50	1227	0	0	0
T51	894	0	0	0
T52	1510	0	0	0
T54	501	0	0	0
T115	0	1	0	0
T149	0	1	0	0
T190	0	1	0	0
T191	0	2	0	0
T192	422	0	0	0
T193	442	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	5996136	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	5998549	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	57	0	0
T9	23434	1	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T21	0	1	0	0
T23	0	1	0	0
T28	0	2	0	0
T29	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0
T149	0	1	0	0
T190	0	1	0	0
T191	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	53	0	0
T21	12106	1	0	0
T23	8336	1	0	0
T28	0	2	0	0
T29	0	1	0	0
T33	117463	1	0	0
T34	0	1	0	0
T49	528	0	0	0
T50	1227	0	0	0
T51	894	0	0	0
T52	1510	0	0	0
T54	501	0	0	0
T115	0	1	0	0
T149	0	1	0	0
T190	0	1	0	0
T191	0	2	0	0
T192	422	0	0	0
T193	442	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	53	0	0
T21	12106	1	0	0
T23	8336	1	0	0
T28	0	2	0	0
T29	0	1	0	0
T33	117463	1	0	0
T34	0	1	0	0
T49	528	0	0	0
T50	1227	0	0	0
T51	894	0	0	0
T52	1510	0	0	0
T54	501	0	0	0
T115	0	1	0	0
T149	0	1	0	0
T190	0	1	0	0
T191	0	2	0	0
T192	422	0	0	0
T193	442	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	53	0	0
T21	12106	1	0	0
T23	8336	1	0	0
T28	0	2	0	0
T29	0	1	0	0
T33	117463	1	0	0
T34	0	1	0	0
T49	528	0	0	0
T50	1227	0	0	0
T51	894	0	0	0
T52	1510	0	0	0
T54	501	0	0	0
T115	0	1	0	0
T149	0	1	0	0
T190	0	1	0	0
T191	0	2	0	0
T192	422	0	0	0
T193	442	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	80611	0	0
T21	12106	110	0	0
T23	8336	209	0	0
T28	0	55	0	0
T29	0	68	0	0
T33	117463	173	0	0
T34	0	300	0	0
T49	528	0	0	0
T50	1227	0	0	0
T51	894	0	0	0
T52	1510	0	0	0
T54	501	0	0	0
T115	0	12	0	0
T149	0	212	0	0
T190	0	40	0	0
T191	0	78	0	0
T192	422	0	0	0
T193	442	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	32	0	0
T23	8336	1	0	0
T28	0	2	0	0
T29	0	1	0	0
T33	117463	0	0	0
T49	528	0	0	0
T50	1227	0	0	0
T51	894	0	0	0
T52	1510	0	0	0
T54	501	0	0	0
T72	0	1	0	0
T100	23786	0	0	0
T115	0	1	0	0
T142	0	1	0	0
T151	0	2	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	422	0	0	0
T193	442	0	0	0
T194	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T14
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T14
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T32,T23,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T32,T23,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T32,T23,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T32,T23
1	0	Covered	T1,T6,T14
1	1	Covered	T32,T23,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T32,T23,T29
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T32,T23,T29
0	1	Covered	T32,T141,T167
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T32,T23,T29
1	-	Covered	T32,T141,T167

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T23,T29
DetectSt	168	Covered	T32,T23,T29
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T32,T23,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T32,T23,T29
DebounceSt->IdleSt	163	Covered	T69,T70
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T32,T23,T29
IdleSt->DebounceSt	148	Covered	T32,T23,T29
StableSt->IdleSt	206	Covered	T32,T23,T72

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T32,T23,T29
0	1	Covered	T32,T23,T29
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T32,T23,T29
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T23,T29
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T32,T23,T29
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T23,T29
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T32,T23,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T141,T167
StableSt	-	-	-	-	-	-	0	Covered	T32,T23,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	66	0	0
CntIncr_A	7216696	50528	0	0
CntNoWrap_A	7216696	6550577	0	0
DetectStDropOut_A	7216696	0	0	0
DetectedOut_A	7216696	112836	0	0
DetectedPulseOut_A	7216696	32	0	0
DisabledIdleSt_A	7216696	6186981	0	0
DisabledNoDetection_A	7216696	6189399	0	0
EnterDebounceSt_A	7216696	34	0	0
EnterDetectSt_A	7216696	32	0	0
EnterStableSt_A	7216696	32	0	0
PulseIsPulse_A	7216696	32	0	0
StayInStableSt	7216696	112782	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7216696	6571	0	0
gen_low_level_sva.LowLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	66	0	0
T21	12106	0	0	0
T23	8336	2	0	0
T29	0	2	0	0
T31	0	2	0	0
T32	646	2	0	0
T40	640	0	0	0
T41	452	0	0	0
T42	18410	0	0	0
T43	9281	0	0	0
T62	427	0	0	0
T63	848	0	0	0
T71	0	2	0	0
T72	0	2	0	0
T141	0	2	0	0
T142	0	2	0	0
T148	0	2	0	0
T190	0	2	0	0
T192	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	50528	0	0
T21	12106	0	0	0
T23	8336	42	0	0
T29	0	48	0	0
T31	0	94	0	0
T32	646	16	0	0
T40	640	0	0	0
T41	452	0	0	0
T42	18410	0	0	0
T43	9281	0	0	0
T62	427	0	0	0
T63	848	0	0	0
T71	0	95	0	0
T72	0	18	0	0
T141	0	15	0	0
T142	0	55	0	0
T148	0	63	0	0
T190	0	75	0	0
T192	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6550577	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	112836	0	0
T21	12106	0	0	0
T23	8336	37	0	0
T29	0	105	0	0
T31	0	42	0	0
T32	646	81	0	0
T40	640	0	0	0
T41	452	0	0	0
T42	18410	0	0	0
T43	9281	0	0	0
T62	427	0	0	0
T63	848	0	0	0
T71	0	142	0	0
T72	0	72	0	0
T141	0	12	0	0
T142	0	42	0	0
T148	0	42	0	0
T190	0	41	0	0
T192	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	32	0	0
T21	12106	0	0	0
T23	8336	1	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	646	1	0	0
T40	640	0	0	0
T41	452	0	0	0
T42	18410	0	0	0
T43	9281	0	0	0
T62	427	0	0	0
T63	848	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T148	0	1	0	0
T190	0	1	0	0
T192	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6186981	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6189399	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	34	0	0
T21	12106	0	0	0
T23	8336	1	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	646	1	0	0
T40	640	0	0	0
T41	452	0	0	0
T42	18410	0	0	0
T43	9281	0	0	0
T62	427	0	0	0
T63	848	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T148	0	1	0	0
T190	0	1	0	0
T192	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	32	0	0
T21	12106	0	0	0
T23	8336	1	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	646	1	0	0
T40	640	0	0	0
T41	452	0	0	0
T42	18410	0	0	0
T43	9281	0	0	0
T62	427	0	0	0
T63	848	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T148	0	1	0	0
T190	0	1	0	0
T192	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	32	0	0
T21	12106	0	0	0
T23	8336	1	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	646	1	0	0
T40	640	0	0	0
T41	452	0	0	0
T42	18410	0	0	0
T43	9281	0	0	0
T62	427	0	0	0
T63	848	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T148	0	1	0	0
T190	0	1	0	0
T192	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	32	0	0
T21	12106	0	0	0
T23	8336	1	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	646	1	0	0
T40	640	0	0	0
T41	452	0	0	0
T42	18410	0	0	0
T43	9281	0	0	0
T62	427	0	0	0
T63	848	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T148	0	1	0	0
T190	0	1	0	0
T192	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	112782	0	0
T21	12106	0	0	0
T23	8336	35	0	0
T29	0	103	0	0
T31	0	40	0	0
T32	646	80	0	0
T40	640	0	0	0
T41	452	0	0	0
T42	18410	0	0	0
T43	9281	0	0	0
T62	427	0	0	0
T63	848	0	0	0
T71	0	140	0	0
T72	0	70	0	0
T141	0	11	0	0
T142	0	40	0	0
T148	0	40	0	0
T190	0	39	0	0
T192	422	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6571	0	0
T1	64534	33	0	0
T2	1898	6	0	0
T3	3483	8	0	0
T4	12671	22	0	0
T6	502	4	0	0
T13	402	0	0	0
T14	437	4	0	0
T15	4238	0	0	0
T16	22713	32	0	0
T17	415	1	0	0
T24	0	5	0	0
T45	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	10	0	0
T21	12106	0	0	0
T23	8336	0	0	0
T32	646	1	0	0
T40	640	0	0	0
T41	452	0	0	0
T42	18410	0	0	0
T43	9281	0	0	0
T62	427	0	0	0
T63	848	0	0	0
T81	0	1	0	0
T131	0	1	0	0
T141	0	1	0	0
T167	0	1	0	0
T180	0	1	0	0
T192	422	0	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T14
1	1	Covered	T1,T6,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T21,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T9,T21,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T28,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T21,T33
1	0	Covered	T1,T6,T14
1	1	Covered	T9,T21,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T28,T34
0	1	Covered	T198
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T28,T34
0	1	Covered	T9,T28,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T28,T34
1	-	Covered	T9,T28,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T21,T33
DetectSt	168	Covered	T9,T28,T34
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T9,T28,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T28,T34
DebounceSt->IdleSt	163	Covered	T21,T33,T69
DetectSt->IdleSt	186	Covered	T198
DetectSt->StableSt	191	Covered	T9,T28,T34
IdleSt->DebounceSt	148	Covered	T9,T21,T33
StableSt->IdleSt	206	Covered	T9,T28,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T21,T33
0	1	Covered	T9,T21,T33
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T28,T34
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T21,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T28,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T33
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T21,T33
DetectSt	-	-	-	-	1	-	-	Covered	T198
DetectSt	-	-	-	-	0	1	-	Covered	T9,T28,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T28,T34
StableSt	-	-	-	-	-	-	0	Covered	T9,T28,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	120	0	0
CntIncr_A	7216696	66396	0	0
CntNoWrap_A	7216696	6550523	0	0
DetectStDropOut_A	7216696	1	0	0
DetectedOut_A	7216696	86998	0	0
DetectedPulseOut_A	7216696	57	0	0
DisabledIdleSt_A	7216696	6267864	0	0
DisabledNoDetection_A	7216696	6270283	0	0
EnterDebounceSt_A	7216696	62	0	0
EnterDetectSt_A	7216696	58	0	0
EnterStableSt_A	7216696	57	0	0
PulseIsPulse_A	7216696	57	0	0
StayInStableSt	7216696	86918	0	0
gen_high_level_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	120	0	0
T9	23434	4	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T21	0	1	0	0
T28	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	2	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0
T148	0	4	0	0
T149	0	2	0	0
T151	0	2	0	0
T152	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	66396	0	0
T9	23434	134	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T21	0	87	0	0
T28	0	17	0	0
T33	0	45	0	0
T34	0	94	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	17	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0
T148	0	126	0	0
T149	0	51	0	0
T151	0	44	0	0
T152	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6550523	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	1	0	0
T198	3239	1	0	0
T199	636	0	0	0
T200	407	0	0	0
T201	506	0	0	0
T202	636	0	0	0
T203	6741	0	0	0
T204	502	0	0	0
T205	8420	0	0	0
T206	2173	0	0	0
T207	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	86998	0	0
T9	23434	212	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T28	0	58	0	0
T34	0	153	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	164	0	0
T115	0	44	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0
T148	0	145	0	0
T149	0	214	0	0
T151	0	193	0	0
T152	0	40	0	0
T208	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	57	0	0
T9	23434	2	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T28	0	1	0	0
T34	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	3	0	0
T115	0	1	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0
T148	0	2	0	0
T149	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T208	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6267864	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6270283	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	62	0	0
T9	23434	2	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T21	0	1	0	0
T28	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0
T148	0	2	0	0
T149	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	58	0	0
T9	23434	2	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T28	0	1	0	0
T34	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	3	0	0
T115	0	1	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0
T148	0	2	0	0
T149	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T208	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	57	0	0
T9	23434	2	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T28	0	1	0	0
T34	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	3	0	0
T115	0	1	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0
T148	0	2	0	0
T149	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T208	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	57	0	0
T9	23434	2	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T28	0	1	0	0
T34	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	3	0	0
T115	0	1	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0
T148	0	2	0	0
T149	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T208	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	86918	0	0
T9	23434	209	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T28	0	57	0	0
T34	0	152	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	159	0	0
T115	0	43	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0
T148	0	142	0	0
T149	0	212	0	0
T151	0	192	0	0
T152	0	38	0	0
T208	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	34	0	0
T9	23434	1	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T28	0	1	0	0
T34	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T72	0	1	0	0
T115	0	1	0	0
T117	426	0	0	0
T118	793	0	0	0
T119	586	0	0	0
T141	0	2	0	0
T148	0	1	0	0
T151	0	1	0	0
T189	0	1	0	0
T194	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T14
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T14
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T32,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T7,T32,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T32,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T6,T14
1	1	Covered	T7,T32,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T32,T23
0	1	Covered	T72
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T32,T23
0	1	Covered	T7,T148,T183
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T32,T23
1	-	Covered	T7,T148,T183

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T32,T23
DetectSt	168	Covered	T7,T32,T23
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T7,T32,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T32,T23
DebounceSt->IdleSt	163	Covered	T167,T69,T70
DetectSt->IdleSt	186	Covered	T72
DetectSt->StableSt	191	Covered	T7,T32,T23
IdleSt->DebounceSt	148	Covered	T7,T32,T23
StableSt->IdleSt	206	Covered	T7,T23,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T32,T23
0	1	Covered	T7,T32,T23
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T32,T23
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T32,T23
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T32,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T167
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T32,T23
DetectSt	-	-	-	-	1	-	-	Covered	T72
DetectSt	-	-	-	-	0	1	-	Covered	T7,T32,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T148,T183
StableSt	-	-	-	-	-	-	0	Covered	T7,T32,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	79	0	0
CntIncr_A	7216696	2350	0	0
CntNoWrap_A	7216696	6550564	0	0
DetectStDropOut_A	7216696	2	0	0
DetectedOut_A	7216696	2628	0	0
DetectedPulseOut_A	7216696	36	0	0
DisabledIdleSt_A	7216696	6526663	0	0
DisabledNoDetection_A	7216696	6529072	0	0
EnterDebounceSt_A	7216696	41	0	0
EnterDetectSt_A	7216696	38	0	0
EnterStableSt_A	7216696	36	0	0
PulseIsPulse_A	7216696	36	0	0
StayInStableSt	7216696	2570	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7216696	6224	0	0
gen_low_level_sva.LowLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	79	0	0
T7	1020	2	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	2	0	0
T25	7798	0	0	0
T28	0	2	0	0
T30	0	2	0	0
T32	0	2	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	2	0	0
T148	0	2	0	0
T150	0	2	0	0
T183	0	2	0	0
T190	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	2350	0	0
T7	1020	95	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	42	0	0
T25	7798	0	0	0
T28	0	17	0	0
T30	0	72	0	0
T32	0	16	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	17	0	0
T148	0	63	0	0
T150	0	55	0	0
T183	0	66	0	0
T190	0	75	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6550564	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	2	0	0
T72	19272	2	0	0
T87	23902	0	0	0
T134	949	0	0	0
T161	962	0	0	0
T184	506	0	0	0
T185	8855	0	0	0
T186	533	0	0	0
T187	503	0	0	0
T188	402	0	0	0
T189	3003	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	2628	0	0
T7	1020	71	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	81	0	0
T25	7798	0	0	0
T28	0	104	0	0
T30	0	113	0	0
T32	0	198	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	53	0	0
T148	0	60	0	0
T150	0	41	0	0
T183	0	57	0	0
T190	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	36	0	0
T7	1020	1	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	1	0	0
T25	7798	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T183	0	1	0	0
T190	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6526663	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6529072	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	41	0	0
T7	1020	1	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	1	0	0
T25	7798	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T183	0	1	0	0
T190	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	38	0	0
T7	1020	1	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	1	0	0
T25	7798	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T183	0	1	0	0
T190	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	36	0	0
T7	1020	1	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	1	0	0
T25	7798	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T183	0	1	0	0
T190	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	36	0	0
T7	1020	1	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	1	0	0
T25	7798	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T183	0	1	0	0
T190	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	2570	0	0
T7	1020	70	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T23	0	79	0	0
T25	7798	0	0	0
T28	0	102	0	0
T30	0	111	0	0
T32	0	196	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T115	0	51	0	0
T148	0	59	0	0
T150	0	39	0	0
T183	0	56	0	0
T190	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6224	0	0
T1	64534	34	0	0
T2	1898	0	0	0
T3	3483	6	0	0
T4	12671	32	0	0
T6	502	5	0	0
T13	402	0	0	0
T14	437	4	0	0
T15	4238	1	0	0
T16	22713	30	0	0
T17	415	1	0	0
T24	0	4	0	0
T45	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	14	0	0
T7	1020	1	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T25	7798	0	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T91	0	1	0	0
T148	0	1	0	0
T161	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T194	0	1	0	0
T209	0	1	0	0
T210	0	2	0	0
T211	0	1	0	0