Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T14
1	1	Covered	T1,T6,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T21,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T9,T21,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T21,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T21,T33
1	0	Covered	T1,T6,T14
1	1	Covered	T9,T21,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T21,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T21,T33
0	1	Covered	T9,T33,T31
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T21,T33
1	-	Covered	T9,T33,T31

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T21,T33
DetectSt	168	Covered	T9,T21,T33
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T9,T21,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T21,T33
DebounceSt->IdleSt	163	Covered	T69,T160,T212
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T21,T33
IdleSt->DebounceSt	148	Covered	T9,T21,T33
StableSt->IdleSt	206	Covered	T9,T21,T33

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T21,T33
0	1	Covered	T9,T21,T33
0	0	Excluded	T5,T1,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T9,T21,T33
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T21,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T21,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T160,T212
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T21,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T21,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T33,T31
StableSt	-	-	-	-	-	-	0	Covered	T9,T21,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	134	0	0
CntIncr_A	7216696	127300	0	0
CntNoWrap_A	7216696	6550509	0	0
DetectStDropOut_A	7216696	0	0	0
DetectedOut_A	7216696	22633	0	0
DetectedPulseOut_A	7216696	65	0	0
DisabledIdleSt_A	7216696	6267686	0	0
DisabledNoDetection_A	7216696	6270104	0	0
EnterDebounceSt_A	7216696	69	0	0
EnterDetectSt_A	7216696	65	0	0
EnterStableSt_A	7216696	65	0	0
PulseIsPulse_A	7216696	65	0	0
StayInStableSt	7216696	22537	0	0
gen_high_level_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	34	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7216696	134
T9	23434	4
T10	36864	0
T11	16698	0
T21	0	2
T30	0	2
T31	0	4
T33	0	2
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	2
T117	426	0
T118	793	0
T119	586	0
T148	0	2
T149	0	2
T150	0	4
T151	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7216696	127300
T9	23434	134
T10	36864	0
T11	16698	0
T21	0	87
T30	0	72
T31	0	188
T33	0	45
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	17
T117	426	0
T118	793	0
T119	586	0
T148	0	63
T149	0	51
T150	0	110
T151	0	44

CntNoWrap_A

Name	Attempts	Real Successes
Total	7216696	6550509
T1	64534	61974
T2	1898	1497
T3	3483	1078
T5	409	8
T6	502	101
T13	402	1
T14	437	36
T15	4238	1287
T16	22713	22267
T17	415	14

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7216696	22633
T9	23434	285
T10	36864	0
T11	16698	0
T21	0	75
T30	0	227
T31	0	105
T33	0	135
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	75
T117	426	0
T118	793	0
T119	586	0
T148	0	164
T149	0	41
T150	0	56
T151	0	24

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7216696	65
T9	23434	2
T10	36864	0
T11	16698	0
T21	0	1
T30	0	1
T31	0	2
T33	0	1
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	1
T117	426	0
T118	793	0
T119	586	0
T148	0	1
T149	0	1
T150	0	2
T151	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7216696	6267686
T1	64534	61974
T2	1898	1497
T3	3483	1078
T5	409	8
T6	502	101
T13	402	1
T14	437	36
T15	4238	1287
T16	22713	22267
T17	415	14

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7216696	6270104
T1	64534	62000
T2	1898	1498
T3	3483	1083
T5	409	9
T6	502	102
T13	402	2
T14	437	37
T15	4238	1296
T16	22713	22274
T17	415	15

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7216696	69
T9	23434	2
T10	36864	0
T11	16698	0
T21	0	1
T30	0	1
T31	0	2
T33	0	1
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	1
T117	426	0
T118	793	0
T119	586	0
T148	0	1
T149	0	1
T150	0	2
T151	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7216696	65
T9	23434	2
T10	36864	0
T11	16698	0
T21	0	1
T30	0	1
T31	0	2
T33	0	1
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	1
T117	426	0
T118	793	0
T119	586	0
T148	0	1
T149	0	1
T150	0	2
T151	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7216696	65
T9	23434	2
T10	36864	0
T11	16698	0
T21	0	1
T30	0	1
T31	0	2
T33	0	1
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	1
T117	426	0
T118	793	0
T119	586	0
T148	0	1
T149	0	1
T150	0	2
T151	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7216696	65
T9	23434	2
T10	36864	0
T11	16698	0
T21	0	1
T30	0	1
T31	0	2
T33	0	1
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	1
T117	426	0
T118	793	0
T119	586	0
T148	0	1
T149	0	1
T150	0	2
T151	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7216696	22537
T9	23434	282
T10	36864	0
T11	16698	0
T21	0	73
T30	0	225
T31	0	102
T33	0	134
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	74
T117	426	0
T118	793	0
T119	586	0
T148	0	162
T149	0	39
T150	0	54
T151	0	23

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7216696	6553108
T1	64534	62000
T2	1898	1498
T3	3483	1083
T5	409	9
T6	502	102
T13	402	2
T14	437	37
T15	4238	1296
T16	22713	22274
T17	415	15

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7216696	34
T9	23434	1
T10	36864	0
T11	16698	0
T31	0	1
T33	0	1
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T72	0	2
T115	0	1
T117	426	0
T118	793	0
T119	586	0
T150	0	2
T151	0	1
T162	0	1
T179	0	1
T210	0	2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T14
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T14
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T8,T9,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T8,T9,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T8,T9,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T6,T14
1	1	Covered	T8,T9,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T32
0	1	Covered	T189
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T32
0	1	Covered	T8,T9,T32
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T32
1	-	Covered	T8,T9,T32

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T32
DetectSt	168	Covered	T8,T9,T32
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T8,T9,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T32
DebounceSt->IdleSt	163	Covered	T69,T70
DetectSt->IdleSt	186	Covered	T189
DetectSt->StableSt	191	Covered	T8,T9,T32
IdleSt->DebounceSt	148	Covered	T8,T9,T32
StableSt->IdleSt	206	Covered	T8,T9,T32

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T32
0	1	Covered	T8,T9,T32
0	0	Excluded	T5,T1,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T32
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T32
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T32
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T32
DetectSt	-	-	-	-	1	-	-	Covered	T189
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T32
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	80	0	0
CntIncr_A	7216696	33705	0	0
CntNoWrap_A	7216696	6550563	0	0
DetectStDropOut_A	7216696	1	0	0
DetectedOut_A	7216696	147920	0	0
DetectedPulseOut_A	7216696	38	0	0
DisabledIdleSt_A	7216696	6185111	0	0
DisabledNoDetection_A	7216696	6187523	0	0
EnterDebounceSt_A	7216696	41	0	0
EnterDetectSt_A	7216696	39	0	0
EnterStableSt_A	7216696	38	0	0
PulseIsPulse_A	7216696	38	0	0
StayInStableSt	7216696	147862	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7216696	6299	0	0
gen_low_level_sva.LowLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	18	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7216696	80
T8	3902	2
T9	23434	2
T10	36864	0
T11	16698	0
T23	0	6
T28	0	2
T29	0	2
T31	0	2
T32	0	2
T33	0	2
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	2
T117	426	0
T191	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7216696	33705
T8	3902	17
T9	23434	67
T10	36864	0
T11	16698	0
T23	0	133
T28	0	17
T29	0	48
T31	0	94
T32	0	16
T33	0	45
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	95
T117	426	0
T191	0	42

CntNoWrap_A

Name	Attempts	Real Successes
Total	7216696	6550563
T1	64534	61974
T2	1898	1497
T3	3483	1078
T5	409	8
T6	502	101
T13	402	1
T14	437	36
T15	4238	1287
T16	22713	22267
T17	415	14

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7216696	1
T116	281552	0
T189	3003	1
T213	403	0
T214	502	0
T215	493	0
T216	1773	0
T217	609	0
T218	438	0
T219	436	0
T220	504	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7216696	147920
T8	3902	40
T9	23434	73
T10	36864	0
T11	16698	0
T23	0	232
T28	0	121
T29	0	41
T31	0	136
T32	0	12
T33	0	56
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	45
T117	426	0
T191	0	43

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7216696	38
T8	3902	1
T9	23434	1
T10	36864	0
T11	16698	0
T23	0	3
T28	0	1
T29	0	1
T31	0	1
T32	0	1
T33	0	1
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	1
T117	426	0
T191	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7216696	6185111
T1	64534	61974
T2	1898	1497
T3	3483	1078
T5	409	8
T6	502	101
T13	402	1
T14	437	36
T15	4238	1287
T16	22713	22267
T17	415	14

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7216696	6187523
T1	64534	62000
T2	1898	1498
T3	3483	1083
T5	409	9
T6	502	102
T13	402	2
T14	437	37
T15	4238	1296
T16	22713	22274
T17	415	15

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7216696	41
T8	3902	1
T9	23434	1
T10	36864	0
T11	16698	0
T23	0	3
T28	0	1
T29	0	1
T31	0	1
T32	0	1
T33	0	1
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	1
T117	426	0
T191	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7216696	39
T8	3902	1
T9	23434	1
T10	36864	0
T11	16698	0
T23	0	3
T28	0	1
T29	0	1
T31	0	1
T32	0	1
T33	0	1
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	1
T117	426	0
T191	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7216696	38
T8	3902	1
T9	23434	1
T10	36864	0
T11	16698	0
T23	0	3
T28	0	1
T29	0	1
T31	0	1
T32	0	1
T33	0	1
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	1
T117	426	0
T191	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7216696	38
T8	3902	1
T9	23434	1
T10	36864	0
T11	16698	0
T23	0	3
T28	0	1
T29	0	1
T31	0	1
T32	0	1
T33	0	1
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	1
T117	426	0
T191	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7216696	147862
T8	3902	39
T9	23434	72
T10	36864	0
T11	16698	0
T23	0	228
T28	0	119
T29	0	39
T31	0	135
T32	0	11
T33	0	54
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	43
T117	426	0
T191	0	42

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7216696	6299
T1	64534	40
T2	1898	0
T3	3483	8
T4	12671	23
T6	502	4
T13	402	0
T14	437	5
T15	4238	1
T16	22713	37
T17	415	1
T24	0	7
T45	0	5

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7216696	6553108
T1	64534	62000
T2	1898	1498
T3	3483	1083
T5	409	9
T6	502	102
T13	402	2
T14	437	37
T15	4238	1296
T16	22713	22274
T17	415	15

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7216696	18
T8	3902	1
T9	23434	1
T10	36864	0
T11	16698	0
T23	0	2
T31	0	1
T32	0	1
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T117	426	0
T150	0	1
T179	0	1
T183	0	1
T191	0	1
T221	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T14
1	1	Covered	T1,T6,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T32,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T9,T32,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T32,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T32,T21
1	0	Covered	T1,T6,T14
1	1	Covered	T9,T32,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T32,T21
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T32,T21
0	1	Covered	T9,T32,T23
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T32,T21
1	-	Covered	T9,T32,T23

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T32,T21
DetectSt	168	Covered	T9,T32,T21
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T9,T32,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T32,T21
DebounceSt->IdleSt	163	Covered	T191,T162,T222
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T32,T21
IdleSt->DebounceSt	148	Covered	T9,T32,T21
StableSt->IdleSt	206	Covered	T9,T32,T21

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T32,T21
0	1	Covered	T9,T32,T21
0	0	Excluded	T5,T1,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T9,T32,T21
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T32,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T32,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T191,T162,T222
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T32,T21
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T32,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T32,T23
StableSt	-	-	-	-	-	-	0	Covered	T9,T32,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	119	0	0
CntIncr_A	7216696	38823	0	0
CntNoWrap_A	7216696	6550524	0	0
DetectStDropOut_A	7216696	0	0	0
DetectedOut_A	7216696	4692	0	0
DetectedPulseOut_A	7216696	55	0	0
DisabledIdleSt_A	7216696	6343698	0	0
DisabledNoDetection_A	7216696	6346118	0	0
EnterDebounceSt_A	7216696	64	0	0
EnterDetectSt_A	7216696	55	0	0
EnterStableSt_A	7216696	55	0	0
PulseIsPulse_A	7216696	55	0	0
StayInStableSt	7216696	4609	0	0
gen_high_level_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	27	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7216696	119
T9	23434	4
T10	36864	0
T11	16698	0
T21	0	2
T23	0	4
T28	0	2
T32	0	4
T34	0	4
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	4
T117	426	0
T118	793	0
T119	586	0
T149	0	2
T150	0	4
T191	0	1

CntIncr_A

Name	Attempts	Real Successes
Total	7216696	38823
T9	23434	134
T10	36864	0
T11	16698	0
T21	0	87
T23	0	84
T28	0	17
T32	0	32
T34	0	188
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	71
T117	426	0
T118	793	0
T119	586	0
T149	0	51
T150	0	110
T191	0	42

CntNoWrap_A

Name	Attempts	Real Successes
Total	7216696	6550524
T1	64534	61974
T2	1898	1497
T3	3483	1078
T5	409	8
T6	502	101
T13	402	1
T14	437	36
T15	4238	1287
T16	22713	22267
T17	415	14

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7216696	4692
T9	23434	160
T10	36864	0
T11	16698	0
T21	0	75
T23	0	119
T28	0	45
T32	0	189
T34	0	73
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	148
T117	426	0
T118	793	0
T119	586	0
T149	0	120
T150	0	147
T152	0	112

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7216696	55
T9	23434	2
T10	36864	0
T11	16698	0
T21	0	1
T23	0	2
T28	0	1
T32	0	2
T34	0	2
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	2
T117	426	0
T118	793	0
T119	586	0
T149	0	1
T150	0	2
T152	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7216696	6343698
T1	64534	61974
T2	1898	1497
T3	3483	1078
T5	409	8
T6	502	101
T13	402	1
T14	437	36
T15	4238	1287
T16	22713	22267
T17	415	14

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7216696	6346118
T1	64534	62000
T2	1898	1498
T3	3483	1083
T5	409	9
T6	502	102
T13	402	2
T14	437	37
T15	4238	1296
T16	22713	22274
T17	415	15

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7216696	64
T9	23434	2
T10	36864	0
T11	16698	0
T21	0	1
T23	0	2
T28	0	1
T32	0	2
T34	0	2
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	2
T117	426	0
T118	793	0
T119	586	0
T149	0	1
T150	0	2
T191	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7216696	55
T9	23434	2
T10	36864	0
T11	16698	0
T21	0	1
T23	0	2
T28	0	1
T32	0	2
T34	0	2
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	2
T117	426	0
T118	793	0
T119	586	0
T149	0	1
T150	0	2
T152	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7216696	55
T9	23434	2
T10	36864	0
T11	16698	0
T21	0	1
T23	0	2
T28	0	1
T32	0	2
T34	0	2
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	2
T117	426	0
T118	793	0
T119	586	0
T149	0	1
T150	0	2
T152	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7216696	55
T9	23434	2
T10	36864	0
T11	16698	0
T21	0	1
T23	0	2
T28	0	1
T32	0	2
T34	0	2
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	2
T117	426	0
T118	793	0
T119	586	0
T149	0	1
T150	0	2
T152	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7216696	4609
T9	23434	157
T10	36864	0
T11	16698	0
T21	0	73
T23	0	116
T28	0	43
T32	0	186
T34	0	70
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	145
T117	426	0
T118	793	0
T119	586	0
T149	0	119
T150	0	144
T152	0	110

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7216696	6553108
T1	64534	62000
T2	1898	1498
T3	3483	1083
T5	409	9
T6	502	102
T13	402	2
T14	437	37
T15	4238	1296
T16	22713	22274
T17	415	15

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7216696	27
T9	23434	1
T10	36864	0
T11	16698	0
T23	0	1
T32	0	1
T34	0	1
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T115	0	1
T117	426	0
T118	793	0
T119	586	0
T149	0	1
T150	0	1
T161	0	1
T189	0	1
T194	0	2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T14
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T14
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T23,T30,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T23,T30,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T23,T30,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T21,T23
1	0	Covered	T1,T6,T14
1	1	Covered	T23,T30,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T30,T31
0	1	Covered	T71
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T30,T31
0	1	Covered	T23,T30,T31
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T23,T30,T31
1	-	Covered	T23,T30,T31

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T23,T30,T31
DetectSt	168	Covered	T23,T30,T31
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T23,T30,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T23,T30,T31
DebounceSt->IdleSt	163	Covered	T161,T69,T70
DetectSt->IdleSt	186	Covered	T71
DetectSt->StableSt	191	Covered	T23,T30,T31
IdleSt->DebounceSt	148	Covered	T23,T30,T31
StableSt->IdleSt	206	Covered	T23,T30,T31

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T23,T30,T31
0	1	Covered	T23,T30,T31
0	0	Excluded	T5,T1,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T23,T30,T31
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T23,T30,T31
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T23,T30,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T161
DebounceSt	-	0	0	-	-	-	-	Covered	T23,T30,T31
DetectSt	-	-	-	-	1	-	-	Covered	T71
DetectSt	-	-	-	-	0	1	-	Covered	T23,T30,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T30,T31
StableSt	-	-	-	-	-	-	0	Covered	T23,T30,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	79	0	0
CntIncr_A	7216696	37111	0	0
CntNoWrap_A	7216696	6550564	0	0
DetectStDropOut_A	7216696	1	0	0
DetectedOut_A	7216696	2335	0	0
DetectedPulseOut_A	7216696	37	0	0
DisabledIdleSt_A	7216696	6452465	0	0
DisabledNoDetection_A	7216696	6454877	0	0
EnterDebounceSt_A	7216696	41	0	0
EnterDetectSt_A	7216696	38	0	0
EnterStableSt_A	7216696	37	0	0
PulseIsPulse_A	7216696	37	0	0
StayInStableSt	7216696	2281	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7216696	6146	0	0
gen_low_level_sva.LowLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	20	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7216696	79
T23	8336	2
T30	0	4
T31	0	2
T33	117463	0
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T71	0	2
T72	0	4
T100	23786	0
T149	0	2
T150	0	2
T161	0	1
T185	0	2
T191	0	2
T192	422	0
T193	442	0

CntIncr_A

Name	Attempts	Real Successes
Total	7216696	37111
T23	8336	42
T30	0	144
T31	0	94
T33	117463	0
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T71	0	95
T72	0	128
T100	23786	0
T149	0	51
T150	0	55
T161	0	90
T185	0	82
T191	0	42
T192	422	0
T193	442	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	7216696	6550564
T1	64534	61974
T2	1898	1497
T3	3483	1078
T5	409	8
T6	502	101
T13	402	1
T14	437	36
T15	4238	1287
T16	22713	22267
T17	415	14

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7216696	1
T71	878	1
T74	35216	0
T149	726	0
T190	643	0
T223	402	0
T224	447	0
T225	1136	0
T226	502	0
T227	592	0
T228	444	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7216696	2335
T23	8336	84
T30	0	80
T31	0	136
T33	117463	0
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T72	0	82
T100	23786	0
T141	0	1
T142	0	41
T149	0	42
T150	0	51
T185	0	239
T191	0	45
T192	422	0
T193	442	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7216696	37
T23	8336	1
T30	0	2
T31	0	1
T33	117463	0
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T72	0	2
T100	23786	0
T141	0	1
T142	0	1
T149	0	1
T150	0	1
T185	0	1
T191	0	1
T192	422	0
T193	442	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7216696	6452465
T1	64534	61974
T2	1898	1497
T3	3483	1078
T5	409	8
T6	502	101
T13	402	1
T14	437	36
T15	4238	1287
T16	22713	22267
T17	415	14

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7216696	6454877
T1	64534	62000
T2	1898	1498
T3	3483	1083
T5	409	9
T6	502	102
T13	402	2
T14	437	37
T15	4238	1296
T16	22713	22274
T17	415	15

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7216696	41
T23	8336	1
T30	0	2
T31	0	1
T33	117463	0
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T71	0	1
T72	0	2
T100	23786	0
T149	0	1
T150	0	1
T161	0	1
T185	0	1
T191	0	1
T192	422	0
T193	442	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7216696	38
T23	8336	1
T30	0	2
T31	0	1
T33	117463	0
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T71	0	1
T72	0	2
T100	23786	0
T141	0	1
T149	0	1
T150	0	1
T185	0	1
T191	0	1
T192	422	0
T193	442	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	7216696	37
T23	8336	1
T30	0	2
T31	0	1
T33	117463	0
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T72	0	2
T100	23786	0
T141	0	1
T142	0	1
T149	0	1
T150	0	1
T185	0	1
T191	0	1
T192	422	0
T193	442	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7216696	37
T23	8336	1
T30	0	2
T31	0	1
T33	117463	0
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T72	0	2
T100	23786	0
T141	0	1
T142	0	1
T149	0	1
T150	0	1
T185	0	1
T191	0	1
T192	422	0
T193	442	0

StayInStableSt

Name	Attempts	Real Successes
Total	7216696	2281
T23	8336	83
T30	0	77
T31	0	135
T33	117463	0
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T72	0	79
T100	23786	0
T142	0	39
T149	0	40
T150	0	50
T185	0	237
T191	0	43
T192	422	0
T193	442	0
T194	0	173

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7216696	6146
T1	64534	45
T2	1898	0
T3	3483	7
T4	12671	29
T6	502	5
T13	402	0
T14	437	5
T15	4238	1
T16	22713	20
T17	415	0
T24	0	4
T25	0	22
T45	0	4

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7216696	6553108
T1	64534	62000
T2	1898	1498
T3	3483	1083
T5	409	9
T6	502	102
T13	402	2
T14	437	37
T15	4238	1296
T16	22713	22274
T17	415	15

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7216696	20
T23	8336	1
T30	0	1
T31	0	1
T33	117463	0
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T72	0	1
T100	23786	0
T141	0	1
T150	0	1
T162	0	1
T192	422	0
T193	442	0
T194	0	1
T210	0	1
T221	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T14
1	1	Covered	T1,T6,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T9,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T7,T9,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T9,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T21
1	0	Covered	T1,T6,T14
1	1	Covered	T7,T9,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T21
0	1	Covered	T9
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T21
0	1	Covered	T9,T23,T30
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T21
1	-	Covered	T9,T23,T30

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T21
DetectSt	168	Covered	T7,T9,T21
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T7,T9,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T21
DebounceSt->IdleSt	163	Covered	T69,T70
DetectSt->IdleSt	186	Covered	T9
DetectSt->StableSt	191	Covered	T7,T9,T21
IdleSt->DebounceSt	148	Covered	T7,T9,T21
StableSt->IdleSt	206	Covered	T9,T21,T23

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T9,T21
0	1	Covered	T7,T9,T21
0	0	Excluded	T5,T1,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T21
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T21
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T21
DetectSt	-	-	-	-	1	-	-	Covered	T9
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T23,T30
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	118	0	0
CntIncr_A	7216696	101363	0	0
CntNoWrap_A	7216696	6550525	0	0
DetectStDropOut_A	7216696	1	0	0
DetectedOut_A	7216696	117412	0	0
DetectedPulseOut_A	7216696	57	0	0
DisabledIdleSt_A	7216696	6191712	0	0
DisabledNoDetection_A	7216696	6194134	0	0
EnterDebounceSt_A	7216696	60	0	0
EnterDetectSt_A	7216696	58	0	0
EnterStableSt_A	7216696	57	0	0
PulseIsPulse_A	7216696	57	0	0
StayInStableSt	7216696	117333	0	0
gen_high_level_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	35	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7216696	118
T7	1020	2
T8	3902	0
T9	23434	4
T10	36864	0
T21	0	2
T23	0	2
T25	7798	0
T28	0	2
T30	0	4
T34	0	2
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	4
T149	0	2
T191	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7216696	101363
T7	1020	95
T8	3902	0
T9	23434	134
T10	36864	0
T21	0	99
T23	0	49
T25	7798	0
T28	0	17
T30	0	144
T34	0	94
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	190
T149	0	51
T191	0	42

CntNoWrap_A

Name	Attempts	Real Successes
Total	7216696	6550525
T1	64534	61974
T2	1898	1497
T3	3483	1078
T5	409	8
T6	502	101
T13	402	1
T14	437	36
T15	4238	1287
T16	22713	22267
T17	415	14

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7216696	1
T9	23434	1
T10	36864	0
T11	16698	0
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T117	426	0
T118	793	0
T119	586	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7216696	117412
T7	1020	205
T8	3902	0
T9	23434	196
T10	36864	0
T21	0	112
T23	0	48
T25	7798	0
T28	0	117
T30	0	154
T34	0	53
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	181
T149	0	43
T191	0	162

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7216696	57
T7	1020	1
T8	3902	0
T9	23434	1
T10	36864	0
T21	0	1
T23	0	1
T25	7798	0
T28	0	1
T30	0	2
T34	0	1
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	2
T149	0	1
T191	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7216696	6191712
T1	64534	61974
T2	1898	1497
T3	3483	1078
T5	409	8
T6	502	101
T13	402	1
T14	437	36
T15	4238	1287
T16	22713	22267
T17	415	14

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7216696	6194134
T1	64534	62000
T2	1898	1498
T3	3483	1083
T5	409	9
T6	502	102
T13	402	2
T14	437	37
T15	4238	1296
T16	22713	22274
T17	415	15

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7216696	60
T7	1020	1
T8	3902	0
T9	23434	2
T10	36864	0
T21	0	1
T23	0	1
T25	7798	0
T28	0	1
T30	0	2
T34	0	1
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	2
T149	0	1
T191	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7216696	58
T7	1020	1
T8	3902	0
T9	23434	2
T10	36864	0
T21	0	1
T23	0	1
T25	7798	0
T28	0	1
T30	0	2
T34	0	1
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	2
T149	0	1
T191	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7216696	57
T7	1020	1
T8	3902	0
T9	23434	1
T10	36864	0
T21	0	1
T23	0	1
T25	7798	0
T28	0	1
T30	0	2
T34	0	1
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	2
T149	0	1
T191	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7216696	57
T7	1020	1
T8	3902	0
T9	23434	1
T10	36864	0
T21	0	1
T23	0	1
T25	7798	0
T28	0	1
T30	0	2
T34	0	1
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	2
T149	0	1
T191	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7216696	117333
T7	1020	203
T8	3902	0
T9	23434	195
T10	36864	0
T21	0	110
T23	0	47
T25	7798	0
T28	0	116
T30	0	151
T34	0	51
T35	701	0
T36	732	0
T46	633	0
T47	503	0
T48	403	0
T71	0	178
T149	0	42
T191	0	160

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7216696	6553108
T1	64534	62000
T2	1898	1498
T3	3483	1083
T5	409	9
T6	502	102
T13	402	2
T14	437	37
T15	4238	1296
T16	22713	22274
T17	415	15

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7216696	35
T9	23434	1
T10	36864	0
T11	16698	0
T23	0	1
T28	0	1
T30	0	1
T35	701	0
T36	732	0
T47	503	0
T48	403	0
T71	0	1
T72	0	2
T117	426	0
T118	793	0
T119	586	0
T149	0	1
T161	0	2
T169	0	1
T185	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T14
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T14
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T23,T33,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T21,T23,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T23,T28,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T21,T23
1	0	Covered	T1,T6,T14
1	1	Covered	T21,T23,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T28,T29
0	1	Covered	T23,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T28,T29
0	1	Covered	T72,T209,T210
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T23,T28,T29
1	-	Covered	T72,T209,T210

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T23,T33
DetectSt	168	Covered	T23,T28,T29
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T23,T28,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T23,T28,T29
DebounceSt->IdleSt	163	Covered	T21,T33,T185
DetectSt->IdleSt	186	Covered	T23,T79
DetectSt->StableSt	191	Covered	T23,T28,T29
IdleSt->DebounceSt	148	Covered	T21,T23,T33
StableSt->IdleSt	206	Covered	T23,T208,T72

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T23,T33,T28
0	1	Covered	T21,T23,T33
0	0	Excluded	T5,T1,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T23,T28,T29
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T23,T33
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T23,T28,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T185,T161
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T23,T33
DetectSt	-	-	-	-	1	-	-	Covered	T23,T79
DetectSt	-	-	-	-	0	1	-	Covered	T23,T28,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T72,T209,T210
StableSt	-	-	-	-	-	-	0	Covered	T23,T28,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	75	0	0
CntIncr_A	7216696	2127	0	0
CntNoWrap_A	7216696	6550568	0	0
DetectStDropOut_A	7216696	2	0	0
DetectedOut_A	7216696	2103	0	0
DetectedPulseOut_A	7216696	33	0	0
DisabledIdleSt_A	7216696	6535396	0	0
DisabledNoDetection_A	7216696	6537812	0	0
EnterDebounceSt_A	7216696	41	0	0
EnterDetectSt_A	7216696	35	0	0
EnterStableSt_A	7216696	33	0	0
PulseIsPulse_A	7216696	33	0	0
StayInStableSt	7216696	2048	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7216696	6880	0	0
gen_low_level_sva.LowLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	11	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7216696	75
T23	8336	4
T28	0	2
T29	0	2
T33	117463	1
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T72	0	6
T100	23786	0
T149	0	2
T151	0	2
T169	0	2
T190	0	2
T192	422	0
T193	442	0
T208	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7216696	2127
T21	12106	74
T23	8336	84
T28	0	17
T29	0	48
T33	117463	45
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T149	0	51
T151	0	44
T169	0	10
T190	0	75
T192	422	0
T193	442	0
T208	0	50

CntNoWrap_A

Name	Attempts	Real Successes
Total	7216696	6550568
T1	64534	61974
T2	1898	1497
T3	3483	1078
T5	409	8
T6	502	101
T13	402	1
T14	437	36
T15	4238	1287
T16	22713	22267
T17	415	14

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7216696	2
T23	8336	1
T33	117463	0
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T79	0	1
T100	23786	0
T192	422	0
T193	442	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7216696	2103
T23	8336	36
T28	0	45
T29	0	197
T33	117463	0
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T72	0	153
T100	23786	0
T149	0	119
T151	0	203
T161	0	44
T169	0	46
T190	0	42
T192	422	0
T193	442	0
T208	0	46

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7216696	33
T23	8336	1
T28	0	1
T29	0	1
T33	117463	0
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T72	0	3
T100	23786	0
T149	0	1
T151	0	1
T161	0	1
T169	0	1
T190	0	1
T192	422	0
T193	442	0
T208	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7216696	6535396
T1	64534	61974
T2	1898	1497
T3	3483	1078
T5	409	8
T6	502	101
T13	402	1
T14	437	36
T15	4238	1287
T16	22713	22267
T17	415	14

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7216696	6537812
T1	64534	62000
T2	1898	1498
T3	3483	1083
T5	409	9
T6	502	102
T13	402	2
T14	437	37
T15	4238	1296
T16	22713	22274
T17	415	15

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7216696	41
T21	12106	1
T23	8336	2
T28	0	1
T29	0	1
T33	117463	1
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T149	0	1
T151	0	1
T169	0	1
T190	0	1
T192	422	0
T193	442	0
T208	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7216696	35
T23	8336	2
T28	0	1
T29	0	1
T33	117463	0
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T72	0	3
T100	23786	0
T149	0	1
T151	0	1
T161	0	1
T169	0	1
T190	0	1
T192	422	0
T193	442	0
T208	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7216696	33
T23	8336	1
T28	0	1
T29	0	1
T33	117463	0
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T72	0	3
T100	23786	0
T149	0	1
T151	0	1
T161	0	1
T169	0	1
T190	0	1
T192	422	0
T193	442	0
T208	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7216696	33
T23	8336	1
T28	0	1
T29	0	1
T33	117463	0
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T72	0	3
T100	23786	0
T149	0	1
T151	0	1
T161	0	1
T169	0	1
T190	0	1
T192	422	0
T193	442	0
T208	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7216696	2048
T23	8336	34
T28	0	43
T29	0	195
T33	117463	0
T49	528	0
T50	1227	0
T51	894	0
T52	1510	0
T54	501	0
T72	0	148
T100	23786	0
T149	0	117
T151	0	201
T161	0	42
T169	0	44
T190	0	40
T192	422	0
T193	442	0
T208	0	44

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7216696	6880
T1	64534	40
T2	1898	5
T3	3483	14
T4	12671	28
T6	502	6
T13	402	0
T14	437	3
T15	4238	0
T16	22713	40
T17	415	0
T24	0	5
T25	0	25
T45	0	6

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7216696	6553108
T1	64534	62000
T2	1898	1498
T3	3483	1083
T5	409	9
T6	502	102
T13	402	2
T14	437	37
T15	4238	1296
T16	22713	22274
T17	415	15

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7216696	11
T72	19272	1
T87	23902	0
T106	0	1
T131	0	1
T134	949	0
T161	962	0
T163	0	1
T164	0	1
T184	506	0
T185	8855	0
T186	533	0
T187	503	0
T188	402	0
T189	3003	0
T195	0	1
T197	0	1
T209	0	1
T210	0	1
T229	0	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr