Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T4,T25
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T16,T4,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T16,T4,T25

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T16,T4,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T4,T25
1	0	Covered	T16,T4,T25
1	1	Covered	T16,T4,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T4,T25
0	1	Covered	T38,T64,T84
1	0	Covered	T25,T38,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T4,T11
0	1	Covered	T16,T4,T11
1	0	Covered	T75,T230

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T4,T11
1	-	Covered	T16,T4,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T4,T25
DetectSt	168	Covered	T16,T4,T25
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T16,T4,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T4,T25
DebounceSt->IdleSt	163	Covered	T231,T69,T232
DetectSt->IdleSt	186	Covered	T25,T38,T64
DetectSt->StableSt	191	Covered	T16,T4,T11
IdleSt->DebounceSt	148	Covered	T16,T4,T25
StableSt->IdleSt	206	Covered	T16,T4,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T4,T25
0	1	Covered	T16,T4,T25
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T4,T25
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T16,T4,T25
IdleSt	0	-	-	-	-	-	-	Covered	T16,T4,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T4,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T231,T69,T232
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T4,T25
DetectSt	-	-	-	-	1	-	-	Covered	T25,T38,T64
DetectSt	-	-	-	-	0	1	-	Covered	T16,T4,T11
DetectSt	-	-	-	-	0	0	-	Covered	T16,T4,T25
StableSt	-	-	-	-	-	-	1	Covered	T16,T4,T11
StableSt	-	-	-	-	-	-	0	Covered	T16,T4,T11
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	2761	0	0
CntIncr_A	7216696	97021	0	0
CntNoWrap_A	7216696	6547882	0	0
DetectStDropOut_A	7216696	410	0	0
DetectedOut_A	7216696	78908	0	0
DetectedPulseOut_A	7216696	807	0	0
DisabledIdleSt_A	7216696	6068787	0	0
DisabledNoDetection_A	7216696	6071039	0	0
EnterDebounceSt_A	7216696	1394	0	0
EnterDetectSt_A	7216696	1368	0	0
EnterStableSt_A	7216696	807	0	0
PulseIsPulse_A	7216696	807	0	0
StayInStableSt	7216696	77982	0	0
gen_high_event_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_high_level_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	671	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	2761	0	0
T3	3483	0	0	0
T4	12671	10	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	24	0	0
T12	0	26	0	0
T16	22713	52	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	30	0	0
T38	0	16	0	0
T39	0	24	0	0
T41	0	2	0	0
T42	0	38	0	0
T43	0	36	0	0
T45	442	0	0	0
T46	633	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	97021	0	0
T3	3483	0	0	0
T4	12671	360	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	1068	0	0
T12	0	2444	0	0
T16	22713	1898	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	1091	0	0
T38	0	526	0	0
T39	0	540	0	0
T41	0	21	0	0
T42	0	1178	0	0
T43	0	738	0	0
T45	442	0	0	0
T46	633	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6547882	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22215	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	410	0	0
T32	646	0	0	0
T38	6087	6	0	0
T39	11193	0	0	0
T40	640	0	0	0
T41	452	0	0	0
T42	18410	0	0	0
T60	502	0	0	0
T61	522	0	0	0
T62	427	0	0	0
T63	848	0	0	0
T64	0	33	0	0
T84	0	12	0	0
T85	0	15	0	0
T86	0	17	0	0
T87	0	10	0	0
T88	0	5	0	0
T121	0	4	0	0
T233	0	21	0	0
T234	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	78908	0	0
T3	3483	0	0	0
T4	12671	224	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	1657	0	0
T12	0	1173	0	0
T16	22713	2201	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T39	0	1486	0	0
T41	0	27	0	0
T42	0	2499	0	0
T43	0	440	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	1562	0	0
T235	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	807	0	0
T3	3483	0	0	0
T4	12671	5	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	12	0	0
T12	0	13	0	0
T16	22713	26	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T39	0	12	0	0
T41	0	1	0	0
T42	0	19	0	0
T43	0	18	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	11	0	0
T235	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6068787	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	15317	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6071039	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	15318	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	1394	0	0
T3	3483	0	0	0
T4	12671	5	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	12	0	0
T12	0	13	0	0
T16	22713	26	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	15	0	0
T38	0	8	0	0
T39	0	12	0	0
T41	0	1	0	0
T42	0	19	0	0
T43	0	18	0	0
T45	442	0	0	0
T46	633	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	1368	0	0
T3	3483	0	0	0
T4	12671	5	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	12	0	0
T12	0	13	0	0
T16	22713	26	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	15	0	0
T38	0	8	0	0
T39	0	12	0	0
T41	0	1	0	0
T42	0	19	0	0
T43	0	18	0	0
T45	442	0	0	0
T46	633	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	807	0	0
T3	3483	0	0	0
T4	12671	5	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	12	0	0
T12	0	13	0	0
T16	22713	26	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T39	0	12	0	0
T41	0	1	0	0
T42	0	19	0	0
T43	0	18	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	11	0	0
T235	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	807	0	0
T3	3483	0	0	0
T4	12671	5	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	12	0	0
T12	0	13	0	0
T16	22713	26	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T39	0	12	0	0
T41	0	1	0	0
T42	0	19	0	0
T43	0	18	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	11	0	0
T235	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	77982	0	0
T3	3483	0	0	0
T4	12671	218	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	1643	0	0
T12	0	1160	0	0
T16	22713	2170	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T39	0	1472	0	0
T41	0	25	0	0
T42	0	2477	0	0
T43	0	422	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	1548	0	0
T235	0	35	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	671	0	0
T3	3483	0	0	0
T4	12671	4	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	10	0	0
T12	0	13	0	0
T16	22713	21	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T39	0	10	0	0
T42	0	16	0	0
T43	0	18	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	8	0	0
T235	0	3	0	0
T236	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T16
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T16
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T15,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T15,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T16,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T16
1	0	Covered	T1,T15,T16
1	1	Covered	T1,T15,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T3
0	1	Covered	T33,T68,T89
1	0	Covered	T69,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T16,T3
1	-	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T15,T16
DetectSt	168	Covered	T1,T16,T3
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T16,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T16,T3
DebounceSt->IdleSt	163	Covered	T1,T15,T9
DetectSt->IdleSt	186	Covered	T33,T68,T89
DetectSt->StableSt	191	Covered	T1,T16,T3
IdleSt->DebounceSt	148	Covered	T1,T15,T16
StableSt->IdleSt	206	Covered	T1,T16,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T15,T16
0	1	Covered	T1,T15,T16
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T3
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T15,T16
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T16,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T15,T9
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T15,T16
DetectSt	-	-	-	-	1	-	-	Covered	T33,T68,T89
DetectSt	-	-	-	-	0	1	-	Covered	T1,T16,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T16,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T4
StableSt	-	-	-	-	-	-	0	Covered	T1,T16,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	992	0	0
CntIncr_A	7216696	51701	0	0
CntNoWrap_A	7216696	6549651	0	0
DetectStDropOut_A	7216696	50	0	0
DetectedOut_A	7216696	16004	0	0
DetectedPulseOut_A	7216696	399	0	0
DisabledIdleSt_A	7216696	6163910	0	0
DisabledNoDetection_A	7216696	6165530	0	0
EnterDebounceSt_A	7216696	545	0	0
EnterDetectSt_A	7216696	454	0	0
EnterStableSt_A	7216696	399	0	0
PulseIsPulse_A	7216696	399	0	0
StayInStableSt	7216696	15564	0	0
gen_high_level_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	355	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	992	0	0
T1	64534	39	0	0
T2	1898	0	0	0
T3	3483	2	0	0
T4	12671	2	0	0
T6	502	0	0	0
T9	0	3	0	0
T10	0	14	0	0
T11	0	5	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	1	0	0
T16	22713	8	0	0
T17	415	0	0	0
T39	0	10	0	0
T41	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	51701	0	0
T1	64534	2926	0	0
T2	1898	0	0	0
T3	3483	25	0	0
T4	12671	44	0	0
T6	502	0	0	0
T9	0	45	0	0
T10	0	810	0	0
T11	0	266	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	20	0	0
T16	22713	300	0	0
T17	415	0	0	0
T39	0	295	0	0
T41	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6549651	0	0
T1	64534	61935	0	0
T2	1898	1497	0	0
T3	3483	1076	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1286	0	0
T16	22713	22259	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	50	0	0
T28	2869	0	0	0
T30	2565	0	0	0
T33	117463	3	0	0
T51	894	0	0	0
T52	1510	0	0	0
T55	495	0	0	0
T68	0	3	0	0
T70	0	1	0	0
T89	0	5	0	0
T90	0	10	0	0
T92	0	1	0	0
T94	0	5	0	0
T95	0	5	0	0
T97	0	1	0	0
T98	0	13	0	0
T100	23786	0	0	0
T101	509	0	0	0
T102	502	0	0	0
T103	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	16004	0	0
T1	64534	458	0	0
T2	1898	0	0	0
T3	3483	3	0	0
T4	12671	89	0	0
T6	502	0	0	0
T9	0	3	0	0
T10	0	145	0	0
T11	0	107	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	281	0	0
T17	415	0	0	0
T21	0	85	0	0
T39	0	319	0	0
T42	0	81	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	399	0	0
T1	64534	18	0	0
T2	1898	0	0	0
T3	3483	1	0	0
T4	12671	1	0	0
T6	502	0	0	0
T9	0	1	0	0
T10	0	6	0	0
T11	0	2	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	4	0	0
T17	415	0	0	0
T21	0	3	0	0
T39	0	5	0	0
T42	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6163910	0	0
T1	64534	48644	0	0
T2	1898	1497	0	0
T3	3483	992	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1253	0	0
T16	22713	20071	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6165530	0	0
T1	64534	48646	0	0
T2	1898	1498	0	0
T3	3483	996	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1261	0	0
T16	22713	20073	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	545	0	0
T1	64534	21	0	0
T2	1898	0	0	0
T3	3483	1	0	0
T4	12671	1	0	0
T6	502	0	0	0
T9	0	2	0	0
T10	0	8	0	0
T11	0	3	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	1	0	0
T16	22713	4	0	0
T17	415	0	0	0
T39	0	5	0	0
T41	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	454	0	0
T1	64534	18	0	0
T2	1898	0	0	0
T3	3483	1	0	0
T4	12671	1	0	0
T6	502	0	0	0
T9	0	1	0	0
T10	0	6	0	0
T11	0	2	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	4	0	0
T17	415	0	0	0
T21	0	3	0	0
T39	0	5	0	0
T42	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	399	0	0
T1	64534	18	0	0
T2	1898	0	0	0
T3	3483	1	0	0
T4	12671	1	0	0
T6	502	0	0	0
T9	0	1	0	0
T10	0	6	0	0
T11	0	2	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	4	0	0
T17	415	0	0	0
T21	0	3	0	0
T39	0	5	0	0
T42	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	399	0	0
T1	64534	18	0	0
T2	1898	0	0	0
T3	3483	1	0	0
T4	12671	1	0	0
T6	502	0	0	0
T9	0	1	0	0
T10	0	6	0	0
T11	0	2	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	4	0	0
T17	415	0	0	0
T21	0	3	0	0
T39	0	5	0	0
T42	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	15564	0	0
T1	64534	440	0	0
T2	1898	0	0	0
T3	3483	2	0	0
T4	12671	88	0	0
T6	502	0	0	0
T9	0	2	0	0
T10	0	139	0	0
T11	0	103	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	273	0	0
T17	415	0	0	0
T21	0	82	0	0
T39	0	314	0	0
T42	0	80	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	355	0	0
T1	64534	18	0	0
T2	1898	0	0	0
T3	3483	1	0	0
T4	12671	1	0	0
T6	502	0	0	0
T9	0	1	0	0
T10	0	6	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	3	0	0
T33	0	14	0	0
T39	0	5	0	0
T42	0	1	0	0
T100	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T4,T25
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T16,T4,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T16,T4,T25

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T16,T4,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T4,T25
1	0	Covered	T16,T4,T25
1	1	Covered	T16,T4,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T4,T25
0	1	Covered	T25,T64,T84
1	0	Covered	T25,T11,T73

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T4,T12
0	1	Covered	T16,T4,T12
1	0	Covered	T73,T69,T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T4,T12
1	-	Covered	T16,T4,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T4,T25
DetectSt	168	Covered	T16,T4,T25
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T16,T4,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T4,T25
DebounceSt->IdleSt	163	Covered	T231,T69,T232
DetectSt->IdleSt	186	Covered	T25,T11,T64
DetectSt->StableSt	191	Covered	T16,T4,T12
IdleSt->DebounceSt	148	Covered	T16,T4,T25
StableSt->IdleSt	206	Covered	T16,T4,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T4,T25
0	1	Covered	T16,T4,T25
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T4,T25
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T16,T4,T25
IdleSt	0	-	-	-	-	-	-	Covered	T16,T4,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T4,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T231,T69,T232
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T4,T25
DetectSt	-	-	-	-	1	-	-	Covered	T25,T11,T64
DetectSt	-	-	-	-	0	1	-	Covered	T16,T4,T12
DetectSt	-	-	-	-	0	0	-	Covered	T16,T4,T25
StableSt	-	-	-	-	-	-	1	Covered	T16,T4,T12
StableSt	-	-	-	-	-	-	0	Covered	T16,T4,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	2912	0	0
CntIncr_A	7216696	106459	0	0
CntNoWrap_A	7216696	6547731	0	0
DetectStDropOut_A	7216696	392	0	0
DetectedOut_A	7216696	76833	0	0
DetectedPulseOut_A	7216696	822	0	0
DisabledIdleSt_A	7216696	6070124	0	0
DisabledNoDetection_A	7216696	6072381	0	0
EnterDebounceSt_A	7216696	1470	0	0
EnterDetectSt_A	7216696	1442	0	0
EnterStableSt_A	7216696	822	0	0
PulseIsPulse_A	7216696	822	0	0
StayInStableSt	7216696	75897	0	0
gen_high_event_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_high_level_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	703	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	2912	0	0
T3	3483	0	0	0
T4	12671	20	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	6	0	0
T12	0	46	0	0
T16	22713	10	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	42	0	0
T38	0	8	0	0
T39	0	10	0	0
T42	0	16	0	0
T43	0	54	0	0
T45	442	0	0	0
T46	633	0	0	0
T64	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	106459	0	0
T3	3483	0	0	0
T4	12671	680	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	346	0	0
T12	0	4439	0	0
T16	22713	375	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	1516	0	0
T38	0	212	0	0
T39	0	195	0	0
T42	0	592	0	0
T43	0	1593	0	0
T45	442	0	0	0
T46	633	0	0	0
T64	0	849	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6547731	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22257	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	392	0	0
T8	3902	0	0	0
T9	23434	0	0	0
T10	36864	0	0	0
T11	16698	0	0	0
T25	7798	11	0	0
T35	701	0	0	0
T36	732	0	0	0
T46	633	0	0	0
T47	503	0	0	0
T48	403	0	0	0
T64	0	15	0	0
T74	0	11	0	0
T84	0	10	0	0
T86	0	13	0	0
T87	0	7	0	0
T125	0	3	0	0
T233	0	8	0	0
T237	0	10	0	0
T238	0	14	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	76833	0	0
T3	3483	0	0	0
T4	12671	347	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T12	0	1981	0	0
T16	22713	478	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T38	0	222	0	0
T39	0	504	0	0
T42	0	917	0	0
T43	0	1527	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	2320	0	0
T235	0	344	0	0
T236	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	822	0	0
T3	3483	0	0	0
T4	12671	10	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T12	0	23	0	0
T16	22713	5	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T38	0	4	0	0
T39	0	5	0	0
T42	0	8	0	0
T43	0	27	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	31	0	0
T235	0	10	0	0
T236	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6070124	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	16273	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6072381	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	16278	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	1470	0	0
T3	3483	0	0	0
T4	12671	10	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	3	0	0
T12	0	23	0	0
T16	22713	5	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	21	0	0
T38	0	4	0	0
T39	0	5	0	0
T42	0	8	0	0
T43	0	27	0	0
T45	442	0	0	0
T46	633	0	0	0
T64	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	1442	0	0
T3	3483	0	0	0
T4	12671	10	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	3	0	0
T12	0	23	0	0
T16	22713	5	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	21	0	0
T38	0	4	0	0
T39	0	5	0	0
T42	0	8	0	0
T43	0	27	0	0
T45	442	0	0	0
T46	633	0	0	0
T64	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	822	0	0
T3	3483	0	0	0
T4	12671	10	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T12	0	23	0	0
T16	22713	5	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T38	0	4	0	0
T39	0	5	0	0
T42	0	8	0	0
T43	0	27	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	31	0	0
T235	0	10	0	0
T236	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	822	0	0
T3	3483	0	0	0
T4	12671	10	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T12	0	23	0	0
T16	22713	5	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T38	0	4	0	0
T39	0	5	0	0
T42	0	8	0	0
T43	0	27	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	31	0	0
T235	0	10	0	0
T236	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	75897	0	0
T3	3483	0	0	0
T4	12671	336	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T12	0	1958	0	0
T16	22713	472	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T38	0	218	0	0
T39	0	497	0	0
T42	0	909	0	0
T43	0	1499	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	2286	0	0
T235	0	333	0	0
T236	0	41	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	703	0	0
T3	3483	0	0	0
T4	12671	9	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T12	0	23	0	0
T16	22713	4	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T42	0	8	0	0
T43	0	26	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	28	0	0
T235	0	9	0	0
T236	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T16,T4
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T4
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T4,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T4,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T4
1	0	Covered	T1,T15,T16
1	1	Covered	T1,T4,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T10
0	1	Covered	T1,T33,T239
1	0	Covered	T69,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T10
0	1	Covered	T1,T4,T10
1	0	Covered	T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T4,T10
1	-	Covered	T1,T4,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T4,T10
DetectSt	168	Covered	T1,T4,T10
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T4,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T4,T10
DebounceSt->IdleSt	163	Covered	T1,T68,T240
DetectSt->IdleSt	186	Covered	T1,T33,T239
DetectSt->StableSt	191	Covered	T1,T4,T10
IdleSt->DebounceSt	148	Covered	T1,T4,T10
StableSt->IdleSt	206	Covered	T1,T4,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T4,T10
0	1	Covered	T1,T4,T10
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T10
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T4,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T4,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T68,T240
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T4,T10
DetectSt	-	-	-	-	1	-	-	Covered	T1,T33,T239
DetectSt	-	-	-	-	0	1	-	Covered	T1,T4,T10
DetectSt	-	-	-	-	0	0	-	Covered	T1,T4,T10
StableSt	-	-	-	-	-	-	1	Covered	T1,T4,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T4,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	913	0	0
CntIncr_A	7216696	52792	0	0
CntNoWrap_A	7216696	6549730	0	0
DetectStDropOut_A	7216696	70	0	0
DetectedOut_A	7216696	17743	0	0
DetectedPulseOut_A	7216696	362	0	0
DisabledIdleSt_A	7216696	6161084	0	0
DisabledNoDetection_A	7216696	6162766	0	0
EnterDebounceSt_A	7216696	477	0	0
EnterDetectSt_A	7216696	437	0	0
EnterStableSt_A	7216696	362	0	0
PulseIsPulse_A	7216696	362	0	0
StayInStableSt	7216696	17355	0	0
gen_high_level_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	333	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	913	0	0
T1	64534	17	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	2	0	0
T6	502	0	0	0
T10	0	2	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	2	0	0
T33	0	24	0	0
T37	0	8	0	0
T38	0	2	0	0
T39	0	4	0	0
T43	0	2	0	0
T100	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	52792	0	0
T1	64534	1178	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	83	0	0
T6	502	0	0	0
T10	0	84	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	124	0	0
T33	0	1509	0	0
T37	0	604	0	0
T38	0	49	0	0
T39	0	78	0	0
T43	0	63	0	0
T100	0	116	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6549730	0	0
T1	64534	61957	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22267	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	70	0	0
T1	64534	2	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	0	0	0
T6	502	0	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T33	0	2	0	0
T167	0	1	0	0
T239	0	7	0	0
T241	0	4	0	0
T242	0	7	0	0
T243	0	2	0	0
T244	0	3	0	0
T245	0	4	0	0
T246	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	17743	0	0
T1	64534	311	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	49	0	0
T6	502	0	0	0
T10	0	65	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	67	0	0
T33	0	163	0	0
T37	0	27	0	0
T38	0	95	0	0
T39	0	168	0	0
T43	0	53	0	0
T100	0	93	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	362	0	0
T1	64534	6	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	1	0	0
T6	502	0	0	0
T10	0	1	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	1	0	0
T33	0	10	0	0
T37	0	4	0	0
T38	0	1	0	0
T39	0	2	0	0
T43	0	1	0	0
T100	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6161084	0	0
T1	64534	48644	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	21790	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6162766	0	0
T1	64534	48646	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	21796	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	477	0	0
T1	64534	9	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	1	0	0
T6	502	0	0	0
T10	0	1	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	1	0	0
T33	0	12	0	0
T37	0	4	0	0
T38	0	1	0	0
T39	0	2	0	0
T43	0	1	0	0
T100	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	437	0	0
T1	64534	8	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	1	0	0
T6	502	0	0	0
T10	0	1	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	1	0	0
T33	0	12	0	0
T37	0	4	0	0
T38	0	1	0	0
T39	0	2	0	0
T43	0	1	0	0
T100	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	362	0	0
T1	64534	6	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	1	0	0
T6	502	0	0	0
T10	0	1	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	1	0	0
T33	0	10	0	0
T37	0	4	0	0
T38	0	1	0	0
T39	0	2	0	0
T43	0	1	0	0
T100	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	362	0	0
T1	64534	6	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	1	0	0
T6	502	0	0	0
T10	0	1	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	1	0	0
T33	0	10	0	0
T37	0	4	0	0
T38	0	1	0	0
T39	0	2	0	0
T43	0	1	0	0
T100	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	17355	0	0
T1	64534	305	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	48	0	0
T6	502	0	0	0
T10	0	64	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	66	0	0
T33	0	153	0	0
T37	0	23	0	0
T38	0	94	0	0
T39	0	166	0	0
T43	0	51	0	0
T100	0	92	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	333	0	0
T1	64534	6	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	1	0	0
T6	502	0	0	0
T10	0	1	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	1	0	0
T33	0	10	0	0
T37	0	4	0	0
T38	0	1	0	0
T39	0	2	0	0
T100	0	1	0	0
T113	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T4,T25
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T16,T4,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T16,T4,T25

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T16,T4,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T4,T25
1	0	Covered	T16,T4,T11
1	1	Covered	T16,T4,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T4,T25
0	1	Covered	T64,T113,T84
1	0	Covered	T113,T235,T247

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T4,T25
0	1	Covered	T16,T4,T25
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T4,T25
1	-	Covered	T16,T4,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T4,T25
DetectSt	168	Covered	T16,T4,T25
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T16,T4,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T4,T25
DebounceSt->IdleSt	163	Covered	T231,T69,T232
DetectSt->IdleSt	186	Covered	T64,T113,T235
DetectSt->StableSt	191	Covered	T16,T4,T25
IdleSt->DebounceSt	148	Covered	T16,T4,T25
StableSt->IdleSt	206	Covered	T16,T4,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T4,T25
0	1	Covered	T16,T4,T25
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T4,T25
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T16,T4,T25
IdleSt	0	-	-	-	-	-	-	Covered	T16,T4,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T4,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T231,T69,T232
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T4,T25
DetectSt	-	-	-	-	1	-	-	Covered	T64,T113,T235
DetectSt	-	-	-	-	0	1	-	Covered	T16,T4,T25
DetectSt	-	-	-	-	0	0	-	Covered	T16,T4,T25
StableSt	-	-	-	-	-	-	1	Covered	T16,T4,T25
StableSt	-	-	-	-	-	-	0	Covered	T16,T4,T25
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	2933	0	0
CntIncr_A	7216696	100171	0	0
CntNoWrap_A	7216696	6547710	0	0
DetectStDropOut_A	7216696	387	0	0
DetectedOut_A	7216696	82288	0	0
DetectedPulseOut_A	7216696	872	0	0
DisabledIdleSt_A	7216696	6063383	0	0
DisabledNoDetection_A	7216696	6065639	0	0
EnterDebounceSt_A	7216696	1482	0	0
EnterDetectSt_A	7216696	1452	0	0
EnterStableSt_A	7216696	872	0	0
PulseIsPulse_A	7216696	872	0	0
StayInStableSt	7216696	81301	0	0
gen_high_event_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_high_level_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	756	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	2933	0	0
T3	3483	0	0	0
T4	12671	22	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	8	0	0
T12	0	20	0	0
T16	22713	36	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	52	0	0
T38	0	4	0	0
T39	0	28	0	0
T42	0	62	0	0
T43	0	44	0	0
T45	442	0	0	0
T46	633	0	0	0
T64	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	100171	0	0
T3	3483	0	0	0
T4	12671	880	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	300	0	0
T12	0	1760	0	0
T16	22713	1566	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	1742	0	0
T38	0	110	0	0
T39	0	420	0	0
T42	0	2263	0	0
T43	0	902	0	0
T45	442	0	0	0
T46	633	0	0	0
T64	0	848	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6547710	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22231	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	387	0	0
T31	935	0	0	0
T53	164830	0	0	0
T56	495	0	0	0
T64	5465	15	0	0
T65	2816	0	0	0
T68	27615	0	0	0
T84	0	28	0	0
T86	0	13	0	0
T88	0	22	0	0
T113	13348	9	0	0
T234	0	10	0	0
T238	0	16	0	0
T248	0	3	0	0
T249	0	8	0	0
T250	0	11	0	0
T251	503	0	0	0
T252	487	0	0	0
T253	8402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	82288	0	0
T3	3483	0	0	0
T4	12671	1743	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	168	0	0
T12	0	1025	0	0
T16	22713	2235	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	1702	0	0
T38	0	28	0	0
T39	0	415	0	0
T42	0	2864	0	0
T43	0	1764	0	0
T45	442	0	0	0
T46	633	0	0	0
T236	0	1084	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	872	0	0
T3	3483	0	0	0
T4	12671	11	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	4	0	0
T12	0	10	0	0
T16	22713	18	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	26	0	0
T38	0	2	0	0
T39	0	14	0	0
T42	0	31	0	0
T43	0	22	0	0
T45	442	0	0	0
T46	633	0	0	0
T236	0	15	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6063383	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	14740	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6065639	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	14742	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	1482	0	0
T3	3483	0	0	0
T4	12671	11	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	4	0	0
T12	0	10	0	0
T16	22713	18	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	26	0	0
T38	0	2	0	0
T39	0	14	0	0
T42	0	31	0	0
T43	0	22	0	0
T45	442	0	0	0
T46	633	0	0	0
T64	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	1452	0	0
T3	3483	0	0	0
T4	12671	11	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	4	0	0
T12	0	10	0	0
T16	22713	18	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	26	0	0
T38	0	2	0	0
T39	0	14	0	0
T42	0	31	0	0
T43	0	22	0	0
T45	442	0	0	0
T46	633	0	0	0
T64	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	872	0	0
T3	3483	0	0	0
T4	12671	11	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	4	0	0
T12	0	10	0	0
T16	22713	18	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	26	0	0
T38	0	2	0	0
T39	0	14	0	0
T42	0	31	0	0
T43	0	22	0	0
T45	442	0	0	0
T46	633	0	0	0
T236	0	15	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	872	0	0
T3	3483	0	0	0
T4	12671	11	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	4	0	0
T12	0	10	0	0
T16	22713	18	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	26	0	0
T38	0	2	0	0
T39	0	14	0	0
T42	0	31	0	0
T43	0	22	0	0
T45	442	0	0	0
T46	633	0	0	0
T236	0	15	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	81301	0	0
T3	3483	0	0	0
T4	12671	1730	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	164	0	0
T12	0	1015	0	0
T16	22713	2213	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	1676	0	0
T38	0	26	0	0
T39	0	401	0	0
T42	0	2830	0	0
T43	0	1742	0	0
T45	442	0	0	0
T46	633	0	0	0
T236	0	1069	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	756	0	0
T3	3483	0	0	0
T4	12671	9	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	4	0	0
T12	0	10	0	0
T16	22713	14	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	26	0	0
T38	0	2	0	0
T39	0	14	0	0
T42	0	28	0	0
T43	0	22	0	0
T45	442	0	0	0
T46	633	0	0	0
T236	0	15	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T16,T4
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T4
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T16,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T16,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T16,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T4
1	0	Covered	T1,T15,T16
1	1	Covered	T1,T16,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T4
0	1	Covered	T254,T91,T246
1	0	Covered	T69,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T4
0	1	Covered	T1,T16,T4
1	0	Covered	T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T16,T4
1	-	Covered	T1,T16,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T16,T4
DetectSt	168	Covered	T1,T16,T4
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T16,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T16,T4
DebounceSt->IdleSt	163	Covered	T1,T10,T37
DetectSt->IdleSt	186	Covered	T255,T254,T91
DetectSt->StableSt	191	Covered	T1,T16,T4
IdleSt->DebounceSt	148	Covered	T1,T16,T4
StableSt->IdleSt	206	Covered	T1,T16,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T16,T4
0	1	Covered	T1,T16,T4
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T4
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T16,T4
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T16,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T10,T37
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T16,T4
DetectSt	-	-	-	-	1	-	-	Covered	T254,T91,T69
DetectSt	-	-	-	-	0	1	-	Covered	T1,T16,T4
DetectSt	-	-	-	-	0	0	-	Covered	T1,T16,T4
StableSt	-	-	-	-	-	-	1	Covered	T1,T16,T4
StableSt	-	-	-	-	-	-	0	Covered	T1,T16,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	968	0	0
CntIncr_A	7216696	53629	0	0
CntNoWrap_A	7216696	6549675	0	0
DetectStDropOut_A	7216696	33	0	0
DetectedOut_A	7216696	19660	0	0
DetectedPulseOut_A	7216696	420	0	0
DisabledIdleSt_A	7216696	6168999	0	0
DisabledNoDetection_A	7216696	6170707	0	0
EnterDebounceSt_A	7216696	512	0	0
EnterDetectSt_A	7216696	457	0	0
EnterStableSt_A	7216696	420	0	0
PulseIsPulse_A	7216696	420	0	0
StayInStableSt	7216696	19212	0	0
gen_high_level_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	389	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	968	0	0
T1	64534	23	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	8	0	0
T6	502	0	0	0
T9	0	4	0	0
T10	0	17	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	8	0	0
T17	415	0	0	0
T21	0	2	0	0
T25	0	4	0	0
T37	0	14	0	0
T42	0	6	0	0
T43	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	53629	0	0
T1	64534	1337	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	260	0	0
T6	502	0	0	0
T9	0	394	0	0
T10	0	726	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	300	0	0
T17	415	0	0	0
T21	0	181	0	0
T25	0	186	0	0
T37	0	626	0	0
T42	0	177	0	0
T43	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6549675	0	0
T1	64534	61951	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22259	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	33	0	0
T70	0	1	0	0
T80	0	4	0	0
T91	0	1	0	0
T98	0	7	0	0
T131	48530	0	0	0
T243	35821	0	0	0
T246	0	1	0	0
T254	34891	7	0	0
T256	0	7	0	0
T257	0	3	0	0
T258	0	2	0	0
T259	409	0	0	0
T260	494	0	0	0
T261	429	0	0	0
T262	448	0	0	0
T263	523	0	0	0
T264	9028	0	0	0
T265	752	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	19660	0	0
T1	64534	322	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	269	0	0
T6	502	0	0	0
T9	0	27	0	0
T10	0	498	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	285	0	0
T17	415	0	0	0
T21	0	10	0	0
T25	0	257	0	0
T37	0	431	0	0
T42	0	289	0	0
T43	0	67	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	420	0	0
T1	64534	10	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	4	0	0
T6	502	0	0	0
T9	0	2	0	0
T10	0	8	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	4	0	0
T17	415	0	0	0
T21	0	1	0	0
T25	0	2	0	0
T37	0	6	0	0
T42	0	3	0	0
T43	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6168999	0	0
T1	64534	48644	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	20036	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6170707	0	0
T1	64534	48646	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	20039	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	512	0	0
T1	64534	13	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	4	0	0
T6	502	0	0	0
T9	0	2	0	0
T10	0	9	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	4	0	0
T17	415	0	0	0
T21	0	1	0	0
T25	0	2	0	0
T37	0	8	0	0
T42	0	3	0	0
T43	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	457	0	0
T1	64534	10	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	4	0	0
T6	502	0	0	0
T9	0	2	0	0
T10	0	8	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	4	0	0
T17	415	0	0	0
T21	0	1	0	0
T25	0	2	0	0
T37	0	6	0	0
T42	0	3	0	0
T43	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	420	0	0
T1	64534	10	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	4	0	0
T6	502	0	0	0
T9	0	2	0	0
T10	0	8	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	4	0	0
T17	415	0	0	0
T21	0	1	0	0
T25	0	2	0	0
T37	0	6	0	0
T42	0	3	0	0
T43	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	420	0	0
T1	64534	10	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	4	0	0
T6	502	0	0	0
T9	0	2	0	0
T10	0	8	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	4	0	0
T17	415	0	0	0
T21	0	1	0	0
T25	0	2	0	0
T37	0	6	0	0
T42	0	3	0	0
T43	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	19212	0	0
T1	64534	312	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	265	0	0
T6	502	0	0	0
T9	0	25	0	0
T10	0	490	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	280	0	0
T17	415	0	0	0
T21	0	9	0	0
T25	0	255	0	0
T37	0	425	0	0
T42	0	283	0	0
T43	0	66	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	389	0	0
T1	64534	10	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	4	0	0
T6	502	0	0	0
T9	0	2	0	0
T10	0	8	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	3	0	0
T17	415	0	0	0
T21	0	1	0	0
T25	0	2	0	0
T33	0	23	0	0
T37	0	6	0	0
T43	0	1	0	0