Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T4,T25
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T16,T4,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T16,T4,T25

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T16,T4,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T4,T25
1	0	Covered	T16,T4,T25
1	1	Covered	T16,T4,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T4,T25
0	1	Covered	T38,T64,T84
1	0	Covered	T38,T43,T73

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T4,T25
0	1	Covered	T16,T4,T25
1	0	Covered	T74,T266

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T4,T25
1	-	Covered	T16,T4,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T4,T25
DetectSt	168	Covered	T16,T4,T25
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T16,T4,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T4,T25
DebounceSt->IdleSt	163	Covered	T231,T69,T232
DetectSt->IdleSt	186	Covered	T38,T43,T64
DetectSt->StableSt	191	Covered	T16,T4,T25
IdleSt->DebounceSt	148	Covered	T16,T4,T25
StableSt->IdleSt	206	Covered	T16,T4,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T4,T25
0	1	Covered	T16,T4,T25
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T4,T25
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T16,T4,T25
IdleSt	0	-	-	-	-	-	-	Covered	T16,T4,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T4,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T231,T69,T232
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T4,T25
DetectSt	-	-	-	-	1	-	-	Covered	T38,T43,T64
DetectSt	-	-	-	-	0	1	-	Covered	T16,T4,T25
DetectSt	-	-	-	-	0	0	-	Covered	T16,T4,T25
StableSt	-	-	-	-	-	-	1	Covered	T16,T4,T25
StableSt	-	-	-	-	-	-	0	Covered	T16,T4,T25
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	2861	0	0
CntIncr_A	7216696	102185	0	0
CntNoWrap_A	7216696	6547782	0	0
DetectStDropOut_A	7216696	386	0	0
DetectedOut_A	7216696	81443	0	0
DetectedPulseOut_A	7216696	792	0	0
DisabledIdleSt_A	7216696	6070744	0	0
DisabledNoDetection_A	7216696	6073025	0	0
EnterDebounceSt_A	7216696	1447	0	0
EnterDetectSt_A	7216696	1417	0	0
EnterStableSt_A	7216696	792	0	0
PulseIsPulse_A	7216696	792	0	0
StayInStableSt	7216696	80561	0	0
gen_high_event_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_high_level_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	697	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	2861	0	0
T3	3483	0	0	0
T4	12671	14	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	44	0	0
T12	0	62	0	0
T16	22713	20	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	30	0	0
T38	0	30	0	0
T39	0	32	0	0
T42	0	32	0	0
T43	0	16	0	0
T45	442	0	0	0
T46	633	0	0	0
T64	0	47	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	102185	0	0
T3	3483	0	0	0
T4	12671	406	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	1408	0	0
T12	0	5332	0	0
T16	22713	890	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	720	0	0
T38	0	991	0	0
T39	0	816	0	0
T42	0	1488	0	0
T43	0	508	0	0
T45	442	0	0	0
T46	633	0	0	0
T64	0	1368	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6547782	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22247	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	386	0	0
T32	646	0	0	0
T38	6087	11	0	0
T39	11193	0	0	0
T40	640	0	0	0
T41	452	0	0	0
T42	18410	0	0	0
T60	502	0	0	0
T61	522	0	0	0
T62	427	0	0	0
T63	848	0	0	0
T64	0	23	0	0
T74	0	17	0	0
T84	0	3	0	0
T86	0	16	0	0
T87	0	11	0	0
T88	0	10	0	0
T248	0	3	0	0
T267	0	5	0	0
T268	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	81443	0	0
T3	3483	0	0	0
T4	12671	356	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	2022	0	0
T12	0	5562	0	0
T16	22713	820	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	549	0	0
T39	0	1050	0	0
T42	0	890	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	630	0	0
T235	0	2143	0	0
T236	0	2827	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	792	0	0
T3	3483	0	0	0
T4	12671	7	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	22	0	0
T12	0	31	0	0
T16	22713	10	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	15	0	0
T39	0	16	0	0
T42	0	16	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	4	0	0
T235	0	25	0	0
T236	0	28	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6070744	0	0
T1	64534	61974	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	15965	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6073025	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	15969	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	1447	0	0
T3	3483	0	0	0
T4	12671	7	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	22	0	0
T12	0	31	0	0
T16	22713	10	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	15	0	0
T38	0	15	0	0
T39	0	16	0	0
T42	0	16	0	0
T43	0	8	0	0
T45	442	0	0	0
T46	633	0	0	0
T64	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	1417	0	0
T3	3483	0	0	0
T4	12671	7	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	22	0	0
T12	0	31	0	0
T16	22713	10	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	15	0	0
T38	0	15	0	0
T39	0	16	0	0
T42	0	16	0	0
T43	0	8	0	0
T45	442	0	0	0
T46	633	0	0	0
T64	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	792	0	0
T3	3483	0	0	0
T4	12671	7	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	22	0	0
T12	0	31	0	0
T16	22713	10	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	15	0	0
T39	0	16	0	0
T42	0	16	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	4	0	0
T235	0	25	0	0
T236	0	28	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	792	0	0
T3	3483	0	0	0
T4	12671	7	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	22	0	0
T12	0	31	0	0
T16	22713	10	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	15	0	0
T39	0	16	0	0
T42	0	16	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	4	0	0
T235	0	25	0	0
T236	0	28	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	80561	0	0
T3	3483	0	0	0
T4	12671	348	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	1999	0	0
T12	0	5531	0	0
T16	22713	808	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	534	0	0
T39	0	1033	0	0
T42	0	874	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	625	0	0
T235	0	2118	0	0
T236	0	2796	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	697	0	0
T3	3483	0	0	0
T4	12671	6	0	0
T7	1020	0	0	0
T8	3902	0	0	0
T11	0	21	0	0
T12	0	31	0	0
T16	22713	8	0	0
T17	415	0	0	0
T24	522	0	0	0
T25	7798	15	0	0
T39	0	15	0	0
T42	0	16	0	0
T45	442	0	0	0
T46	633	0	0	0
T113	0	3	0	0
T235	0	25	0	0
T236	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T16,T4
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T4
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T16,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T16,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T16,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T4
1	0	Covered	T1,T15,T16
1	1	Covered	T1,T16,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T4
0	1	Covered	T33,T68,T269
1	0	Covered	T69,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T4
0	1	Covered	T1,T4,T9
1	0	Covered	T69,T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T16,T4
1	-	Covered	T1,T4,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T16,T4
DetectSt	168	Covered	T1,T16,T4
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T16,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T16,T4
DebounceSt->IdleSt	163	Covered	T1,T100,T269
DetectSt->IdleSt	186	Covered	T33,T68,T269
DetectSt->StableSt	191	Covered	T1,T16,T4
IdleSt->DebounceSt	148	Covered	T1,T16,T4
StableSt->IdleSt	206	Covered	T1,T16,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T16,T4
0	1	Covered	T1,T16,T4
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T4
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T16,T4
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T16,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T100,T269
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T16,T4
DetectSt	-	-	-	-	1	-	-	Covered	T33,T68,T269
DetectSt	-	-	-	-	0	1	-	Covered	T1,T16,T4
DetectSt	-	-	-	-	0	0	-	Covered	T1,T16,T4
StableSt	-	-	-	-	-	-	1	Covered	T1,T4,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T16,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7216696	936	0	0
CntIncr_A	7216696	56395	0	0
CntNoWrap_A	7216696	6549707	0	0
DetectStDropOut_A	7216696	65	0	0
DetectedOut_A	7216696	14202	0	0
DetectedPulseOut_A	7216696	377	0	0
DisabledIdleSt_A	7216696	6160986	0	0
DisabledNoDetection_A	7216696	6162702	0	0
EnterDebounceSt_A	7216696	490	0	0
EnterDetectSt_A	7216696	446	0	0
EnterStableSt_A	7216696	377	0	0
PulseIsPulse_A	7216696	377	0	0
StayInStableSt	7216696	13789	0	0
gen_high_level_sva.HighLevelEvent_A	7216696	6553108	0	0
gen_not_sticky_sva.StableStDropOut_A	7216696	337	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	936	0	0
T1	64534	19	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	2	0	0
T6	502	0	0	0
T9	0	4	0	0
T10	0	6	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	4	0	0
T17	415	0	0	0
T37	0	4	0	0
T39	0	8	0	0
T42	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	56395	0	0
T1	64534	1078	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	68	0	0
T6	502	0	0	0
T9	0	374	0	0
T10	0	339	0	0
T11	0	79	0	0
T12	0	172	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	156	0	0
T17	415	0	0	0
T37	0	282	0	0
T39	0	172	0	0
T42	0	392	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6549707	0	0
T1	64534	61955	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	22263	0	0
T17	415	14	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	65	0	0
T28	2869	0	0	0
T30	2565	0	0	0
T33	117463	7	0	0
T51	894	0	0	0
T52	1510	0	0	0
T55	495	0	0	0
T68	0	2	0	0
T100	23786	0	0	0
T101	509	0	0	0
T102	502	0	0	0
T103	423	0	0	0
T131	0	2	0	0
T243	0	12	0	0
T255	0	7	0	0
T269	0	4	0	0
T270	0	4	0	0
T271	0	5	0	0
T272	0	4	0	0
T273	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	14202	0	0
T1	64534	360	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	64	0	0
T6	502	0	0	0
T9	0	51	0	0
T10	0	106	0	0
T11	0	83	0	0
T12	0	49	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	135	0	0
T17	415	0	0	0
T37	0	34	0	0
T39	0	321	0	0
T42	0	234	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	377	0	0
T1	64534	9	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	1	0	0
T6	502	0	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	2	0	0
T17	415	0	0	0
T37	0	2	0	0
T39	0	4	0	0
T42	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6160986	0	0
T1	64534	48646	0	0
T2	1898	1497	0	0
T3	3483	1078	0	0
T5	409	8	0	0
T6	502	101	0	0
T13	402	1	0	0
T14	437	36	0	0
T15	4238	1287	0	0
T16	22713	21449	0	0
T17	415	14	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6162702	0	0
T1	64534	48648	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	21454	0	0
T17	415	15	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	490	0	0
T1	64534	10	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	1	0	0
T6	502	0	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	2	0	0
T17	415	0	0	0
T37	0	2	0	0
T39	0	4	0	0
T42	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	446	0	0
T1	64534	9	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	1	0	0
T6	502	0	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	2	0	0
T17	415	0	0	0
T37	0	2	0	0
T39	0	4	0	0
T42	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	377	0	0
T1	64534	9	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	1	0	0
T6	502	0	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	2	0	0
T17	415	0	0	0
T37	0	2	0	0
T39	0	4	0	0
T42	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	377	0	0
T1	64534	9	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	1	0	0
T6	502	0	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	2	0	0
T17	415	0	0	0
T37	0	2	0	0
T39	0	4	0	0
T42	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	13789	0	0
T1	64534	351	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	63	0	0
T6	502	0	0	0
T9	0	49	0	0
T10	0	103	0	0
T11	0	82	0	0
T12	0	48	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	131	0	0
T17	415	0	0	0
T37	0	32	0	0
T39	0	317	0	0
T42	0	230	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	6553108	0	0
T1	64534	62000	0	0
T2	1898	1498	0	0
T3	3483	1083	0	0
T5	409	9	0	0
T6	502	102	0	0
T13	402	2	0	0
T14	437	37	0	0
T15	4238	1296	0	0
T16	22713	22274	0	0
T17	415	15	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7216696	337	0	0
T1	64534	9	0	0
T2	1898	0	0	0
T3	3483	0	0	0
T4	12671	1	0	0
T6	502	0	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	402	0	0	0
T14	437	0	0	0
T15	4238	0	0	0
T16	22713	0	0	0
T17	415	0	0	0
T21	0	2	0	0
T37	0	2	0	0
T39	0	4	0	0
T42	0	4	0	0