Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1249995120	11023	0	0
auto_block_debounce_ctl_rd_A	1249995120	2020	0	0
auto_block_out_ctl_rd_A	1249995120	3276	0	0
com_det_ctl_0_rd_A	1249995120	3335	0	0
com_det_ctl_1_rd_A	1249995120	3622	0	0
com_det_ctl_2_rd_A	1249995120	3613	0	0
com_det_ctl_3_rd_A	1249995120	3524	0	0
com_out_ctl_0_rd_A	1249995120	4436	0	0
com_out_ctl_1_rd_A	1249995120	4973	0	0
com_out_ctl_2_rd_A	1249995120	4409	0	0
com_out_ctl_3_rd_A	1249995120	4511	0	0
com_pre_det_ctl_0_rd_A	1249995120	1439	0	0
com_pre_det_ctl_1_rd_A	1249995120	1616	0	0
com_pre_det_ctl_2_rd_A	1249995120	1374	0	0
com_pre_det_ctl_3_rd_A	1249995120	1580	0	0
com_pre_sel_ctl_0_rd_A	1249995120	4650	0	0
com_pre_sel_ctl_1_rd_A	1249995120	4658	0	0
com_pre_sel_ctl_2_rd_A	1249995120	4594	0	0
com_pre_sel_ctl_3_rd_A	1249995120	4805	0	0
com_sel_ctl_0_rd_A	1249995120	4680	0	0
com_sel_ctl_1_rd_A	1249995120	4823	0	0
com_sel_ctl_2_rd_A	1249995120	4928	0	0
com_sel_ctl_3_rd_A	1249995120	4890	0	0
ec_rst_ctl_rd_A	1249995120	2512	0	0
intr_enable_rd_A	1249995120	2161	0	0
key_intr_ctl_rd_A	1249995120	5947	0	0
key_intr_debounce_ctl_rd_A	1249995120	1371	0	0
key_invert_ctl_rd_A	1249995120	7618	0	0
pin_allowed_ctl_rd_A	1249995120	8333	0	0
pin_out_ctl_rd_A	1249995120	5516	0	0
pin_out_value_rd_A	1249995120	5758	0	0
regwen_rd_A	1249995120	1728	0	0
ulp_ac_debounce_ctl_rd_A	1249995120	1628	0	0
ulp_ctl_rd_A	1249995120	1646	0	0
ulp_lid_debounce_ctl_rd_A	1249995120	1627	0	0
ulp_pwrb_debounce_ctl_rd_A	1249995120	1651	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	11023	0	0
T30	175865	0	0	0
T35	234057	2	0	0
T36	205202	0	0	0
T40	229141	0	0	0
T43	0	18	0	0
T44	196347	0	0	0
T45	0	19	0	0
T51	225213	0	0	0
T57	0	5	0	0
T63	0	2	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T93	0	23	0	0
T111	112094	0	0	0
T122	0	7	0	0
T181	86358	0	0	0
T183	0	11	0	0
T269	0	5	0	0
T270	0	7	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	2020	0	0
T30	175865	0	0	0
T31	0	7	0	0
T35	234057	11	0	0
T36	205202	0	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T54	0	16	0	0
T57	0	47	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T111	112094	0	0	0
T113	0	15	0	0
T165	0	4	0	0
T181	86358	0	0	0
T269	0	16	0	0
T270	0	36	0	0
T283	0	9	0	0
T284	0	5	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	3276	0	0
T30	175865	0	0	0
T31	0	15	0	0
T35	234057	12	0	0
T36	205202	0	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T54	0	11	0	0
T57	0	36	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T111	112094	0	0	0
T113	0	6	0	0
T165	0	10	0	0
T181	86358	0	0	0
T269	0	27	0	0
T270	0	37	0	0
T283	0	14	0	0
T284	0	15	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	3335	0	0
T25	34735	0	0	0
T30	175865	0	0	0
T36	205202	77	0	0
T37	0	46	0	0
T38	0	55	0	0
T39	0	14	0	0
T59	646568	0	0	0
T60	449263	0	0	0
T62	192912	0	0	0
T67	62197	0	0	0
T79	0	63	0	0
T138	141841	0	0	0
T139	44583	0	0	0
T140	126643	0	0	0
T226	0	43	0	0
T237	0	48	0	0
T238	0	50	0	0
T269	0	10	0	0
T270	0	16	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	3622	0	0
T30	175865	0	0	0
T35	234057	29	0	0
T36	205202	66	0	0
T37	0	59	0	0
T38	0	82	0	0
T39	0	28	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T79	0	53	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T226	0	52	0	0
T237	0	38	0	0
T269	0	16	0	0
T270	0	15	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	3613	0	0
T30	175865	0	0	0
T35	234057	20	0	0
T36	205202	44	0	0
T37	0	49	0	0
T38	0	69	0	0
T39	0	17	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T79	0	56	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T226	0	45	0	0
T237	0	35	0	0
T269	0	20	0	0
T270	0	20	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	3524	0	0
T30	175865	0	0	0
T35	234057	21	0	0
T36	205202	76	0	0
T37	0	62	0	0
T38	0	80	0	0
T39	0	12	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T79	0	49	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T226	0	44	0	0
T237	0	40	0	0
T269	0	22	0	0
T270	0	36	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	4436	0	0
T30	175865	0	0	0
T35	234057	14	0	0
T36	205202	67	0	0
T37	0	57	0	0
T38	0	76	0	0
T39	0	28	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T79	0	51	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T226	0	50	0	0
T237	0	39	0	0
T269	0	12	0	0
T270	0	16	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	4973	0	0
T30	175865	0	0	0
T35	234057	22	0	0
T36	205202	74	0	0
T37	0	73	0	0
T38	0	75	0	0
T39	0	18	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T79	0	43	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T226	0	48	0	0
T237	0	50	0	0
T269	0	17	0	0
T270	0	27	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	4409	0	0
T30	175865	0	0	0
T35	234057	16	0	0
T36	205202	93	0	0
T37	0	46	0	0
T38	0	64	0	0
T39	0	34	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T79	0	57	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T226	0	68	0	0
T237	0	47	0	0
T269	0	11	0	0
T270	0	16	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	4511	0	0
T30	175865	0	0	0
T35	234057	13	0	0
T36	205202	84	0	0
T37	0	33	0	0
T38	0	58	0	0
T39	0	30	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T79	0	59	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T226	0	39	0	0
T237	0	33	0	0
T269	0	16	0	0
T270	0	22	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	1439	0	0
T30	175865	0	0	0
T35	234057	6	0	0
T36	205202	0	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T95	0	10	0	0
T96	0	2	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T194	0	23	0	0
T214	0	17	0	0
T253	0	4	0	0
T269	0	7	0	0
T270	0	27	0	0
T285	0	9	0	0
T286	0	33	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	1616	0	0
T30	175865	0	0	0
T35	234057	17	0	0
T36	205202	0	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T95	0	37	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T194	0	32	0	0
T214	0	15	0	0
T253	0	16	0	0
T269	0	13	0	0
T270	0	28	0	0
T285	0	14	0	0
T286	0	25	0	0
T287	0	13	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	1374	0	0
T30	175865	0	0	0
T35	234057	24	0	0
T36	205202	0	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T95	0	23	0	0
T96	0	6	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T194	0	26	0	0
T214	0	29	0	0
T253	0	6	0	0
T269	0	9	0	0
T270	0	18	0	0
T285	0	6	0	0
T286	0	19	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	1580	0	0
T30	175865	0	0	0
T35	234057	16	0	0
T36	205202	0	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T95	0	9	0	0
T96	0	5	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T194	0	27	0	0
T214	0	24	0	0
T253	0	16	0	0
T269	0	15	0	0
T270	0	26	0	0
T285	0	6	0	0
T286	0	20	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	4650	0	0
T30	175865	0	0	0
T35	234057	12	0	0
T36	205202	78	0	0
T37	0	50	0	0
T38	0	64	0	0
T39	0	48	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T57	0	5	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T79	0	65	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T226	0	50	0	0
T237	0	56	0	0
T269	0	9	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	4658	0	0
T30	175865	0	0	0
T35	234057	8	0	0
T36	205202	61	0	0
T37	0	34	0	0
T38	0	41	0	0
T39	0	16	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T79	0	47	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T226	0	54	0	0
T237	0	53	0	0
T269	0	14	0	0
T270	0	20	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	4594	0	0
T30	175865	0	0	0
T35	234057	11	0	0
T36	205202	49	0	0
T37	0	60	0	0
T38	0	85	0	0
T39	0	33	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T79	0	64	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T226	0	51	0	0
T237	0	40	0	0
T269	0	3	0	0
T270	0	22	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	4805	0	0
T30	175865	0	0	0
T35	234057	15	0	0
T36	205202	74	0	0
T37	0	44	0	0
T38	0	72	0	0
T39	0	42	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T79	0	43	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T226	0	37	0	0
T237	0	38	0	0
T269	0	12	0	0
T270	0	24	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	4680	0	0
T30	175865	0	0	0
T35	234057	12	0	0
T36	205202	42	0	0
T37	0	45	0	0
T38	0	82	0	0
T39	0	33	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T79	0	68	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T226	0	50	0	0
T237	0	59	0	0
T269	0	16	0	0
T270	0	15	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	4823	0	0
T30	175865	0	0	0
T35	234057	15	0	0
T36	205202	71	0	0
T37	0	41	0	0
T38	0	66	0	0
T39	0	35	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T79	0	63	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T226	0	43	0	0
T237	0	63	0	0
T269	0	11	0	0
T270	0	10	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	4928	0	0
T30	175865	0	0	0
T35	234057	14	0	0
T36	205202	54	0	0
T37	0	58	0	0
T38	0	61	0	0
T39	0	38	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T79	0	49	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T226	0	28	0	0
T237	0	54	0	0
T269	0	19	0	0
T270	0	29	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	4890	0	0
T30	175865	0	0	0
T35	234057	1	0	0
T36	205202	76	0	0
T37	0	46	0	0
T38	0	53	0	0
T39	0	36	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T79	0	49	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T226	0	45	0	0
T237	0	60	0	0
T269	0	20	0	0
T270	0	31	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	2512	0	0
T9	322046	0	0	0
T10	50294	0	0	0
T26	241675	0	0	0
T27	330836	0	0	0
T28	60717	0	0	0
T35	0	16	0	0
T36	0	19	0	0
T37	0	18	0	0
T38	0	23	0	0
T39	0	3	0	0
T50	257551	8	0	0
T61	156671	0	0	0
T69	193287	0	0	0
T75	189429	0	0	0
T76	101649	0	0	0
T79	0	26	0	0
T219	0	6	0	0
T226	0	7	0	0
T269	0	28	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	2161	0	0
T30	175865	0	0	0
T35	234057	23	0	0
T36	205202	0	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T95	0	21	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T194	0	29	0	0
T214	0	36	0	0
T253	0	35	0	0
T269	0	23	0	0
T270	0	58	0	0
T285	0	13	0	0
T286	0	76	0	0
T287	0	4	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	5947	0	0
T12	414115	4	0	0
T13	247242	0	0	0
T35	234057	13	0	0
T40	229141	2	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T57	0	4	0	0
T66	228834	0	0	0
T70	130717	0	0	0
T77	131213	0	0	0
T94	0	3	0	0
T111	112094	0	0	0
T114	0	3	0	0
T150	0	4	0	0
T165	0	2	0	0
T269	0	17	0	0
T270	0	22	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	1371	0	0
T30	175865	0	0	0
T35	234057	18	0	0
T36	205202	0	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T95	0	19	0	0
T96	0	5	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T194	0	24	0	0
T214	0	14	0	0
T253	0	8	0	0
T269	0	17	0	0
T270	0	19	0	0
T285	0	8	0	0
T286	0	15	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	7618	0	0
T30	175865	0	0	0
T35	234057	72	0	0
T36	205202	0	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T57	0	211	0	0
T66	228834	44	0	0
T67	0	73	0	0
T78	752617	0	0	0
T111	112094	0	0	0
T165	0	76	0	0
T181	86358	0	0	0
T269	0	80	0	0
T270	0	238	0	0
T288	0	53	0	0
T289	0	47	0	0
T290	0	49	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	8333	0	0
T9	322046	0	0	0
T10	50294	0	0	0
T11	111191	0	0	0
T27	330836	0	0	0
T28	60717	75	0	0
T29	62963	0	0	0
T35	0	17	0	0
T57	0	70	0	0
T58	200952	0	0	0
T69	193287	0	0	0
T75	189429	0	0	0
T76	101649	0	0	0
T231	0	68	0	0
T253	0	114	0	0
T269	0	11	0	0
T270	0	154	0	0
T291	0	85	0	0
T292	0	79	0	0
T293	0	92	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	5516	0	0
T9	322046	0	0	0
T10	50294	0	0	0
T11	111191	0	0	0
T27	330836	0	0	0
T28	60717	64	0	0
T29	62963	0	0	0
T35	0	7	0	0
T57	0	98	0	0
T58	200952	0	0	0
T69	193287	0	0	0
T75	189429	0	0	0
T76	101649	0	0	0
T231	0	58	0	0
T253	0	91	0	0
T269	0	16	0	0
T270	0	164	0	0
T291	0	80	0	0
T292	0	74	0	0
T293	0	61	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	5758	0	0
T9	322046	0	0	0
T10	50294	0	0	0
T11	111191	0	0	0
T27	330836	0	0	0
T28	60717	70	0	0
T29	62963	0	0	0
T35	0	11	0	0
T57	0	63	0	0
T58	200952	0	0	0
T69	193287	0	0	0
T75	189429	0	0	0
T76	101649	0	0	0
T231	0	69	0	0
T253	0	58	0	0
T269	0	19	0	0
T270	0	169	0	0
T291	0	64	0	0
T292	0	69	0	0
T293	0	59	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	1728	0	0
T30	175865	0	0	0
T35	234057	29	0	0
T36	205202	0	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T95	0	18	0	0
T96	0	7	0	0
T111	112094	0	0	0
T181	86358	0	0	0
T194	0	39	0	0
T214	0	15	0	0
T253	0	28	0	0
T269	0	12	0	0
T270	0	9	0	0
T285	0	9	0	0
T286	0	28	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	1628	0	0
T30	175865	0	0	0
T35	234057	10	0	0
T36	205202	0	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T82	0	9	0	0
T83	0	3	0	0
T86	0	7	0	0
T96	0	1	0	0
T111	112094	0	0	0
T142	0	11	0	0
T181	86358	0	0	0
T228	0	2	0	0
T253	0	6	0	0
T269	0	12	0	0
T270	0	26	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	1646	0	0
T30	175865	0	0	0
T35	234057	15	0	0
T36	205202	0	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T82	0	16	0	0
T83	0	10	0	0
T86	0	11	0	0
T96	0	5	0	0
T111	112094	0	0	0
T142	0	10	0	0
T181	86358	0	0	0
T228	0	15	0	0
T253	0	27	0	0
T269	0	26	0	0
T270	0	14	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	1627	0	0
T30	175865	0	0	0
T35	234057	18	0	0
T36	205202	0	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T82	0	11	0	0
T83	0	1	0	0
T86	0	12	0	0
T96	0	22	0	0
T111	112094	0	0	0
T142	0	9	0	0
T181	86358	0	0	0
T228	0	9	0	0
T253	0	9	0	0
T269	0	21	0	0
T270	0	23	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1249995120	1651	0	0
T30	175865	0	0	0
T35	234057	19	0	0
T36	205202	0	0	0
T40	229141	0	0	0
T44	196347	0	0	0
T51	225213	0	0	0
T66	228834	0	0	0
T78	752617	0	0	0
T82	0	3	0	0
T83	0	2	0	0
T86	0	3	0	0
T96	0	11	0	0
T111	112094	0	0	0
T142	0	2	0	0
T181	86358	0	0	0
T228	0	1	0	0
T253	0	16	0	0
T269	0	17	0	0
T270	0	23	0	0