Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 100.00 96.08 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 99.02 100.00 96.08 100.00 100.00


Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 100.00 96.08 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.60 99.35 96.43 100.00 97.44 98.78 99.61


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
sysrst_ctrl_csr_assert 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_prim_flop_2sync_input 100.00 100.00 100.00
u_reg 99.07 99.38 97.02 100.00 98.94 100.00
u_sysrst_ctrl_autoblock 98.89 100.00 94.44 100.00 100.00 100.00
u_sysrst_ctrl_combo 99.12 100.00 97.61 100.00 98.00 100.00
u_sysrst_ctrl_intr 96.25 100.00 85.00 100.00 100.00
u_sysrst_ctrl_keyintr 95.66 98.30 89.12 95.24 97.50 98.16
u_sysrst_ctrl_pin 100.00 100.00 100.00 100.00
u_sysrst_ctrl_ulp 98.98 100.00 94.92 100.00 100.00 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sysrst_ctrl
Line No.TotalCoveredPercent
TOTAL1717100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN30411100.00
CONT_ASSIGN30511100.00
CONT_ASSIGN30611100.00
CONT_ASSIGN30711100.00
CONT_ASSIGN30811100.00
CONT_ASSIGN31011100.00
CONT_ASSIGN31111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1
107 1 1
108 1 1
109 1 1
110 1 1
111 1 1
113 1 1
114 1 1
303 1 1
304 1 1
305 1 1
306 1 1
307 1 1
308 1 1
310 1 1
311 1 1

Cond Coverage for Module : sysrst_ctrl
TotalCoveredPercent
Conditions514996.08
Logical514996.08
Non-Logical00
Event00

 LINE       68
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01CoveredT69,T75,T139
10CoveredT5,T6,T7
11CoveredT69,T75,T139 

 LINE       106
 EXPRESSION (reg2hw.key_invert_ctl.pwrb_in.q ^ cio_pwrb_in_i)
             ---------------1---------------   ------2------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT5,T7,T1
10CoveredT15,T26,T27
11CoveredT15,T26,T27 

 LINE       107
 EXPRESSION (reg2hw.key_invert_ctl.key0_in.q ^ cio_key0_in_i)
             ---------------1---------------   ------2------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT6,T7,T2
10CoveredT15,T26,T27
11CoveredT15,T26,T27 

 LINE       108
 EXPRESSION (reg2hw.key_invert_ctl.key1_in.q ^ cio_key1_in_i)
             ---------------1---------------   ------2------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT6,T7,T2
10CoveredT15,T26,T27
11CoveredT15,T26,T27 

 LINE       109
 EXPRESSION (reg2hw.key_invert_ctl.key2_in.q ^ cio_key2_in_i)
             ---------------1---------------   ------2------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT6,T7,T2
10CoveredT15,T26,T27
11CoveredT15,T26,T27 

 LINE       110
 EXPRESSION (reg2hw.key_invert_ctl.ac_present.q ^ cio_ac_present_i)
             -----------------1----------------   --------2-------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT7,T1,T2
10CoveredT15,T26,T27
11CoveredT15,T26,T27 

 LINE       111
 EXPRESSION (reg2hw.key_invert_ctl.lid_open.q ^ cio_lid_open_i)
             ----------------1---------------   -------2------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT7,T1,T3
10CoveredT15,T26,T27
11CoveredT15,T26,T27 

 LINE       303
 EXPRESSION (reg2hw.key_invert_ctl.pwrb_out.q ^ pwrb_out_int)
             ----------------1---------------   ------2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT5,T7,T1
10CoveredT15,T26,T27
11CoveredT15,T26,T27 

 LINE       304
 EXPRESSION (reg2hw.key_invert_ctl.key0_out.q ^ key0_out_int)
             ----------------1---------------   ------2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT6,T7,T2
10CoveredT15,T26,T27
11CoveredT15,T26,T27 

 LINE       305
 EXPRESSION (reg2hw.key_invert_ctl.key1_out.q ^ key1_out_int)
             ----------------1---------------   ------2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT6,T7,T2
10CoveredT15,T26,T27
11CoveredT15,T26,T27 

 LINE       306
 EXPRESSION (reg2hw.key_invert_ctl.key2_out.q ^ key2_out_int)
             ----------------1---------------   ------2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT6,T7,T2
10CoveredT15,T26,T27
11CoveredT15,T26,T27 

 LINE       307
 EXPRESSION (reg2hw.key_invert_ctl.bat_disable.q ^ aon_bat_disable_out_int)
             -----------------1-----------------   -----------2-----------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT2,T4,T14
10CoveredT15,T26,T27
11Not Covered 

 LINE       308
 EXPRESSION (reg2hw.key_invert_ctl.z3_wakeup.q ^ aon_z3_wakeup_out_int)
             ----------------1----------------   ----------2----------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T3,T9
10CoveredT15,T26,T27
11Not Covered
Toggle Coverage for Module : sysrst_ctrl
TotalCoveredPercent
Totals 47 47 100.00
Total Bits 374 374 100.00
Total Bits 0->1 187 187 100.00
Total Bits 1->0 187 187 100.00

Ports 47 47 100.00
Port Bits 374 374 100.00
Port Bits 0->1 187 187 100.00
Port Bits 1->0 187 187 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
clk_aon_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
rst_ni Yes Yes T2,T4,T14 Yes T5,T6,T7 INPUT
rst_aon_ni Yes Yes T2,T4,T14 Yes T5,T6,T7 INPUT
tl_i.d_ready Yes Yes T6,T4,T17 Yes T5,T6,T7 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T5,T7,T2 Yes T5,T7,T2 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_mask[3:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_address[31:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_source[7:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_size[1:0] Yes Yes T5,T6,T7 Yes T5,T7,T1 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_valid Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_o.a_ready Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_error Yes Yes T35,T63,T43 Yes T35,T63,T43 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T5,T7,T1 Yes T5,T7,T1 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T5,*T6,*T7 Yes T5,T6,T7 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T6,T7,T2 Yes T6,T7,T2 OUTPUT
tl_o.d_size[1:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T5,*T1,*T2 Yes T5,T6,T7 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
alert_rx_i[0].ack_n Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
alert_rx_i[0].ack_p Yes Yes T69,T75,T139 Yes T69,T75,T139 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
alert_tx_o[0].alert_p Yes Yes T69,T75,T139 Yes T69,T75,T139 OUTPUT
wkup_req_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rst_req_o Yes Yes T2,T4,T14 Yes T2,T4,T14 OUTPUT
intr_event_detected_o Yes Yes T1,T4,T9 Yes T1,T4,T9 OUTPUT
cio_ac_present_i Yes Yes T7,T1,T2 Yes T7,T1,T2 INPUT
cio_ec_rst_l_i Yes Yes T7,T4,T15 Yes T7,T4,T15 INPUT
cio_key0_in_i Yes Yes T6,T7,T2 Yes T6,T7,T2 INPUT
cio_key1_in_i Yes Yes T6,T7,T2 Yes T6,T7,T2 INPUT
cio_key2_in_i Yes Yes T6,T7,T2 Yes T6,T7,T2 INPUT
cio_pwrb_in_i Yes Yes T5,T7,T1 Yes T5,T7,T1 INPUT
cio_lid_open_i Yes Yes T7,T1,T3 Yes T7,T1,T3 INPUT
cio_flash_wp_l_i Yes Yes T7,T15,T17 Yes T7,T15,T17 INPUT
cio_bat_disable_o Yes Yes T2,T4,T14 Yes T2,T4,T14 OUTPUT
cio_flash_wp_l_o Yes Yes T28,T9,T29 Yes T28,T9,T29 OUTPUT
cio_ec_rst_l_o Yes Yes T2,T4,T14 Yes T6,T2,T4 OUTPUT
cio_key0_out_o Yes Yes T6,T7,T2 Yes T6,T7,T2 OUTPUT
cio_key1_out_o Yes Yes T6,T7,T2 Yes T6,T7,T2 OUTPUT
cio_key2_out_o Yes Yes T6,T7,T2 Yes T6,T7,T2 OUTPUT
cio_pwrb_out_o Yes Yes T5,T7,T1 Yes T5,T7,T1 OUTPUT
cio_z3_wakeup_o Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
cio_bat_disable_en_o Unreachable Unreachable Unreachable OUTPUT
cio_flash_wp_l_en_o Unreachable Unreachable Unreachable OUTPUT
cio_ec_rst_l_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key0_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key1_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key2_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_pwrb_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_z3_wakeup_en_o Unreachable Unreachable Unreachable OUTPUT

*Tests covering at least one bit in the range
Assert Coverage for Module : sysrst_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 23 23 100.00 23 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 23 23 100.00 23 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertKnown_A 1177064824 1175365895 0 0
BatOEnIsOne_A 1177064824 1175365895 0 0
BatOKnown_A 1177064824 1175365895 0 0
ECRSTOEnIsOne_A 1177064824 1175365895 0 0
ECRSTOKnown_A 1177064824 1175365895 0 0
FlashWpOEnIsOne_A 1177064824 1175365895 0 0
FlashWpOKnown_A 1177064824 1175365895 0 0
FpvSecCmRegWeOnehotCheck_A 1177064824 70 0 0
IntrEventOKnown_A 1177064824 1175365895 0 0
Key0OEnIsOne_A 1177064824 1175365895 0 0
Key0OKnown_A 1177064824 1175365895 0 0
Key1OEnIsOne_A 1177064824 1175365895 0 0
Key1OKnown_A 1177064824 1175365895 0 0
Key2OEnIsOne_A 1177064824 1175365895 0 0
Key2OKnown_A 1177064824 1175365895 0 0
OTRstOKnown_A 1177064824 1175365895 0 0
OTWkOKnown_A 1177064824 1175365895 0 0
PwrbOEnIsOne_A 1177064824 1175365895 0 0
PwrbOKnown_A 1177064824 1175365895 0 0
TlOAReadyKnown_A 1177064824 1175365895 0 0
TlODValidKnown_A 1177064824 1175365895 0 0
Z3WakeupOEnIsOne_A 1177064824 1175365895 0 0
Z3WwakupOKnown_A 1177064824 1175365895 0 0


AlertKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

BatOEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

BatOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

ECRSTOEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

ECRSTOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

FlashWpOEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

FlashWpOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 70 0 0
T82 223490 0 0 0
T112 107900 10 0 0
T113 238113 0 0 0
T114 67076 0 0 0
T115 202770 0 0 0
T116 389990 0 0 0
T117 199097 0 0 0
T118 52432 0 0 0
T119 51147 0 0 0
T258 0 20 0 0
T259 0 10 0 0
T280 0 10 0 0
T281 0 20 0 0
T282 118630 0 0 0

IntrEventOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

Key0OEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

Key0OKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

Key1OEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

Key1OKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

Key2OEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

Key2OKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

OTRstOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

OTWkOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

PwrbOEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

PwrbOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

TlOAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

TlODValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

Z3WakeupOEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

Z3WwakupOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1177064824 1175365895 0 0
T1 52767 52696 0 0
T2 887365 885973 0 0
T3 53463 53385 0 0
T4 611177 609780 0 0
T5 350873 350774 0 0
T6 52316 52264 0 0
T7 52510 52451 0 0
T14 397958 397622 0 0
T15 128589 128495 0 0
T16 238278 238270 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%