Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T28,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T27,T28,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T28,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T28,T44
1	0	Covered	T4,T1,T5
1	1	Covered	T27,T28,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T44
0	1	Covered	T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T44
0	1	Covered	T27,T28,T44
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T28,T44
1	-	Covered	T27,T28,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T28,T44
DetectSt	168	Covered	T27,T28,T44
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T27,T28,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T28,T44
DebounceSt->IdleSt	163	Covered	T45,T37,T96
DetectSt->IdleSt	186	Covered	T87
DetectSt->StableSt	191	Covered	T27,T28,T44
IdleSt->DebounceSt	148	Covered	T27,T28,T44
StableSt->IdleSt	206	Covered	T27,T28,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T27,T28,T44
0	1	Covered	T27,T28,T44
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T44
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T28,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T39
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T28,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T37,T96
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T28,T44
DetectSt	-	-	-	-	1	-	-	Covered	T87
DetectSt	-	-	-	-	0	1	-	Covered	T27,T28,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T27,T28,T44
StableSt	-	-	-	-	-	-	0	Covered	T27,T28,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	275	0	0
CntIncr_A	6649655	156924	0	0
CntNoWrap_A	6649655	5989160	0	0
DetectStDropOut_A	6649655	1	0	0
DetectedOut_A	6649655	850	0	0
DetectedPulseOut_A	6649655	121	0	0
DisabledIdleSt_A	6649655	5826049	0	0
DisabledNoDetection_A	6649655	5828327	0	0
EnterDebounceSt_A	6649655	155	0	0
EnterDetectSt_A	6649655	122	0	0
EnterStableSt_A	6649655	121	0	0
PulseIsPulse_A	6649655	121	0	0
StayInStableSt	6649655	729	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6649655	6688	0	0
gen_low_level_sva.LowLevelEvent_A	6649655	5991763	0	0
gen_not_sticky_sva.StableStDropOut_A	6649655	120	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	275	0	0
T7	23533	0	0	0
T8	32789	0	0	0
T9	1004	0	0	0
T10	504	0	0	0
T24	0	2	0	0
T25	494	0	0	0
T27	667	2	0	0
T28	594	2	0	0
T29	727	0	0	0
T35	0	4	0	0
T37	0	10	0	0
T44	0	4	0	0
T45	0	3	0	0
T47	0	2	0	0
T48	0	4	0	0
T50	424	0	0	0
T51	833	0	0	0
T96	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	156924	0	0
T7	23533	0	0	0
T8	32789	0	0	0
T9	1004	0	0	0
T10	504	0	0	0
T24	0	36	0	0
T25	494	0	0	0
T27	667	44	0	0
T28	594	13	0	0
T29	727	0	0	0
T35	0	52	0	0
T37	0	331	0	0
T44	0	151	0	0
T45	0	1456	0	0
T47	0	18	0	0
T48	0	152	0	0
T50	424	0	0	0
T51	833	0	0	0
T96	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5989160	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	1	0	0
T87	56084	1	0	0
T89	28754	0	0	0
T90	10794	0	0	0
T95	1546	0	0	0
T116	1068	0	0	0
T117	413	0	0	0
T118	423	0	0	0
T119	421	0	0	0
T120	739	0	0	0
T121	29684	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	850	0	0
T7	23533	0	0	0
T8	32789	0	0	0
T9	1004	0	0	0
T10	504	0	0	0
T24	0	9	0	0
T25	494	0	0	0
T27	667	2	0	0
T28	594	4	0	0
T29	727	0	0	0
T35	0	16	0	0
T37	0	27	0	0
T44	0	18	0	0
T45	0	6	0	0
T47	0	11	0	0
T48	0	10	0	0
T50	424	0	0	0
T51	833	0	0	0
T96	0	11	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	121	0	0
T7	23533	0	0	0
T8	32789	0	0	0
T9	1004	0	0	0
T10	504	0	0	0
T24	0	1	0	0
T25	494	0	0	0
T27	667	1	0	0
T28	594	1	0	0
T29	727	0	0	0
T35	0	2	0	0
T37	0	4	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	424	0	0	0
T51	833	0	0	0
T96	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5826049	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5828327	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	155	0	0
T7	23533	0	0	0
T8	32789	0	0	0
T9	1004	0	0	0
T10	504	0	0	0
T24	0	1	0	0
T25	494	0	0	0
T27	667	1	0	0
T28	594	1	0	0
T29	727	0	0	0
T35	0	2	0	0
T37	0	6	0	0
T44	0	2	0	0
T45	0	2	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	424	0	0	0
T51	833	0	0	0
T96	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	122	0	0
T7	23533	0	0	0
T8	32789	0	0	0
T9	1004	0	0	0
T10	504	0	0	0
T24	0	1	0	0
T25	494	0	0	0
T27	667	1	0	0
T28	594	1	0	0
T29	727	0	0	0
T35	0	2	0	0
T37	0	4	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	424	0	0	0
T51	833	0	0	0
T96	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	121	0	0
T7	23533	0	0	0
T8	32789	0	0	0
T9	1004	0	0	0
T10	504	0	0	0
T24	0	1	0	0
T25	494	0	0	0
T27	667	1	0	0
T28	594	1	0	0
T29	727	0	0	0
T35	0	2	0	0
T37	0	4	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	424	0	0	0
T51	833	0	0	0
T96	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	121	0	0
T7	23533	0	0	0
T8	32789	0	0	0
T9	1004	0	0	0
T10	504	0	0	0
T24	0	1	0	0
T25	494	0	0	0
T27	667	1	0	0
T28	594	1	0	0
T29	727	0	0	0
T35	0	2	0	0
T37	0	4	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	424	0	0	0
T51	833	0	0	0
T96	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	729	0	0
T7	23533	0	0	0
T8	32789	0	0	0
T9	1004	0	0	0
T10	504	0	0	0
T24	0	8	0	0
T25	494	0	0	0
T27	667	1	0	0
T28	594	3	0	0
T29	727	0	0	0
T35	0	14	0	0
T37	0	23	0	0
T44	0	16	0	0
T45	0	5	0	0
T47	0	10	0	0
T48	0	8	0	0
T50	424	0	0	0
T51	833	0	0	0
T96	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	6688	0	0
T1	3384	17	0	0
T2	33900	14	0	0
T3	7686	25	0	0
T4	503	6	0	0
T5	502	5	0	0
T13	422	1	0	0
T14	426	3	0	0
T15	427	1	0	0
T16	504	5	0	0
T17	449	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	120	0	0
T7	23533	0	0	0
T8	32789	0	0	0
T9	1004	0	0	0
T10	504	0	0	0
T24	0	1	0	0
T25	494	0	0	0
T27	667	1	0	0
T28	594	1	0	0
T29	727	0	0	0
T35	0	2	0	0
T37	0	4	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	424	0	0	0
T51	833	0	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T22,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T4,T1,T5
1	1	Covered	T22,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T24,T54
0	1	Covered	T22,T80,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T24,T54
0	1	Unreachable
1	0	Covered	T23,T24,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T23,T24
DetectSt	168	Covered	T22,T23,T24
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T23,T24,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T23,T24
DebounceSt->IdleSt	163	Covered	T22,T35,T39
DetectSt->IdleSt	186	Covered	T22,T80,T95
DetectSt->StableSt	191	Covered	T23,T24,T54
IdleSt->DebounceSt	148	Covered	T22,T23,T24
StableSt->IdleSt	206	Covered	T23,T24,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T23,T24
0	1	Covered	T22,T23,T24
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T23,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T35,T91
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T22,T80,T95
DetectSt	-	-	-	-	0	1	-	Covered	T23,T24,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T24,T54
StableSt	-	-	-	-	-	-	0	Covered	T23,T24,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	178	0	0
CntIncr_A	6649655	104388	0	0
CntNoWrap_A	6649655	5989257	0	0
DetectStDropOut_A	6649655	18	0	0
DetectedOut_A	6649655	353574	0	0
DetectedPulseOut_A	6649655	51	0	0
DisabledIdleSt_A	6649655	4696025	0	0
DisabledNoDetection_A	6649655	4698352	0	0
EnterDebounceSt_A	6649655	111	0	0
EnterDetectSt_A	6649655	69	0	0
EnterStableSt_A	6649655	51	0	0
PulseIsPulse_A	6649655	51	0	0
StayInStableSt	6649655	353523	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6649655	6688	0	0
gen_low_level_sva.LowLevelEvent_A	6649655	5991763	0	0
gen_sticky_sva.StableStDropOut_A	6649655	677926	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	178	0	0
T22	660	3	0	0
T23	336909	2	0	0
T24	0	2	0	0
T35	0	5	0	0
T36	809	0	0	0
T39	0	1	0	0
T47	1638	0	0	0
T54	0	2	0	0
T56	0	2	0	0
T60	502	0	0	0
T61	497	0	0	0
T62	422	0	0	0
T66	492	0	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	4	0	0
T81	403	0	0	0
T82	495	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	104388	0	0
T22	660	174	0	0
T23	336909	23599	0	0
T24	0	37	0	0
T35	0	115	0	0
T36	809	0	0	0
T39	0	77	0	0
T47	1638	0	0	0
T54	0	41	0	0
T56	0	31	0	0
T60	502	0	0	0
T61	497	0	0	0
T62	422	0	0	0
T66	492	0	0	0
T78	0	12	0	0
T79	0	41	0	0
T80	0	150	0	0
T81	403	0	0	0
T82	495	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5989257	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	18	0	0
T22	660	1	0	0
T23	336909	0	0	0
T36	809	0	0	0
T47	1638	0	0	0
T60	502	0	0	0
T61	497	0	0	0
T62	422	0	0	0
T66	492	0	0	0
T80	0	2	0	0
T81	403	0	0	0
T82	495	0	0	0
T95	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	5	0	0
T139	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	353574	0	0
T23	336909	163240	0	0
T24	0	5	0	0
T41	15335	0	0	0
T48	52940	0	0	0
T54	0	111	0	0
T56	0	97	0	0
T74	504	0	0	0
T78	0	54	0	0
T79	0	295	0	0
T91	0	421	0	0
T122	0	494	0	0
T123	0	536	0	0
T125	0	36	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T132	524	0	0	0
T133	504	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	51	0	0
T23	336909	1	0	0
T24	0	1	0	0
T41	15335	0	0	0
T48	52940	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T74	504	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T91	0	2	0	0
T122	0	1	0	0
T123	0	2	0	0
T125	0	2	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T132	524	0	0	0
T133	504	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	4696025	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	4698352	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	111	0	0
T22	660	2	0	0
T23	336909	1	0	0
T24	0	1	0	0
T35	0	5	0	0
T36	809	0	0	0
T39	0	2	0	0
T47	1638	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T60	502	0	0	0
T61	497	0	0	0
T62	422	0	0	0
T66	492	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	403	0	0	0
T82	495	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	69	0	0
T22	660	1	0	0
T23	336909	1	0	0
T24	0	1	0	0
T36	809	0	0	0
T47	1638	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T60	502	0	0	0
T61	497	0	0	0
T62	422	0	0	0
T66	492	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	403	0	0	0
T82	495	0	0	0
T91	0	2	0	0
T122	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	51	0	0
T23	336909	1	0	0
T24	0	1	0	0
T41	15335	0	0	0
T48	52940	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T74	504	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T91	0	2	0	0
T122	0	1	0	0
T123	0	2	0	0
T125	0	2	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T132	524	0	0	0
T133	504	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	51	0	0
T23	336909	1	0	0
T24	0	1	0	0
T41	15335	0	0	0
T48	52940	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T74	504	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T91	0	2	0	0
T122	0	1	0	0
T123	0	2	0	0
T125	0	2	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T132	524	0	0	0
T133	504	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	353523	0	0
T23	336909	163239	0	0
T24	0	4	0	0
T41	15335	0	0	0
T48	52940	0	0	0
T54	0	110	0	0
T56	0	96	0	0
T74	504	0	0	0
T78	0	53	0	0
T79	0	294	0	0
T91	0	419	0	0
T122	0	493	0	0
T123	0	534	0	0
T125	0	34	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T132	524	0	0	0
T133	504	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	6688	0	0
T1	3384	17	0	0
T2	33900	14	0	0
T3	7686	25	0	0
T4	503	6	0	0
T5	502	5	0	0
T13	422	1	0	0
T14	426	3	0	0
T15	427	1	0	0
T16	504	5	0	0
T17	449	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	677926	0	0
T23	336909	87	0	0
T24	0	36	0	0
T41	15335	0	0	0
T48	52940	0	0	0
T54	0	67763	0	0
T56	0	286	0	0
T74	504	0	0	0
T78	0	369	0	0
T79	0	277	0	0
T91	0	117	0	0
T122	0	600	0	0
T123	0	272	0	0
T125	0	170	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T132	524	0	0	0
T133	504	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T22,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T4,T1,T5
1	1	Covered	T22,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T54,T56
0	1	Covered	T22,T23,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T54,T56
0	1	Unreachable
1	0	Covered	T35,T54,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T23,T24
DetectSt	168	Covered	T22,T23,T35
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T35,T54,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T23,T35
DebounceSt->IdleSt	163	Covered	T22,T23,T24
DetectSt->IdleSt	186	Covered	T22,T23,T94
DetectSt->StableSt	191	Covered	T35,T54,T56
IdleSt->DebounceSt	148	Covered	T22,T23,T24
StableSt->IdleSt	206	Covered	T35,T54,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T23,T24
0	1	Covered	T22,T23,T24
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T35
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T23,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T23,T24
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T22,T23,T94
DetectSt	-	-	-	-	0	1	-	Covered	T35,T54,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T54,T56
StableSt	-	-	-	-	-	-	0	Covered	T35,T54,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	179	0	0
CntIncr_A	6649655	113763	0	0
CntNoWrap_A	6649655	5989256	0	0
DetectStDropOut_A	6649655	12	0	0
DetectedOut_A	6649655	8606	0	0
DetectedPulseOut_A	6649655	48	0	0
DisabledIdleSt_A	6649655	4696025	0	0
DisabledNoDetection_A	6649655	4698352	0	0
EnterDebounceSt_A	6649655	121	0	0
EnterDetectSt_A	6649655	60	0	0
EnterStableSt_A	6649655	48	0	0
PulseIsPulse_A	6649655	48	0	0
StayInStableSt	6649655	8558	0	0
gen_high_level_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_sticky_sva.StableStDropOut_A	6649655	678699	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	179	0	0
T22	660	3	0	0
T23	336909	8	0	0
T24	0	1	0	0
T35	0	2	0	0
T36	809	0	0	0
T39	0	1	0	0
T47	1638	0	0	0
T54	0	2	0	0
T56	0	2	0	0
T60	502	0	0	0
T61	497	0	0	0
T62	422	0	0	0
T66	492	0	0	0
T78	0	2	0	0
T79	0	5	0	0
T80	0	2	0	0
T81	403	0	0	0
T82	495	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	113763	0	0
T22	660	58	0	0
T23	336909	70	0	0
T24	0	33	0	0
T35	0	53	0	0
T36	809	0	0	0
T39	0	78	0	0
T47	1638	0	0	0
T54	0	49	0	0
T56	0	83	0	0
T60	502	0	0	0
T61	497	0	0	0
T62	422	0	0	0
T66	492	0	0	0
T78	0	51	0	0
T79	0	155	0	0
T80	0	102	0	0
T81	403	0	0	0
T82	495	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5989256	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	12	0	0
T22	660	1	0	0
T23	336909	3	0	0
T36	809	0	0	0
T47	1638	0	0	0
T60	502	0	0	0
T61	497	0	0	0
T62	422	0	0	0
T66	492	0	0	0
T81	403	0	0	0
T82	495	0	0	0
T94	0	2	0	0
T108	0	1	0	0
T135	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0
T142	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	8606	0	0
T35	119316	313	0	0
T53	6572	0	0	0
T54	0	230	0	0
T56	0	274	0	0
T76	4315	0	0	0
T77	20631	0	0	0
T78	0	277	0	0
T91	0	516	0	0
T111	653	0	0	0
T112	702	0	0	0
T113	733	0	0	0
T114	734	0	0	0
T115	426	0	0	0
T123	0	506	0	0
T124	0	410	0	0
T125	0	15	0	0
T126	0	176	0	0
T127	0	192	0	0
T134	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	48	0	0
T35	119316	1	0	0
T53	6572	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T76	4315	0	0	0
T77	20631	0	0	0
T78	0	1	0	0
T91	0	2	0	0
T111	653	0	0	0
T112	702	0	0	0
T113	733	0	0	0
T114	734	0	0	0
T115	426	0	0	0
T123	0	2	0	0
T124	0	1	0	0
T125	0	2	0	0
T126	0	2	0	0
T127	0	1	0	0
T134	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	4696025	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	4698352	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	121	0	0
T22	660	2	0	0
T23	336909	5	0	0
T24	0	1	0	0
T35	0	1	0	0
T36	809	0	0	0
T39	0	2	0	0
T47	1638	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T60	502	0	0	0
T61	497	0	0	0
T62	422	0	0	0
T66	492	0	0	0
T78	0	1	0	0
T79	0	5	0	0
T80	0	2	0	0
T81	403	0	0	0
T82	495	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	60	0	0
T22	660	1	0	0
T23	336909	3	0	0
T35	0	1	0	0
T36	809	0	0	0
T47	1638	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T60	502	0	0	0
T61	497	0	0	0
T62	422	0	0	0
T66	492	0	0	0
T78	0	1	0	0
T81	403	0	0	0
T82	495	0	0	0
T91	0	2	0	0
T123	0	2	0	0
T124	0	1	0	0
T125	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	48	0	0
T35	119316	1	0	0
T53	6572	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T76	4315	0	0	0
T77	20631	0	0	0
T78	0	1	0	0
T91	0	2	0	0
T111	653	0	0	0
T112	702	0	0	0
T113	733	0	0	0
T114	734	0	0	0
T115	426	0	0	0
T123	0	2	0	0
T124	0	1	0	0
T125	0	2	0	0
T126	0	2	0	0
T127	0	1	0	0
T134	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	48	0	0
T35	119316	1	0	0
T53	6572	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T76	4315	0	0	0
T77	20631	0	0	0
T78	0	1	0	0
T91	0	2	0	0
T111	653	0	0	0
T112	702	0	0	0
T113	733	0	0	0
T114	734	0	0	0
T115	426	0	0	0
T123	0	2	0	0
T124	0	1	0	0
T125	0	2	0	0
T126	0	2	0	0
T127	0	1	0	0
T134	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	8558	0	0
T35	119316	312	0	0
T53	6572	0	0	0
T54	0	229	0	0
T56	0	273	0	0
T76	4315	0	0	0
T77	20631	0	0	0
T78	0	276	0	0
T91	0	514	0	0
T111	653	0	0	0
T112	702	0	0	0
T113	733	0	0	0
T114	734	0	0	0
T115	426	0	0	0
T123	0	504	0	0
T124	0	409	0	0
T125	0	13	0	0
T126	0	174	0	0
T127	0	191	0	0
T134	402	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	678699	0	0
T35	119316	101632	0	0
T53	6572	0	0	0
T54	0	67641	0	0
T56	0	62	0	0
T76	4315	0	0	0
T77	20631	0	0	0
T78	0	109	0	0
T91	0	937	0	0
T111	653	0	0	0
T112	702	0	0	0
T113	733	0	0	0
T114	734	0	0	0
T115	426	0	0	0
T123	0	300	0	0
T124	0	108	0	0
T125	0	188	0	0
T126	0	1246	0	0
T127	0	91	0	0
T134	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T22,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T23,T24,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T4,T1,T5
1	1	Covered	T22,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T24,T54
0	1	Covered	T23,T35,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T24,T54
0	1	Unreachable
1	0	Covered	T23,T24,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T23,T24
DetectSt	168	Covered	T23,T24,T35
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T23,T24,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T23,T24,T35
DebounceSt->IdleSt	163	Covered	T22,T35,T39
DetectSt->IdleSt	186	Covered	T23,T35,T91
DetectSt->StableSt	191	Covered	T23,T24,T54
IdleSt->DebounceSt	148	Covered	T22,T23,T24
StableSt->IdleSt	206	Covered	T23,T24,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T23,T24
0	1	Covered	T22,T23,T24
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T23,T24,T35
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T23,T24,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T35,T125
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T23,T35,T91
DetectSt	-	-	-	-	0	1	-	Covered	T23,T24,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T24,T54
StableSt	-	-	-	-	-	-	0	Covered	T23,T24,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	183	0	0
CntIncr_A	6649655	450843	0	0
CntNoWrap_A	6649655	5989252	0	0
DetectStDropOut_A	6649655	13	0	0
DetectedOut_A	6649655	280007	0	0
DetectedPulseOut_A	6649655	48	0	0
DisabledIdleSt_A	6649655	4696025	0	0
DisabledNoDetection_A	6649655	4698352	0	0
EnterDebounceSt_A	6649655	124	0	0
EnterDetectSt_A	6649655	61	0	0
EnterStableSt_A	6649655	48	0	0
PulseIsPulse_A	6649655	48	0	0
StayInStableSt	6649655	279959	0	0
gen_high_event_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_high_level_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_sticky_sva.StableStDropOut_A	6649655	333831	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	183	0	0
T22	660	2	0	0
T23	336909	8	0	0
T24	0	2	0	0
T35	0	8	0	0
T36	809	0	0	0
T39	0	1	0	0
T47	1638	0	0	0
T54	0	2	0	0
T56	0	2	0	0
T60	502	0	0	0
T61	497	0	0	0
T62	422	0	0	0
T66	492	0	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	2	0	0
T81	403	0	0	0
T82	495	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	450843	0	0
T22	660	84	0	0
T23	336909	68	0	0
T24	0	70	0	0
T35	0	101915	0	0
T36	809	0	0	0
T39	0	81	0	0
T47	1638	0	0	0
T54	0	14205	0	0
T56	0	46	0	0
T60	502	0	0	0
T61	497	0	0	0
T62	422	0	0	0
T66	492	0	0	0
T78	0	21	0	0
T79	0	86	0	0
T80	0	76	0	0
T81	403	0	0	0
T82	495	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5989252	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	13	0	0
T23	336909	3	0	0
T35	0	3	0	0
T41	15335	0	0	0
T48	52940	0	0	0
T74	504	0	0	0
T91	0	2	0	0
T124	0	1	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T132	524	0	0	0
T133	504	0	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	280007	0	0
T23	336909	20	0	0
T24	0	1	0	0
T41	15335	0	0	0
T48	52940	0	0	0
T54	0	53675	0	0
T56	0	131	0	0
T74	504	0	0	0
T78	0	134	0	0
T79	0	347	0	0
T80	0	224	0	0
T91	0	1068	0	0
T93	0	377	0	0
T122	0	793	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T132	524	0	0	0
T133	504	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	48	0	0
T23	336909	1	0	0
T24	0	1	0	0
T41	15335	0	0	0
T48	52940	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T74	504	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T91	0	3	0	0
T93	0	1	0	0
T122	0	1	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T132	524	0	0	0
T133	504	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	4696025	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	4698352	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	124	0	0
T22	660	2	0	0
T23	336909	4	0	0
T24	0	1	0	0
T35	0	5	0	0
T36	809	0	0	0
T39	0	2	0	0
T47	1638	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T60	502	0	0	0
T61	497	0	0	0
T62	422	0	0	0
T66	492	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	403	0	0	0
T82	495	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	61	0	0
T23	336909	4	0	0
T24	0	1	0	0
T35	0	3	0	0
T41	15335	0	0	0
T48	52940	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T74	504	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T91	0	5	0	0
T93	0	1	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T132	524	0	0	0
T133	504	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	48	0	0
T23	336909	1	0	0
T24	0	1	0	0
T41	15335	0	0	0
T48	52940	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T74	504	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T91	0	3	0	0
T93	0	1	0	0
T122	0	1	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T132	524	0	0	0
T133	504	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	48	0	0
T23	336909	1	0	0
T24	0	1	0	0
T41	15335	0	0	0
T48	52940	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T74	504	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T91	0	3	0	0
T93	0	1	0	0
T122	0	1	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T132	524	0	0	0
T133	504	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	279959	0	0
T23	336909	19	0	0
T41	15335	0	0	0
T48	52940	0	0	0
T54	0	53674	0	0
T56	0	130	0	0
T74	504	0	0	0
T78	0	133	0	0
T79	0	346	0	0
T80	0	223	0	0
T91	0	1065	0	0
T93	0	376	0	0
T122	0	792	0	0
T123	0	676	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T132	524	0	0	0
T133	504	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	333831	0	0
T23	336909	74747	0	0
T24	0	26	0	0
T41	15335	0	0	0
T48	52940	0	0	0
T54	0	44	0	0
T56	0	244	0	0
T74	504	0	0	0
T78	0	294	0	0
T79	0	197	0	0
T80	0	128	0	0
T91	0	263	0	0
T93	0	110	0	0
T122	0	322	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T132	524	0	0	0
T133	504	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T36,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T36,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T36,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T36
1	0	Covered	T4,T1,T5
1	1	Covered	T1,T36,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T36,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T36,T38
0	1	Covered	T36,T38,T56
1	0	Covered	T39

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T36,T38
1	-	Covered	T36,T38,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T36,T38
DetectSt	168	Covered	T1,T36,T38
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T36,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T36,T38
DebounceSt->IdleSt	163	Covered	T146,T85,T147
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T36,T38
IdleSt->DebounceSt	148	Covered	T1,T36,T38
StableSt->IdleSt	206	Covered	T1,T36,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T36,T38
0	1	Covered	T1,T36,T38
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T36,T38
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T36,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T36,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T146,T147
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T36,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T36,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T38,T56
StableSt	-	-	-	-	-	-	0	Covered	T1,T36,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	83	0	0
CntIncr_A	6649655	2304	0	0
CntNoWrap_A	6649655	5989352	0	0
DetectStDropOut_A	6649655	0	0	0
DetectedOut_A	6649655	2942	0	0
DetectedPulseOut_A	6649655	40	0	0
DisabledIdleSt_A	6649655	5895295	0	0
DisabledNoDetection_A	6649655	5897565	0	0
EnterDebounceSt_A	6649655	43	0	0
EnterDetectSt_A	6649655	40	0	0
EnterStableSt_A	6649655	40	0	0
PulseIsPulse_A	6649655	40	0	0
StayInStableSt	6649655	2878	0	0
gen_high_level_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_not_sticky_sva.StableStDropOut_A	6649655	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	83	0	0
T1	3384	2	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T56	0	2	0	0
T112	0	2	0	0
T146	0	1	0	0
T148	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	2304	0	0
T1	3384	67	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	54	0	0
T36	0	69	0	0
T38	0	22	0	0
T39	0	30	0	0
T40	0	71	0	0
T56	0	15	0	0
T112	0	52	0	0
T146	0	33	0	0
T148	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5989352	0	0
T1	3384	977	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	2942	0	0
T1	3384	341	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	50	0	0
T36	0	41	0	0
T38	0	66	0	0
T39	0	6	0	0
T40	0	156	0	0
T56	0	121	0	0
T112	0	77	0	0
T148	0	44	0	0
T149	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	40	0	0
T1	3384	1	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T56	0	1	0	0
T112	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5895295	0	0
T1	3384	386	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5897565	0	0
T1	3384	390	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	43	0	0
T1	3384	1	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T56	0	1	0	0
T112	0	1	0	0
T146	0	1	0	0
T148	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	40	0	0
T1	3384	1	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T56	0	1	0	0
T112	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	40	0	0
T1	3384	1	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T56	0	1	0	0
T112	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	40	0	0
T1	3384	1	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T56	0	1	0	0
T112	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	2878	0	0
T1	3384	339	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	48	0	0
T36	0	40	0	0
T38	0	65	0	0
T39	0	5	0	0
T40	0	155	0	0
T56	0	120	0	0
T112	0	75	0	0
T148	0	42	0	0
T149	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	15	0	0
T23	336909	0	0	0
T36	809	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T48	52940	0	0	0
T56	0	1	0	0
T74	504	0	0	0
T81	403	0	0	0
T82	495	0	0	0
T116	0	1	0	0
T123	0	1	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T38,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T9,T38,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T38,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T38,T24
1	0	Covered	T4,T1,T5
1	1	Covered	T9,T38,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T38,T35
0	1	Covered	T154,T155,T156
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T38,T35
0	1	Covered	T35,T56,T157
1	0	Covered	T39

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T38,T35
1	-	Covered	T35,T56,T157

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T38,T35
DetectSt	168	Covered	T9,T38,T35
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T9,T38,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T38,T35
DebounceSt->IdleSt	163	Covered	T38,T91,T158
DetectSt->IdleSt	186	Covered	T154,T155,T156
DetectSt->StableSt	191	Covered	T9,T38,T35
IdleSt->DebounceSt	148	Covered	T9,T38,T35
StableSt->IdleSt	206	Covered	T35,T56,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T38,T35
0	1	Covered	T9,T38,T35
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T38,T35
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T38,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T38,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T91,T158
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T38,T35
DetectSt	-	-	-	-	1	-	-	Covered	T154,T155,T156
DetectSt	-	-	-	-	0	1	-	Covered	T9,T38,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T56,T39
StableSt	-	-	-	-	-	-	0	Covered	T9,T38,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	120	0	0
CntIncr_A	6649655	26755	0	0
CntNoWrap_A	6649655	5989315	0	0
DetectStDropOut_A	6649655	3	0	0
DetectedOut_A	6649655	38777	0	0
DetectedPulseOut_A	6649655	54	0	0
DisabledIdleSt_A	6649655	5915119	0	0
DisabledNoDetection_A	6649655	5917394	0	0
EnterDebounceSt_A	6649655	64	0	0
EnterDetectSt_A	6649655	57	0	0
EnterStableSt_A	6649655	54	0	0
PulseIsPulse_A	6649655	54	0	0
StayInStableSt	6649655	38693	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6649655	2507	0	0
gen_low_level_sva.LowLevelEvent_A	6649655	5991763	0	0
gen_not_sticky_sva.StableStDropOut_A	6649655	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	120	0	0
T9	1004	2	0	0
T10	504	0	0	0
T11	109442	0	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	8	0	0
T38	0	3	0	0
T39	0	2	0	0
T52	719	0	0	0
T56	0	4	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T91	0	5	0	0
T92	0	2	0	0
T146	0	4	0	0
T148	0	2	0	0
T157	0	4	0	0
T159	444	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	26755	0	0
T9	1004	72	0	0
T10	504	0	0	0
T11	109442	0	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	152	0	0
T38	0	44	0	0
T39	0	30	0	0
T52	719	0	0	0
T56	0	30	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T91	0	48	0	0
T92	0	33	0	0
T146	0	66	0	0
T148	0	37	0	0
T157	0	136	0	0
T159	444	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5989315	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	3	0	0
T86	15841	0	0	0
T154	2475	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T160	12371	0	0	0
T161	422	0	0	0
T162	418	0	0	0
T163	402	0	0	0
T164	502	0	0	0
T165	495	0	0	0
T166	502	0	0	0
T167	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	38777	0	0
T9	1004	39	0	0
T10	504	0	0	0
T11	109442	0	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	416	0	0
T38	0	131	0	0
T39	0	6	0	0
T52	719	0	0	0
T56	0	43	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T91	0	116	0	0
T92	0	79	0	0
T146	0	146	0	0
T148	0	143	0	0
T157	0	69	0	0
T159	444	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	54	0	0
T9	1004	1	0	0
T10	504	0	0	0
T11	109442	0	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	4	0	0
T38	0	1	0	0
T39	0	1	0	0
T52	719	0	0	0
T56	0	2	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T91	0	2	0	0
T92	0	1	0	0
T146	0	2	0	0
T148	0	1	0	0
T157	0	2	0	0
T159	444	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5915119	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5917394	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	64	0	0
T9	1004	1	0	0
T10	504	0	0	0
T11	109442	0	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	4	0	0
T38	0	2	0	0
T39	0	1	0	0
T52	719	0	0	0
T56	0	2	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T91	0	3	0	0
T92	0	1	0	0
T146	0	2	0	0
T148	0	1	0	0
T157	0	2	0	0
T159	444	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	57	0	0
T9	1004	1	0	0
T10	504	0	0	0
T11	109442	0	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	4	0	0
T38	0	1	0	0
T39	0	1	0	0
T52	719	0	0	0
T56	0	2	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T91	0	2	0	0
T92	0	1	0	0
T146	0	2	0	0
T148	0	1	0	0
T157	0	2	0	0
T159	444	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	54	0	0
T9	1004	1	0	0
T10	504	0	0	0
T11	109442	0	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	4	0	0
T38	0	1	0	0
T39	0	1	0	0
T52	719	0	0	0
T56	0	2	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T91	0	2	0	0
T92	0	1	0	0
T146	0	2	0	0
T148	0	1	0	0
T157	0	2	0	0
T159	444	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	54	0	0
T9	1004	1	0	0
T10	504	0	0	0
T11	109442	0	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	4	0	0
T38	0	1	0	0
T39	0	1	0	0
T52	719	0	0	0
T56	0	2	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T91	0	2	0	0
T92	0	1	0	0
T146	0	2	0	0
T148	0	1	0	0
T157	0	2	0	0
T159	444	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	38693	0	0
T9	1004	37	0	0
T10	504	0	0	0
T11	109442	0	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	410	0	0
T38	0	129	0	0
T39	0	5	0	0
T52	719	0	0	0
T56	0	40	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T91	0	112	0	0
T92	0	77	0	0
T146	0	143	0	0
T148	0	142	0	0
T157	0	66	0	0
T159	444	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	2507	0	0
T1	3384	16	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T4	503	6	0	0
T5	502	6	0	0
T13	422	2	0	0
T14	426	2	0	0
T15	427	3	0	0
T16	504	5	0	0
T17	449	7	0	0
T25	0	5	0	0
T50	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	23	0	0
T35	119316	2	0	0
T53	6572	0	0	0
T56	0	1	0	0
T76	4315	0	0	0
T77	20631	0	0	0
T93	0	2	0	0
T111	653	0	0	0
T112	702	0	0	0
T113	733	0	0	0
T114	734	0	0	0
T115	426	0	0	0
T134	402	0	0	0
T146	0	1	0	0
T148	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0
T157	0	1	0	0
T168	0	2	0	0
T169	0	1	0	0