Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	90.21	93.48	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	91.56	95.65	90.48		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
90.21	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
91.56	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T83,T54,T84
1	0	Covered	T39,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T39,T86,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T6
1	-	Covered	T2,T3,T6

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
90.21	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T28,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T28,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T28,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T28,T9
1	0	Covered	T4,T1,T5
1	1	Covered	T27,T28,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T9
0	1	Covered	T1,T73,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T9
0	1	Covered	T27,T28,T44
1	0	Covered	T39,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T28,T9
1	-	Covered	T27,T28,T44

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T7,T12
1	0	Covered	T3,T6,T7

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T88,T89,T90

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T7
1	-	Covered	T3,T6,T7

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T23,T24,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T4,T1,T5
1	1	Covered	T22,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T24,T54
0	1	Covered	T23,T35,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T24,T54
0	1	Unreachable
1	0	Covered	T23,T24,T54

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
91.56	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T11
1	0	Covered	T4,T1,T5
1	1	Covered	T1,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Covered	T1,T92,T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Covered	T1,T9,T11
1	0	Covered	T39

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T11
1	-	Covered	T1,T9,T11

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T4,T1,T5
1	1	Covered	T22,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T54,T56
0	1	Covered	T22,T23,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T54,T56
0	1	Unreachable
1	0	Covered	T35,T54,T56

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T4,T1,T5
1	1	Covered	T22,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T24,T54
0	1	Covered	T22,T80,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T24,T54
0	1	Unreachable
1	0	Covered	T23,T24,T54

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T28,T9
DetectSt	168	Covered	T27,T28,T9
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T27,T28,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T28,T9
DebounceSt->IdleSt	163	Covered	T45,T38,T37
DetectSt->IdleSt	186	Covered	T1,T22,T23
DetectSt->StableSt	191	Covered	T27,T28,T9
IdleSt->DebounceSt	148	Covered	T27,T28,T9
StableSt->IdleSt	206	Covered	T27,T28,T44

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
90.21	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
91.56	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T28,T9
0	1	Covered	T27,T28,T9
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T9
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T27,T28,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T28,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T38,T37
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T28,T9
DetectSt	-	-	-	-	1	-	-	Covered	T1,T22,T23
DetectSt	-	-	-	-	0	1	-	Covered	T27,T28,T9
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T27,T28,T44
StableSt	-	-	-	-	-	-	0	Covered	T27,T28,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T35,T39
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T3,T6,T12
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T7
DetectSt	-	-	-	-	0	0	-	Covered	T3,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T7
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T7
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	172891030	17806	0	0
CntIncr_A	172891030	1901442	0	0
CntNoWrap_A	172891030	155707504	0	0
DetectStDropOut_A	172891030	1949	0	0
DetectedOut_A	172891030	1278015	0	0
DetectedPulseOut_A	172891030	5808	0	0
DisabledIdleSt_A	172891030	146053056	0	0
DisabledNoDetection_A	172891030	146109399	0	0
EnterDebounceSt_A	172891030	9220	0	0
EnterDetectSt_A	172891030	8605	0	0
EnterStableSt_A	172891030	5808	0	0
PulseIsPulse_A	172891030	5808	0	0
StayInStableSt	172891030	1271355	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	59846895	50005	0	0
gen_high_event_sva.HighLevelEvent_A	33248275	29958815	0	0
gen_high_level_sva.HighLevelEvent_A	113044135	101859971	0	0
gen_low_level_sva.LowLevelEvent_A	59846895	53925867	0	0
gen_not_sticky_sva.StableStDropOut_A	152942065	4716	0	0
gen_sticky_sva.StableStDropOut_A	19948965	1690456	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172891030	17806	0	0
T2	135600	4	0	0
T3	61488	38	0	0
T6	124368	48	0	0
T7	23533	54	0	0
T8	32789	4	0	0
T9	2008	0	0	0
T10	1008	4	0	0
T11	109442	2	0	0
T12	0	16	0	0
T14	1704	0	0	0
T15	1708	0	0	0
T16	4032	0	0	0
T17	3592	0	0	0
T24	0	2	0	0
T25	2470	0	0	0
T27	6003	2	0	0
T28	5346	2	0	0
T29	3635	0	0	0
T35	0	4	0	0
T37	0	10	0	0
T42	0	52	0	0
T43	0	18	0	0
T44	0	5	0	0
T45	0	3	0	0
T47	0	2	0	0
T48	0	4	0	0
T49	5032	0	0	0
T50	2120	0	0	0
T51	833	0	0	0
T52	719	0	0	0
T67	1334	0	0	0
T74	0	4	0	0
T96	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172891030	1901442	0	0
T2	135600	230	0	0
T3	61488	1431	0	0
T6	124368	1236	0	0
T7	23533	1862	0	0
T8	32789	204	0	0
T9	2008	0	0	0
T10	1008	46	0	0
T11	109442	25	0	0
T12	0	484	0	0
T14	1704	0	0	0
T15	1708	0	0	0
T16	4032	0	0	0
T17	3592	0	0	0
T24	0	36	0	0
T25	2470	0	0	0
T27	6003	44	0	0
T28	5346	13	0	0
T29	3635	0	0	0
T35	0	52	0	0
T37	0	331	0	0
T42	0	1479	0	0
T43	0	464	0	0
T44	0	171	0	0
T45	0	1456	0	0
T47	0	18	0	0
T48	0	152	0	0
T49	5032	0	0	0
T50	2120	0	0	0
T51	833	0	0	0
T52	719	0	0	0
T67	1334	0	0	0
T74	0	46	0	0
T96	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172891030	155707504	0	0
T1	87984	25430	0	0
T2	881400	868564	0	0
T3	199836	189229	0	0
T4	13078	2652	0	0
T5	13052	2626	0	0
T13	10972	546	0	0
T14	11076	650	0	0
T15	11102	676	0	0
T16	13104	2678	0	0
T17	11674	1248	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172891030	1949	0	0
T3	7686	6	0	0
T35	119316	0	0	0
T39	0	1	0	0
T43	0	9	0	0
T53	6572	0	0	0
T76	4315	9	0	0
T77	20631	13	0	0
T83	35940	10	0	0
T87	56084	1	0	0
T89	28754	0	0	0
T90	10794	0	0	0
T95	1546	0	0	0
T97	0	9	0	0
T98	0	9	0	0
T99	0	25	0	0
T100	0	23	0	0
T101	0	3	0	0
T102	0	7	0	0
T103	0	5	0	0
T104	0	2	0	0
T105	0	4	0	0
T106	0	1	0	0
T107	0	2	0	0
T108	0	3	0	0
T109	0	2	0	0
T110	0	2	0	0
T111	653	0	0	0
T112	702	0	0	0
T113	733	0	0	0
T114	734	0	0	0
T115	426	0	0	0
T116	1068	0	0	0
T117	413	0	0	0
T118	423	0	0	0
T119	421	0	0	0
T120	739	0	0	0
T121	29684	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172891030	1278015	0	0
T2	135600	148	0	0
T3	38430	0	0	0
T6	124368	3089	0	0
T7	94132	1688	0	0
T8	131156	96	0	0
T9	2008	0	0	0
T10	1008	81	0	0
T11	109442	3	0	0
T12	0	1634	0	0
T14	1704	0	0	0
T15	1708	0	0	0
T16	2520	0	0	0
T17	2245	0	0	0
T24	0	9	0	0
T25	2470	0	0	0
T27	6003	2	0	0
T28	5346	4	0	0
T29	3635	0	0	0
T35	0	16	0	0
T37	0	27	0	0
T41	0	2778	0	0
T42	0	2491	0	0
T44	0	18	0	0
T45	0	6	0	0
T47	0	11	0	0
T48	0	10	0	0
T49	5032	0	0	0
T50	2120	0	0	0
T51	3332	0	0	0
T52	719	0	0	0
T53	0	4	0	0
T67	1334	0	0	0
T74	0	82	0	0
T96	0	11	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172891030	5808	0	0
T2	135600	2	0	0
T3	38430	0	0	0
T6	124368	24	0	0
T7	94132	27	0	0
T8	131156	2	0	0
T9	2008	0	0	0
T10	1008	2	0	0
T11	109442	1	0	0
T12	0	8	0	0
T14	1704	0	0	0
T15	1708	0	0	0
T16	2520	0	0	0
T17	2245	0	0	0
T24	0	1	0	0
T25	2470	0	0	0
T27	6003	1	0	0
T28	5346	1	0	0
T29	3635	0	0	0
T35	0	2	0	0
T37	0	4	0	0
T41	0	27	0	0
T42	0	25	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	5032	0	0	0
T50	2120	0	0	0
T51	3332	0	0	0
T52	719	0	0	0
T53	0	1	0	0
T67	1334	0	0	0
T74	0	2	0	0
T96	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172891030	146053056	0	0
T1	87984	21303	0	0
T2	881400	847788	0	0
T3	199836	170826	0	0
T4	13078	2652	0	0
T5	13052	2626	0	0
T13	10972	546	0	0
T14	11076	650	0	0
T15	11102	676	0	0
T16	13104	2678	0	0
T17	11674	1248	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172891030	146109399	0	0
T1	87984	21426	0	0
T2	881400	848096	0	0
T3	199836	170848	0	0
T4	13078	2678	0	0
T5	13052	2652	0	0
T13	10972	572	0	0
T14	11076	676	0	0
T15	11102	702	0	0
T16	13104	2704	0	0
T17	11674	1274	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172891030	9220	0	0
T2	135600	2	0	0
T3	61488	19	0	0
T6	124368	24	0	0
T7	23533	27	0	0
T8	32789	2	0	0
T9	2008	0	0	0
T10	1008	2	0	0
T11	109442	1	0	0
T12	0	8	0	0
T14	1704	0	0	0
T15	1708	0	0	0
T16	4032	0	0	0
T17	3592	0	0	0
T24	0	1	0	0
T25	2470	0	0	0
T27	6003	1	0	0
T28	5346	1	0	0
T29	3635	0	0	0
T35	0	2	0	0
T37	0	6	0	0
T42	0	27	0	0
T43	0	9	0	0
T44	0	3	0	0
T45	0	2	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	5032	0	0	0
T50	2120	0	0	0
T51	833	0	0	0
T52	719	0	0	0
T67	1334	0	0	0
T74	0	2	0	0
T96	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172891030	8605	0	0
T2	135600	2	0	0
T3	61488	19	0	0
T6	124368	24	0	0
T7	23533	27	0	0
T8	32789	2	0	0
T9	2008	0	0	0
T10	1008	2	0	0
T11	109442	1	0	0
T12	0	8	0	0
T14	1704	0	0	0
T15	1708	0	0	0
T16	4032	0	0	0
T17	3592	0	0	0
T24	0	1	0	0
T25	2470	0	0	0
T27	6003	1	0	0
T28	5346	1	0	0
T29	3635	0	0	0
T35	0	2	0	0
T37	0	4	0	0
T42	0	25	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	5032	0	0	0
T50	2120	0	0	0
T51	833	0	0	0
T52	719	0	0	0
T67	1334	0	0	0
T74	0	2	0	0
T83	0	10	0	0
T96	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172891030	5808	0	0
T2	135600	2	0	0
T3	38430	0	0	0
T6	124368	24	0	0
T7	94132	27	0	0
T8	131156	2	0	0
T9	2008	0	0	0
T10	1008	2	0	0
T11	109442	1	0	0
T12	0	8	0	0
T14	1704	0	0	0
T15	1708	0	0	0
T16	2520	0	0	0
T17	2245	0	0	0
T24	0	1	0	0
T25	2470	0	0	0
T27	6003	1	0	0
T28	5346	1	0	0
T29	3635	0	0	0
T35	0	2	0	0
T37	0	4	0	0
T41	0	27	0	0
T42	0	25	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	5032	0	0	0
T50	2120	0	0	0
T51	3332	0	0	0
T52	719	0	0	0
T53	0	1	0	0
T67	1334	0	0	0
T74	0	2	0	0
T96	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172891030	5808	0	0
T2	135600	2	0	0
T3	38430	0	0	0
T6	124368	24	0	0
T7	94132	27	0	0
T8	131156	2	0	0
T9	2008	0	0	0
T10	1008	2	0	0
T11	109442	1	0	0
T12	0	8	0	0
T14	1704	0	0	0
T15	1708	0	0	0
T16	2520	0	0	0
T17	2245	0	0	0
T24	0	1	0	0
T25	2470	0	0	0
T27	6003	1	0	0
T28	5346	1	0	0
T29	3635	0	0	0
T35	0	2	0	0
T37	0	4	0	0
T41	0	27	0	0
T42	0	25	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	5032	0	0	0
T50	2120	0	0	0
T51	3332	0	0	0
T52	719	0	0	0
T53	0	1	0	0
T67	1334	0	0	0
T74	0	2	0	0
T96	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	172891030	1271355	0	0
T2	135600	146	0	0
T3	38430	0	0	0
T6	124368	3062	0	0
T7	94132	1657	0	0
T8	131156	94	0	0
T9	2008	0	0	0
T10	1008	78	0	0
T11	109442	2	0	0
T12	0	1626	0	0
T14	1704	0	0	0
T15	1708	0	0	0
T16	2520	0	0	0
T17	2245	0	0	0
T24	0	8	0	0
T25	2470	0	0	0
T27	6003	1	0	0
T28	5346	3	0	0
T29	3635	0	0	0
T35	0	14	0	0
T37	0	23	0	0
T41	0	2748	0	0
T42	0	2459	0	0
T44	0	16	0	0
T45	0	5	0	0
T47	0	10	0	0
T48	0	8	0	0
T49	5032	0	0	0
T50	2120	0	0	0
T51	3332	0	0	0
T52	719	0	0	0
T53	0	3	0	0
T67	1334	0	0	0
T74	0	79	0	0
T96	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59846895	50005	0	0
T1	30456	163	0	0
T2	305100	86	0	0
T3	69174	199	0	0
T4	4527	44	0	0
T5	4518	42	0	0
T13	3798	15	0	0
T14	3834	26	0	0
T15	3843	20	0	0
T16	4536	52	0	0
T17	4041	45	0	0
T25	0	10	0	0
T49	0	4	0	0
T50	0	3	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33248275	29958815	0	0
T1	16920	4920	0	0
T2	169500	167110	0	0
T3	38430	36430	0	0
T4	2515	515	0	0
T5	2510	510	0	0
T13	2110	110	0	0
T14	2130	130	0	0
T15	2135	135	0	0
T16	2520	520	0	0
T17	2245	245	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113044135	101859971	0	0
T1	57528	16728	0	0
T2	576300	568174	0	0
T3	130662	123862	0	0
T4	8551	1751	0	0
T5	8534	1734	0	0
T13	7174	374	0	0
T14	7242	442	0	0
T15	7259	459	0	0
T16	8568	1768	0	0
T17	7633	833	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59846895	53925867	0	0
T1	30456	8856	0	0
T2	305100	300798	0	0
T3	69174	65574	0	0
T4	4527	927	0	0
T5	4518	918	0	0
T13	3798	198	0	0
T14	3834	234	0	0
T15	3843	243	0	0
T16	4536	936	0	0
T17	4041	441	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152942065	4716	0	0
T2	135600	2	0	0
T3	38430	0	0	0
T6	124368	21	0	0
T7	94132	23	0	0
T8	131156	2	0	0
T9	1004	0	0	0
T10	504	1	0	0
T11	0	1	0	0
T12	0	8	0	0
T14	1704	0	0	0
T15	1708	0	0	0
T16	2520	0	0	0
T17	2245	0	0	0
T24	0	1	0	0
T25	2470	0	0	0
T27	6003	1	0	0
T28	5346	1	0	0
T29	3635	0	0	0
T35	119316	2	0	0
T37	0	4	0	0
T42	0	18	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	5032	0	0	0
T50	2120	0	0	0
T51	3332	0	0	0
T53	6572	1	0	0
T54	0	6	0	0
T74	0	1	0	0
T76	4315	0	0	0
T96	0	1	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19948965	1690456	0	0
T23	673818	74834	0	0
T24	0	62	0	0
T35	119316	101632	0	0
T41	30670	0	0	0
T48	105880	0	0	0
T53	6572	0	0	0
T54	0	135448	0	0
T56	0	592	0	0
T74	1008	0	0	0
T76	4315	0	0	0
T77	20631	0	0	0
T78	0	772	0	0
T79	0	474	0	0
T80	0	128	0	0
T91	0	1317	0	0
T93	0	110	0	0
T111	653	0	0	0
T112	702	0	0	0
T113	733	0	0	0
T114	734	0	0	0
T115	426	0	0	0
T122	0	922	0	0
T123	0	572	0	0
T124	0	108	0	0
T125	0	358	0	0
T126	0	1246	0	0
T127	0	91	0	0
T128	854	0	0	0
T129	804	0	0	0
T130	886	0	0	0
T131	872	0	0	0
T132	1048	0	0	0
T133	1008	0	0	0
T134	402	0	0	0