Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T38,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T38,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T38,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T72
1	0	Covered	T4,T1,T5
1	1	Covered	T1,T38,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T38,T35
0	1	Covered	T170
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T38,T35
0	1	Covered	T1,T38,T35
1	0	Covered	T39

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T38,T35
1	-	Covered	T1,T38,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T38,T35
DetectSt	168	Covered	T1,T38,T35
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T38,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T38,T35
DebounceSt->IdleSt	163	Covered	T56,T87,T85
DetectSt->IdleSt	186	Covered	T170
DetectSt->StableSt	191	Covered	T1,T38,T35
IdleSt->DebounceSt	148	Covered	T1,T38,T35
StableSt->IdleSt	206	Covered	T1,T38,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T38,T35
0	1	Covered	T1,T38,T35
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T38,T35
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T38,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T38,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T87
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T38,T35
DetectSt	-	-	-	-	1	-	-	Covered	T170
DetectSt	-	-	-	-	0	1	-	Covered	T1,T38,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T38,T35
StableSt	-	-	-	-	-	-	0	Covered	T1,T38,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	83	0	0
CntIncr_A	6649655	24838	0	0
CntNoWrap_A	6649655	5989352	0	0
DetectStDropOut_A	6649655	1	0	0
DetectedOut_A	6649655	2513	0	0
DetectedPulseOut_A	6649655	39	0	0
DisabledIdleSt_A	6649655	5795716	0	0
DisabledNoDetection_A	6649655	5797992	0	0
EnterDebounceSt_A	6649655	43	0	0
EnterDetectSt_A	6649655	40	0	0
EnterStableSt_A	6649655	39	0	0
PulseIsPulse_A	6649655	39	0	0
StayInStableSt	6649655	2459	0	0
gen_high_level_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_not_sticky_sva.StableStDropOut_A	6649655	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	83	0	0
T1	3384	4	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	4	0	0
T38	0	2	0	0
T39	0	2	0	0
T56	0	1	0	0
T93	0	2	0	0
T122	0	2	0	0
T124	0	2	0	0
T150	0	4	0	0
T171	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	24838	0	0
T1	3384	134	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	108	0	0
T38	0	22	0	0
T39	0	30	0	0
T56	0	15	0	0
T93	0	21	0	0
T122	0	38	0	0
T124	0	14	0	0
T150	0	72	0	0
T171	0	36	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5989352	0	0
T1	3384	975	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	1	0	0
T170	79741	1	0	0
T172	500	0	0	0
T173	1032	0	0	0
T174	21993	0	0	0
T175	522	0	0	0
T176	825	0	0	0
T177	408	0	0	0
T178	490	0	0	0
T179	9828	0	0	0
T180	856	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	2513	0	0
T1	3384	86	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	189	0	0
T38	0	96	0	0
T39	0	5	0	0
T93	0	40	0	0
T116	0	213	0	0
T122	0	104	0	0
T124	0	43	0	0
T150	0	90	0	0
T171	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	39	0	0
T1	3384	2	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T93	0	1	0	0
T116	0	2	0	0
T122	0	1	0	0
T124	0	1	0	0
T150	0	2	0	0
T171	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5795716	0	0
T1	3384	386	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5797992	0	0
T1	3384	390	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	43	0	0
T1	3384	2	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T56	0	1	0	0
T93	0	1	0	0
T122	0	1	0	0
T124	0	1	0	0
T150	0	2	0	0
T171	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	40	0	0
T1	3384	2	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T93	0	1	0	0
T116	0	2	0	0
T122	0	1	0	0
T124	0	1	0	0
T150	0	2	0	0
T171	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	39	0	0
T1	3384	2	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T93	0	1	0	0
T116	0	2	0	0
T122	0	1	0	0
T124	0	1	0	0
T150	0	2	0	0
T171	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	39	0	0
T1	3384	2	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T93	0	1	0	0
T116	0	2	0	0
T122	0	1	0	0
T124	0	1	0	0
T150	0	2	0	0
T171	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	2459	0	0
T1	3384	83	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	186	0	0
T38	0	95	0	0
T39	0	4	0	0
T93	0	39	0	0
T116	0	211	0	0
T122	0	102	0	0
T124	0	41	0	0
T150	0	87	0	0
T171	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	23	0	0
T1	3384	1	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T93	0	1	0	0
T116	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0
T181	0	1	0	0
T182	0	2	0	0
T183	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T36,T38,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T36,T38,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T36,T38,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T72,T36,T38
1	0	Covered	T4,T1,T5
1	1	Covered	T36,T38,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T38,T37
0	1	Covered	T184
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T36,T38,T37
0	1	Covered	T36,T38,T37
1	0	Covered	T39

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T36,T38,T37
1	-	Covered	T36,T38,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T36,T38,T37
DetectSt	168	Covered	T36,T38,T37
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T36,T38,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T36,T38,T37
DebounceSt->IdleSt	163	Covered	T35,T124,T150
DetectSt->IdleSt	186	Covered	T184
DetectSt->StableSt	191	Covered	T36,T38,T37
IdleSt->DebounceSt	148	Covered	T36,T38,T37
StableSt->IdleSt	206	Covered	T36,T38,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T36,T38,T37
0	1	Covered	T36,T38,T37
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T36,T38,T37
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T38,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T36,T38,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T124,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T38,T37
DetectSt	-	-	-	-	1	-	-	Covered	T184
DetectSt	-	-	-	-	0	1	-	Covered	T36,T38,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T38,T37
StableSt	-	-	-	-	-	-	0	Covered	T36,T38,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	121	0	0
CntIncr_A	6649655	3668	0	0
CntNoWrap_A	6649655	5989314	0	0
DetectStDropOut_A	6649655	1	0	0
DetectedOut_A	6649655	4070	0	0
DetectedPulseOut_A	6649655	56	0	0
DisabledIdleSt_A	6649655	5950380	0	0
DisabledNoDetection_A	6649655	5952656	0	0
EnterDebounceSt_A	6649655	65	0	0
EnterDetectSt_A	6649655	57	0	0
EnterStableSt_A	6649655	56	0	0
PulseIsPulse_A	6649655	56	0	0
StayInStableSt	6649655	3985	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6649655	2957	0	0
gen_low_level_sva.LowLevelEvent_A	6649655	5991763	0	0
gen_not_sticky_sva.StableStDropOut_A	6649655	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	121	0	0
T23	336909	0	0	0
T35	0	5	0	0
T36	809	2	0	0
T37	0	6	0	0
T38	0	4	0	0
T39	0	2	0	0
T48	52940	0	0	0
T56	0	4	0	0
T74	504	0	0	0
T81	403	0	0	0
T82	495	0	0	0
T93	0	6	0	0
T122	0	2	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T157	0	4	0	0
T185	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	3668	0	0
T23	336909	0	0	0
T35	0	155	0	0
T36	809	69	0	0
T37	0	141	0	0
T38	0	44	0	0
T39	0	30	0	0
T48	52940	0	0	0
T56	0	30	0	0
T74	504	0	0	0
T81	403	0	0	0
T82	495	0	0	0
T93	0	170	0	0
T122	0	38	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T157	0	136	0	0
T185	0	63	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5989314	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	1	0	0
T153	1093	0	0	0
T183	7902	0	0	0
T184	3069	1	0	0
T186	407	0	0	0
T187	2893	0	0	0
T188	526	0	0	0
T189	626	0	0	0
T190	823	0	0	0
T191	417	0	0	0
T192	444	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	4070	0	0
T23	336909	0	0	0
T35	0	74	0	0
T36	809	140	0	0
T37	0	118	0	0
T38	0	78	0	0
T39	0	5	0	0
T48	52940	0	0	0
T56	0	157	0	0
T74	504	0	0	0
T81	403	0	0	0
T82	495	0	0	0
T93	0	87	0	0
T122	0	74	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T157	0	172	0	0
T185	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	56	0	0
T23	336909	0	0	0
T35	0	2	0	0
T36	809	1	0	0
T37	0	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T48	52940	0	0	0
T56	0	2	0	0
T74	504	0	0	0
T81	403	0	0	0
T82	495	0	0	0
T93	0	3	0	0
T122	0	1	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T157	0	2	0	0
T185	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5950380	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5952656	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	65	0	0
T23	336909	0	0	0
T35	0	3	0	0
T36	809	1	0	0
T37	0	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T48	52940	0	0	0
T56	0	2	0	0
T74	504	0	0	0
T81	403	0	0	0
T82	495	0	0	0
T93	0	3	0	0
T122	0	1	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T157	0	2	0	0
T185	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	57	0	0
T23	336909	0	0	0
T35	0	2	0	0
T36	809	1	0	0
T37	0	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T48	52940	0	0	0
T56	0	2	0	0
T74	504	0	0	0
T81	403	0	0	0
T82	495	0	0	0
T93	0	3	0	0
T122	0	1	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T157	0	2	0	0
T185	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	56	0	0
T23	336909	0	0	0
T35	0	2	0	0
T36	809	1	0	0
T37	0	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T48	52940	0	0	0
T56	0	2	0	0
T74	504	0	0	0
T81	403	0	0	0
T82	495	0	0	0
T93	0	3	0	0
T122	0	1	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T157	0	2	0	0
T185	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	56	0	0
T23	336909	0	0	0
T35	0	2	0	0
T36	809	1	0	0
T37	0	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T48	52940	0	0	0
T56	0	2	0	0
T74	504	0	0	0
T81	403	0	0	0
T82	495	0	0	0
T93	0	3	0	0
T122	0	1	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T157	0	2	0	0
T185	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	3985	0	0
T23	336909	0	0	0
T35	0	72	0	0
T36	809	139	0	0
T37	0	114	0	0
T38	0	75	0	0
T39	0	4	0	0
T48	52940	0	0	0
T56	0	154	0	0
T74	504	0	0	0
T81	403	0	0	0
T82	495	0	0	0
T93	0	83	0	0
T122	0	73	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T157	0	170	0	0
T185	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	2957	0	0
T1	3384	21	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T4	503	6	0	0
T5	502	6	0	0
T13	422	2	0	0
T14	426	3	0	0
T15	427	2	0	0
T16	504	4	0	0
T17	449	6	0	0
T25	0	5	0	0
T49	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	26	0	0
T23	336909	0	0	0
T35	0	2	0	0
T36	809	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T48	52940	0	0	0
T56	0	1	0	0
T74	504	0	0	0
T81	403	0	0	0
T82	495	0	0	0
T93	0	2	0	0
T122	0	1	0	0
T123	0	1	0	0
T128	427	0	0	0
T129	402	0	0	0
T130	443	0	0	0
T131	436	0	0	0
T157	0	2	0	0
T185	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T11
1	0	Covered	T4,T1,T5
1	1	Covered	T1,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Covered	T92,T193
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Covered	T1,T9,T11
1	0	Covered	T39

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T11
1	-	Covered	T1,T9,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T11
DetectSt	168	Covered	T1,T9,T11
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T11
DebounceSt->IdleSt	163	Covered	T112,T122,T158
DetectSt->IdleSt	186	Covered	T92,T193
DetectSt->StableSt	191	Covered	T1,T9,T11
IdleSt->DebounceSt	148	Covered	T1,T9,T11
StableSt->IdleSt	206	Covered	T1,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T11
0	1	Covered	T1,T9,T11
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T11
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T112,T122,T158
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T92,T193
DetectSt	-	-	-	-	0	1	-	Covered	T1,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T9,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	141	0	0
CntIncr_A	6649655	85596	0	0
CntNoWrap_A	6649655	5989294	0	0
DetectStDropOut_A	6649655	2	0	0
DetectedOut_A	6649655	67148	0	0
DetectedPulseOut_A	6649655	66	0	0
DisabledIdleSt_A	6649655	5782016	0	0
DisabledNoDetection_A	6649655	5784284	0	0
EnterDebounceSt_A	6649655	74	0	0
EnterDetectSt_A	6649655	68	0	0
EnterStableSt_A	6649655	66	0	0
PulseIsPulse_A	6649655	66	0	0
StayInStableSt	6649655	67046	0	0
gen_high_level_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_not_sticky_sva.StableStDropOut_A	6649655	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	141	0	0
T1	3384	4	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T9	0	4	0	0
T11	0	2	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T37	0	6	0	0
T38	0	2	0	0
T39	0	2	0	0
T56	0	4	0	0
T91	0	2	0	0
T92	0	2	0	0
T112	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	85596	0	0
T1	3384	134	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T9	0	144	0	0
T11	0	47338	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T37	0	141	0	0
T38	0	22	0	0
T39	0	30	0	0
T56	0	30	0	0
T91	0	14	0	0
T92	0	33	0	0
T112	0	104	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5989294	0	0
T1	3384	975	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	2	0	0
T39	7361	0	0	0
T40	1109	0	0	0
T92	522	1	0	0
T99	4766	0	0	0
T157	965	0	0	0
T193	0	1	0	0
T194	672	0	0	0
T195	529	0	0	0
T196	445	0	0	0
T197	4402	0	0	0
T198	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	67148	0	0
T1	3384	112	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T9	0	79	0	0
T11	0	12009	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T37	0	125	0	0
T38	0	65	0	0
T39	0	5	0	0
T56	0	81	0	0
T91	0	62	0	0
T112	0	15	0	0
T146	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	66	0	0
T1	3384	2	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T9	0	2	0	0
T11	0	1	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	1	0	0
T56	0	2	0	0
T91	0	1	0	0
T112	0	1	0	0
T146	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5782016	0	0
T1	3384	386	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5784284	0	0
T1	3384	390	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	74	0	0
T1	3384	2	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T9	0	2	0	0
T11	0	1	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	1	0	0
T56	0	2	0	0
T91	0	1	0	0
T92	0	1	0	0
T112	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	68	0	0
T1	3384	2	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T9	0	2	0	0
T11	0	1	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	1	0	0
T56	0	2	0	0
T91	0	1	0	0
T92	0	1	0	0
T112	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	66	0	0
T1	3384	2	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T9	0	2	0	0
T11	0	1	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	1	0	0
T56	0	2	0	0
T91	0	1	0	0
T112	0	1	0	0
T146	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	66	0	0
T1	3384	2	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T9	0	2	0	0
T11	0	1	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	1	0	0
T56	0	2	0	0
T91	0	1	0	0
T112	0	1	0	0
T146	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	67046	0	0
T1	3384	110	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T9	0	76	0	0
T11	0	12008	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T37	0	121	0	0
T38	0	64	0	0
T39	0	4	0	0
T56	0	78	0	0
T91	0	60	0	0
T112	0	14	0	0
T146	0	41	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	29	0	0
T1	3384	2	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T56	0	1	0	0
T93	0	1	0	0
T112	0	1	0	0
T148	0	1	0	0
T168	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T11,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T11,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T11,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T36,T37
1	0	Covered	T4,T1,T5
1	1	Covered	T11,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T36,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T36,T37
0	1	Covered	T37,T35,T112
1	0	Covered	T39

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T36,T37
1	-	Covered	T37,T35,T112

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T36,T37
DetectSt	168	Covered	T11,T36,T37
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T11,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T36,T37
DebounceSt->IdleSt	163	Covered	T37,T93,T85
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T36,T37
IdleSt->DebounceSt	148	Covered	T11,T36,T37
StableSt->IdleSt	206	Covered	T11,T37,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T36,T37
0	1	Covered	T11,T36,T37
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T36,T37
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T37,T93
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T36,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T35,T112
StableSt	-	-	-	-	-	-	0	Covered	T11,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	79	0	0
CntIncr_A	6649655	49120	0	0
CntNoWrap_A	6649655	5989356	0	0
DetectStDropOut_A	6649655	0	0	0
DetectedOut_A	6649655	2008	0	0
DetectedPulseOut_A	6649655	38	0	0
DisabledIdleSt_A	6649655	5793137	0	0
DisabledNoDetection_A	6649655	5795412	0	0
EnterDebounceSt_A	6649655	41	0	0
EnterDetectSt_A	6649655	38	0	0
EnterStableSt_A	6649655	38	0	0
PulseIsPulse_A	6649655	38	0	0
StayInStableSt	6649655	1948	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6649655	6438	0	0
gen_low_level_sva.LowLevelEvent_A	6649655	5991763	0	0
gen_not_sticky_sva.StableStDropOut_A	6649655	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	79	0	0
T11	109442	2	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	6	0	0
T36	0	2	0	0
T37	0	3	0	0
T39	0	2	0	0
T42	18387	0	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T70	503	0	0	0
T91	0	4	0	0
T92	0	2	0	0
T93	0	3	0	0
T112	0	4	0	0
T157	0	2	0	0
T159	444	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	49120	0	0
T11	109442	47338	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	87	0	0
T36	0	69	0	0
T37	0	94	0	0
T39	0	30	0	0
T42	18387	0	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T70	503	0	0	0
T91	0	34	0	0
T92	0	33	0	0
T93	0	51	0	0
T112	0	104	0	0
T157	0	68	0	0
T159	444	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5989356	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	2008	0	0
T11	109442	44	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	128	0	0
T36	0	120	0	0
T37	0	43	0	0
T39	0	5	0	0
T42	18387	0	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T70	503	0	0	0
T91	0	88	0	0
T92	0	45	0	0
T93	0	41	0	0
T112	0	84	0	0
T157	0	42	0	0
T159	444	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	38	0	0
T11	109442	1	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	18387	0	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T70	503	0	0	0
T91	0	2	0	0
T92	0	1	0	0
T93	0	1	0	0
T112	0	2	0	0
T157	0	1	0	0
T159	444	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5793137	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5795412	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	41	0	0
T11	109442	1	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T42	18387	0	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T70	503	0	0	0
T91	0	2	0	0
T92	0	1	0	0
T93	0	2	0	0
T112	0	2	0	0
T157	0	1	0	0
T159	444	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	38	0	0
T11	109442	1	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	18387	0	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T70	503	0	0	0
T91	0	2	0	0
T92	0	1	0	0
T93	0	1	0	0
T112	0	2	0	0
T157	0	1	0	0
T159	444	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	38	0	0
T11	109442	1	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	18387	0	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T70	503	0	0	0
T91	0	2	0	0
T92	0	1	0	0
T93	0	1	0	0
T112	0	2	0	0
T157	0	1	0	0
T159	444	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	38	0	0
T11	109442	1	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	18387	0	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T70	503	0	0	0
T91	0	2	0	0
T92	0	1	0	0
T93	0	1	0	0
T112	0	2	0	0
T157	0	1	0	0
T159	444	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	1948	0	0
T11	109442	42	0	0
T12	7112	0	0	0
T26	490	0	0	0
T35	0	124	0	0
T36	0	118	0	0
T37	0	42	0	0
T39	0	4	0	0
T42	18387	0	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T70	503	0	0	0
T91	0	85	0	0
T92	0	43	0	0
T93	0	39	0	0
T112	0	81	0	0
T157	0	41	0	0
T159	444	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	6438	0	0
T1	3384	15	0	0
T2	33900	17	0	0
T3	7686	30	0	0
T4	503	3	0	0
T5	502	3	0	0
T13	422	2	0	0
T14	426	4	0	0
T15	427	2	0	0
T16	504	8	0	0
T17	449	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	15	0	0
T24	6662	0	0	0
T35	0	2	0	0
T37	11126	1	0	0
T73	12861	0	0	0
T75	11183	0	0	0
T91	0	1	0	0
T112	0	1	0	0
T122	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T157	0	1	0	0
T182	0	1	0	0
T199	0	1	0	0
T200	403	0	0	0
T201	501	0	0	0
T202	501	0	0	0
T203	527	0	0	0
T204	631	0	0	0
T205	521	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T36,T37
1	0	Covered	T4,T1,T5
1	1	Covered	T1,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T36,T37
0	1	Covered	T1,T93,T206
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T36,T37
0	1	Covered	T1,T37,T35
1	0	Covered	T39

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T36,T37
1	-	Covered	T1,T37,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T36,T37
DetectSt	168	Covered	T1,T36,T37
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T36,T37
DebounceSt->IdleSt	163	Covered	T85,T193,T170
DetectSt->IdleSt	186	Covered	T1,T93,T206
DetectSt->StableSt	191	Covered	T1,T36,T37
IdleSt->DebounceSt	148	Covered	T1,T36,T37
StableSt->IdleSt	206	Covered	T1,T37,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T36,T37
0	1	Covered	T1,T36,T37
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T36,T37
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T193,T207
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T36,T37
DetectSt	-	-	-	-	1	-	-	Covered	T1,T93,T206
DetectSt	-	-	-	-	0	1	-	Covered	T1,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T37,T35
StableSt	-	-	-	-	-	-	0	Covered	T1,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	115	0	0
CntIncr_A	6649655	4706	0	0
CntNoWrap_A	6649655	5989320	0	0
DetectStDropOut_A	6649655	3	0	0
DetectedOut_A	6649655	4118	0	0
DetectedPulseOut_A	6649655	53	0	0
DisabledIdleSt_A	6649655	5817571	0	0
DisabledNoDetection_A	6649655	5819850	0	0
EnterDebounceSt_A	6649655	60	0	0
EnterDetectSt_A	6649655	56	0	0
EnterStableSt_A	6649655	53	0	0
PulseIsPulse_A	6649655	53	0	0
StayInStableSt	6649655	4037	0	0
gen_high_level_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_not_sticky_sva.StableStDropOut_A	6649655	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	115	0	0
T1	3384	6	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	8	0	0
T36	0	2	0	0
T37	0	6	0	0
T39	0	2	0	0
T91	0	6	0	0
T93	0	4	0	0
T122	0	2	0	0
T199	0	4	0	0
T208	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	4706	0	0
T1	3384	201	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	159	0	0
T36	0	69	0	0
T37	0	141	0	0
T39	0	30	0	0
T91	0	45	0	0
T93	0	100	0	0
T122	0	38	0	0
T199	0	92	0	0
T208	0	61	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5989320	0	0
T1	3384	973	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	3	0	0
T1	3384	1	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T93	0	1	0	0
T206	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	4118	0	0
T1	3384	86	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	397	0	0
T36	0	39	0	0
T37	0	155	0	0
T39	0	7	0	0
T91	0	96	0	0
T93	0	44	0	0
T122	0	216	0	0
T199	0	222	0	0
T208	0	47	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	53	0	0
T1	3384	2	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	4	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	1	0	0
T91	0	3	0	0
T93	0	1	0	0
T122	0	1	0	0
T199	0	2	0	0
T208	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5817571	0	0
T1	3384	386	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5819850	0	0
T1	3384	390	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	60	0	0
T1	3384	3	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	4	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	1	0	0
T91	0	3	0	0
T93	0	2	0	0
T122	0	1	0	0
T199	0	2	0	0
T208	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	56	0	0
T1	3384	3	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	4	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	1	0	0
T91	0	3	0	0
T93	0	2	0	0
T122	0	1	0	0
T199	0	2	0	0
T208	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	53	0	0
T1	3384	2	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	4	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	1	0	0
T91	0	3	0	0
T93	0	1	0	0
T122	0	1	0	0
T199	0	2	0	0
T208	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	53	0	0
T1	3384	2	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	4	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	1	0	0
T91	0	3	0	0
T93	0	1	0	0
T122	0	1	0	0
T199	0	2	0	0
T208	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	4037	0	0
T1	3384	83	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	391	0	0
T36	0	37	0	0
T37	0	151	0	0
T39	0	6	0	0
T91	0	91	0	0
T93	0	43	0	0
T122	0	214	0	0
T199	0	219	0	0
T208	0	45	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	24	0	0
T1	3384	1	0	0
T2	33900	0	0	0
T3	7686	0	0	0
T5	502	0	0	0
T6	15546	0	0	0
T13	422	0	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T87	0	1	0	0
T91	0	1	0	0
T93	0	1	0	0
T116	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T11,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T9,T11,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T11,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T35
1	0	Covered	T4,T1,T5
1	1	Covered	T9,T11,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T39
0	1	Covered	T153
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T39
0	1	Covered	T9,T40,T91
1	0	Covered	T39

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T39
1	-	Covered	T9,T40,T91

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T11,T39
DetectSt	168	Covered	T9,T11,T39
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T9,T11,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T39
DebounceSt->IdleSt	163	Covered	T9,T181,T85
DetectSt->IdleSt	186	Covered	T153
DetectSt->StableSt	191	Covered	T9,T11,T39
IdleSt->DebounceSt	148	Covered	T9,T11,T39
StableSt->IdleSt	206	Covered	T9,T11,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T11,T39
0	1	Covered	T9,T11,T39
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T39
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T11,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T181,T147
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T11,T39
DetectSt	-	-	-	-	1	-	-	Covered	T153
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T39,T40
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	70	0	0
CntIncr_A	6649655	49430	0	0
CntNoWrap_A	6649655	5989365	0	0
DetectStDropOut_A	6649655	1	0	0
DetectedOut_A	6649655	2212	0	0
DetectedPulseOut_A	6649655	32	0	0
DisabledIdleSt_A	6649655	5806990	0	0
DisabledNoDetection_A	6649655	5809264	0	0
EnterDebounceSt_A	6649655	37	0	0
EnterDetectSt_A	6649655	33	0	0
EnterStableSt_A	6649655	32	0	0
PulseIsPulse_A	6649655	32	0	0
StayInStableSt	6649655	2165	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6649655	5998	0	0
gen_low_level_sva.LowLevelEvent_A	6649655	5991763	0	0
gen_not_sticky_sva.StableStDropOut_A	6649655	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	70	0	0
T9	1004	3	0	0
T10	504	0	0	0
T11	109442	2	0	0
T12	7112	0	0	0
T26	490	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T87	0	2	0	0
T91	0	2	0	0
T93	0	4	0	0
T123	0	2	0	0
T159	444	0	0	0
T168	0	4	0	0
T209	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	49430	0	0
T9	1004	144	0	0
T10	504	0	0	0
T11	109442	47338	0	0
T12	7112	0	0	0
T26	490	0	0	0
T39	0	30	0	0
T40	0	142	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T87	0	84	0	0
T91	0	14	0	0
T93	0	91	0	0
T123	0	79	0	0
T159	444	0	0	0
T168	0	156	0	0
T209	0	80	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5989365	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	1	0	0
T110	8928	0	0	0
T153	1093	1	0	0
T183	7902	0	0	0
T192	444	0	0	0
T210	41167	0	0	0
T211	698	0	0	0
T212	26394	0	0	0
T213	435	0	0	0
T214	421	0	0	0
T215	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	2212	0	0
T9	1004	39	0	0
T10	504	0	0	0
T11	109442	43	0	0
T12	7112	0	0	0
T26	490	0	0	0
T39	0	6	0	0
T40	0	108	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T87	0	125	0	0
T91	0	56	0	0
T93	0	439	0	0
T123	0	43	0	0
T159	444	0	0	0
T168	0	86	0	0
T209	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	32	0	0
T9	1004	1	0	0
T10	504	0	0	0
T11	109442	1	0	0
T12	7112	0	0	0
T26	490	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T87	0	1	0	0
T91	0	1	0	0
T93	0	2	0	0
T123	0	1	0	0
T159	444	0	0	0
T168	0	2	0	0
T209	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5806990	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5809264	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	37	0	0
T9	1004	2	0	0
T10	504	0	0	0
T11	109442	1	0	0
T12	7112	0	0	0
T26	490	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T87	0	1	0	0
T91	0	1	0	0
T93	0	2	0	0
T123	0	1	0	0
T159	444	0	0	0
T168	0	2	0	0
T209	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	33	0	0
T9	1004	1	0	0
T10	504	0	0	0
T11	109442	1	0	0
T12	7112	0	0	0
T26	490	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T87	0	1	0	0
T91	0	1	0	0
T93	0	2	0	0
T123	0	1	0	0
T159	444	0	0	0
T168	0	2	0	0
T209	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	32	0	0
T9	1004	1	0	0
T10	504	0	0	0
T11	109442	1	0	0
T12	7112	0	0	0
T26	490	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T87	0	1	0	0
T91	0	1	0	0
T93	0	2	0	0
T123	0	1	0	0
T159	444	0	0	0
T168	0	2	0	0
T209	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	32	0	0
T9	1004	1	0	0
T10	504	0	0	0
T11	109442	1	0	0
T12	7112	0	0	0
T26	490	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T87	0	1	0	0
T91	0	1	0	0
T93	0	2	0	0
T123	0	1	0	0
T159	444	0	0	0
T168	0	2	0	0
T209	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	2165	0	0
T9	1004	38	0	0
T10	504	0	0	0
T11	109442	41	0	0
T12	7112	0	0	0
T26	490	0	0	0
T39	0	5	0	0
T40	0	105	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T87	0	124	0	0
T91	0	55	0	0
T93	0	435	0	0
T123	0	42	0	0
T159	444	0	0	0
T168	0	83	0	0
T209	0	44	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5998	0	0
T1	3384	21	0	0
T2	33900	11	0	0
T3	7686	34	0	0
T4	503	5	0	0
T5	502	5	0	0
T13	422	1	0	0
T14	426	2	0	0
T15	427	3	0	0
T16	504	7	0	0
T17	449	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	16	0	0
T9	1004	1	0	0
T10	504	0	0	0
T11	109442	0	0	0
T12	7112	0	0	0
T26	490	0	0	0
T40	0	1	0	0
T52	719	0	0	0
T67	1334	0	0	0
T68	502	0	0	0
T69	525	0	0	0
T87	0	1	0	0
T91	0	1	0	0
T123	0	1	0	0
T152	0	1	0	0
T159	444	0	0	0
T168	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0
T218	0	1	0	0