Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T43,T76
1	0	Covered	T3,T75,T77

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T10
0	1	Covered	T6,T7,T12
1	0	Covered	T88,T255

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T10
1	-	Covered	T6,T7,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T7
DetectSt	168	Covered	T3,T6,T7
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T6,T7,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T7
DebounceSt->IdleSt	163	Covered	T39,T101,T256
DetectSt->IdleSt	186	Covered	T3,T43,T75
DetectSt->StableSt	191	Covered	T6,T7,T10
IdleSt->DebounceSt	148	Covered	T3,T6,T7
StableSt->IdleSt	206	Covered	T6,T7,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T3,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T101,T256
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T3,T43,T75
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T10
DetectSt	-	-	-	-	0	0	-	Covered	T3,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T6,T7,T12
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	3069	0	0
CntIncr_A	6649655	117702	0	0
CntNoWrap_A	6649655	5986366	0	0
DetectStDropOut_A	6649655	389	0	0
DetectedOut_A	6649655	91797	0	0
DetectedPulseOut_A	6649655	970	0	0
DisabledIdleSt_A	6649655	5492568	0	0
DisabledNoDetection_A	6649655	5494674	0	0
EnterDebounceSt_A	6649655	1549	0	0
EnterDetectSt_A	6649655	1520	0	0
EnterStableSt_A	6649655	970	0	0
PulseIsPulse_A	6649655	970	0	0
StayInStableSt	6649655	90697	0	0
gen_high_event_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_high_level_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_not_sticky_sva.StableStDropOut_A	6649655	825	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	3069	0	0
T3	7686	38	0	0
T6	15546	44	0	0
T7	0	50	0	0
T10	0	2	0	0
T12	0	12	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T41	0	54	0	0
T42	0	44	0	0
T43	0	18	0	0
T49	629	0	0	0
T50	424	0	0	0
T74	0	2	0	0
T75	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	117702	0	0
T3	7686	1431	0	0
T6	15546	1166	0	0
T7	0	1750	0	0
T10	0	21	0	0
T12	0	318	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T41	0	1377	0	0
T42	0	1166	0	0
T43	0	464	0	0
T49	629	0	0	0
T50	424	0	0	0
T74	0	21	0	0
T75	0	692	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5986366	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7247	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	389	0	0
T3	7686	6	0	0
T6	15546	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	1	0	0
T43	0	9	0	0
T49	629	0	0	0
T50	424	0	0	0
T76	0	9	0	0
T77	0	13	0	0
T97	0	9	0	0
T98	0	9	0	0
T99	0	25	0	0
T100	0	23	0	0
T101	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	91797	0	0
T6	15546	2553	0	0
T7	23533	1538	0	0
T8	32789	0	0	0
T10	0	78	0	0
T12	0	1527	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	352	0	0
T41	0	2778	0	0
T42	0	2332	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T74	0	79	0	0
T243	0	187	0	0
T257	0	2087	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	970	0	0
T6	15546	22	0	0
T7	23533	25	0	0
T8	32789	0	0	0
T10	0	1	0	0
T12	0	6	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	5	0	0
T41	0	27	0	0
T42	0	22	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T74	0	1	0	0
T243	0	8	0	0
T257	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5492568	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	3331	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5494674	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	3331	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	1549	0	0
T3	7686	19	0	0
T6	15546	22	0	0
T7	0	25	0	0
T10	0	1	0	0
T12	0	6	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T41	0	27	0	0
T42	0	22	0	0
T43	0	9	0	0
T49	629	0	0	0
T50	424	0	0	0
T74	0	1	0	0
T75	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	1520	0	0
T3	7686	19	0	0
T6	15546	22	0	0
T7	0	25	0	0
T10	0	1	0	0
T12	0	6	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T41	0	27	0	0
T42	0	22	0	0
T43	0	9	0	0
T49	629	0	0	0
T50	424	0	0	0
T74	0	1	0	0
T75	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	970	0	0
T6	15546	22	0	0
T7	23533	25	0	0
T8	32789	0	0	0
T10	0	1	0	0
T12	0	6	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	5	0	0
T41	0	27	0	0
T42	0	22	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T74	0	1	0	0
T243	0	8	0	0
T257	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	970	0	0
T6	15546	22	0	0
T7	23533	25	0	0
T8	32789	0	0	0
T10	0	1	0	0
T12	0	6	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	5	0	0
T41	0	27	0	0
T42	0	22	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T74	0	1	0	0
T243	0	8	0	0
T257	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	90697	0	0
T6	15546	2528	0	0
T7	23533	1509	0	0
T8	32789	0	0	0
T10	0	76	0	0
T12	0	1521	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	347	0	0
T41	0	2748	0	0
T42	0	2306	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T74	0	77	0	0
T243	0	179	0	0
T257	0	2055	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	825	0	0
T6	15546	19	0	0
T7	23533	21	0	0
T8	32789	0	0	0
T12	0	6	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	5	0	0
T41	0	24	0	0
T42	0	18	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T243	0	8	0	0
T257	0	20	0	0
T258	0	26	0	0
T259	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T83,T102,T103
1	0	Covered	T39,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
1	0	Covered	T39

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T7
1	-	Covered	T2,T6,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T7
DetectSt	168	Covered	T2,T6,T7
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T6,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T7
DebounceSt->IdleSt	163	Covered	T42,T44,T41
DetectSt->IdleSt	186	Covered	T83,T39,T102
DetectSt->StableSt	191	Covered	T2,T6,T7
IdleSt->DebounceSt	148	Covered	T2,T6,T7
StableSt->IdleSt	206	Covered	T2,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T44,T41
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T83,T39,T102
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T7
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T7
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	977	0	0
CntIncr_A	6649655	49663	0	0
CntNoWrap_A	6649655	5988458	0	0
DetectStDropOut_A	6649655	53	0	0
DetectedOut_A	6649655	17705	0	0
DetectedPulseOut_A	6649655	389	0	0
DisabledIdleSt_A	6649655	5602698	0	0
DisabledNoDetection_A	6649655	5604302	0	0
EnterDebounceSt_A	6649655	532	0	0
EnterDetectSt_A	6649655	447	0	0
EnterStableSt_A	6649655	389	0	0
PulseIsPulse_A	6649655	389	0	0
StayInStableSt	6649655	17288	0	0
gen_high_level_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_not_sticky_sva.StableStDropOut_A	6649655	359	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	977	0	0
T2	33900	4	0	0
T3	7686	0	0	0
T6	15546	4	0	0
T7	0	4	0	0
T8	0	4	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	4	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T42	0	8	0	0
T44	0	1	0	0
T49	629	0	0	0
T74	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	49663	0	0
T2	33900	230	0	0
T3	7686	0	0	0
T6	15546	70	0	0
T7	0	112	0	0
T8	0	204	0	0
T10	0	25	0	0
T11	0	25	0	0
T12	0	166	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T42	0	313	0	0
T44	0	20	0	0
T49	629	0	0	0
T74	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5988458	0	0
T1	3384	979	0	0
T2	33900	33404	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	53	0	0
T35	119316	0	0	0
T53	6572	0	0	0
T76	4315	0	0	0
T77	20631	0	0	0
T83	35940	10	0	0
T102	0	7	0	0
T103	0	5	0	0
T104	0	2	0	0
T105	0	4	0	0
T106	0	1	0	0
T107	0	2	0	0
T108	0	3	0	0
T109	0	2	0	0
T110	0	2	0	0
T111	653	0	0	0
T112	702	0	0	0
T113	733	0	0	0
T114	734	0	0	0
T115	426	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	17705	0	0
T2	33900	148	0	0
T3	7686	0	0	0
T6	15546	536	0	0
T7	0	150	0	0
T8	0	96	0	0
T10	0	3	0	0
T11	0	3	0	0
T12	0	107	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T42	0	159	0	0
T49	629	0	0	0
T53	0	4	0	0
T74	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	389	0	0
T2	33900	2	0	0
T3	7686	0	0	0
T6	15546	2	0	0
T7	0	2	0	0
T8	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T42	0	3	0	0
T49	629	0	0	0
T53	0	1	0	0
T74	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5602698	0	0
T1	3384	979	0	0
T2	33900	28203	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5604302	0	0
T1	3384	984	0	0
T2	33900	28203	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	532	0	0
T2	33900	2	0	0
T3	7686	0	0	0
T6	15546	2	0	0
T7	0	2	0	0
T8	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T42	0	5	0	0
T44	0	1	0	0
T49	629	0	0	0
T74	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	447	0	0
T2	33900	2	0	0
T3	7686	0	0	0
T6	15546	2	0	0
T7	0	2	0	0
T8	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T42	0	3	0	0
T49	629	0	0	0
T74	0	1	0	0
T83	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	389	0	0
T2	33900	2	0	0
T3	7686	0	0	0
T6	15546	2	0	0
T7	0	2	0	0
T8	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T42	0	3	0	0
T49	629	0	0	0
T53	0	1	0	0
T74	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	389	0	0
T2	33900	2	0	0
T3	7686	0	0	0
T6	15546	2	0	0
T7	0	2	0	0
T8	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T42	0	3	0	0
T49	629	0	0	0
T53	0	1	0	0
T74	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	17288	0	0
T2	33900	146	0	0
T3	7686	0	0	0
T6	15546	534	0	0
T7	0	148	0	0
T8	0	94	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	105	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T42	0	153	0	0
T49	629	0	0	0
T53	0	3	0	0
T74	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	359	0	0
T2	33900	2	0	0
T3	7686	0	0	0
T6	15546	2	0	0
T7	0	2	0	0
T8	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T49	629	0	0	0
T53	0	1	0	0
T54	0	6	0	0
T74	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T6,T7,T12
1	1	Covered	T3,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T12,T43,T76
1	0	Covered	T6,T12,T42

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T41
0	1	Covered	T3,T7,T41
1	0	Covered	T90,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T41
1	-	Covered	T3,T7,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T7
DetectSt	168	Covered	T3,T6,T7
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T3,T7,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T7
DebounceSt->IdleSt	163	Covered	T39,T101,T256
DetectSt->IdleSt	186	Covered	T6,T12,T42
DetectSt->StableSt	191	Covered	T3,T7,T41
IdleSt->DebounceSt	148	Covered	T3,T6,T7
StableSt->IdleSt	206	Covered	T3,T7,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T3,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T101,T256
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T6,T12,T42
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T41
DetectSt	-	-	-	-	0	0	-	Covered	T3,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T41
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T41
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	3021	0	0
CntIncr_A	6649655	121140	0	0
CntNoWrap_A	6649655	5986414	0	0
DetectStDropOut_A	6649655	436	0	0
DetectedOut_A	6649655	71441	0	0
DetectedPulseOut_A	6649655	819	0	0
DisabledIdleSt_A	6649655	5508035	0	0
DisabledNoDetection_A	6649655	5510183	0	0
EnterDebounceSt_A	6649655	1527	0	0
EnterDetectSt_A	6649655	1494	0	0
EnterStableSt_A	6649655	819	0	0
PulseIsPulse_A	6649655	819	0	0
StayInStableSt	6649655	70534	0	0
gen_high_event_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_high_level_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_not_sticky_sva.StableStDropOut_A	6649655	728	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	3021	0	0
T3	7686	50	0	0
T6	15546	26	0	0
T7	0	50	0	0
T12	0	26	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T41	0	12	0	0
T42	0	18	0	0
T43	0	18	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	42	0	0
T76	0	30	0	0
T77	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	121140	0	0
T3	7686	1725	0	0
T6	15546	708	0	0
T7	0	1700	0	0
T12	0	739	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T41	0	336	0	0
T42	0	628	0	0
T43	0	464	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	903	0	0
T76	0	502	0	0
T77	0	243	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5986414	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7235	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	436	0	0
T12	7112	10	0	0
T26	490	0	0	0
T39	0	1	0	0
T42	18387	0	0	0
T43	5216	9	0	0
T69	525	0	0	0
T70	503	0	0	0
T76	0	15	0	0
T90	0	17	0	0
T99	0	11	0	0
T100	0	30	0	0
T101	0	2	0	0
T159	444	0	0	0
T260	0	11	0	0
T261	0	9	0	0
T262	434	0	0	0
T263	424	0	0	0
T264	742	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	71441	0	0
T3	7686	1452	0	0
T6	15546	0	0	0
T7	0	2428	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	364	0	0
T41	0	522	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	1775	0	0
T77	0	233	0	0
T97	0	1189	0	0
T98	0	2003	0	0
T243	0	1333	0	0
T257	0	1006	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	819	0	0
T3	7686	25	0	0
T6	15546	0	0	0
T7	0	25	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	5	0	0
T41	0	6	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	21	0	0
T77	0	3	0	0
T97	0	20	0	0
T98	0	29	0	0
T243	0	12	0	0
T257	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5508035	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	2015	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5510183	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	2015	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	1527	0	0
T3	7686	25	0	0
T6	15546	13	0	0
T7	0	25	0	0
T12	0	13	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T41	0	6	0	0
T42	0	9	0	0
T43	0	9	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	21	0	0
T76	0	15	0	0
T77	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	1494	0	0
T3	7686	25	0	0
T6	15546	13	0	0
T7	0	25	0	0
T12	0	13	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T41	0	6	0	0
T42	0	9	0	0
T43	0	9	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	21	0	0
T76	0	15	0	0
T77	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	819	0	0
T3	7686	25	0	0
T6	15546	0	0	0
T7	0	25	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	5	0	0
T41	0	6	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	21	0	0
T77	0	3	0	0
T97	0	20	0	0
T98	0	29	0	0
T243	0	12	0	0
T257	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	819	0	0
T3	7686	25	0	0
T6	15546	0	0	0
T7	0	25	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	5	0	0
T41	0	6	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	21	0	0
T77	0	3	0	0
T97	0	20	0	0
T98	0	29	0	0
T243	0	12	0	0
T257	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	70534	0	0
T3	7686	1427	0	0
T6	15546	0	0	0
T7	0	2397	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	359	0	0
T41	0	516	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	1753	0	0
T77	0	229	0	0
T97	0	1169	0	0
T98	0	1970	0	0
T243	0	1319	0	0
T257	0	988	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	728	0	0
T3	7686	25	0	0
T6	15546	0	0	0
T7	0	19	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	5	0	0
T41	0	6	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	20	0	0
T77	0	2	0	0
T97	0	20	0	0
T98	0	25	0	0
T243	0	10	0	0
T257	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T54,T91,T102
1	0	Covered	T39,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T7
1	-	Covered	T2,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T7
DetectSt	168	Covered	T2,T3,T7
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T7
DebounceSt->IdleSt	163	Covered	T3,T97,T84
DetectSt->IdleSt	186	Covered	T54,T39,T91
DetectSt->StableSt	191	Covered	T2,T3,T7
IdleSt->DebounceSt	148	Covered	T2,T3,T7
StableSt->IdleSt	206	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T97,T84
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T54,T39,T91
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	790	0	0
CntIncr_A	6649655	45135	0	0
CntNoWrap_A	6649655	5988645	0	0
DetectStDropOut_A	6649655	46	0	0
DetectedOut_A	6649655	13974	0	0
DetectedPulseOut_A	6649655	316	0	0
DisabledIdleSt_A	6649655	5623703	0	0
DisabledNoDetection_A	6649655	5625402	0	0
EnterDebounceSt_A	6649655	425	0	0
EnterDetectSt_A	6649655	367	0	0
EnterStableSt_A	6649655	316	0	0
PulseIsPulse_A	6649655	316	0	0
StayInStableSt	6649655	13635	0	0
gen_high_level_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_not_sticky_sva.StableStDropOut_A	6649655	292	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	790	0	0
T2	33900	22	0	0
T3	7686	3	0	0
T6	15546	0	0	0
T7	0	10	0	0
T8	0	6	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T39	0	8	0	0
T49	629	0	0	0
T54	0	4	0	0
T77	0	2	0	0
T84	0	31	0	0
T97	0	3	0	0
T98	0	9	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	45135	0	0
T2	33900	1870	0	0
T3	7686	118	0	0
T6	15546	0	0	0
T7	0	285	0	0
T8	0	297	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T39	0	217	0	0
T49	629	0	0	0
T54	0	256	0	0
T77	0	66	0	0
T84	0	2096	0	0
T97	0	105	0	0
T98	0	270	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5988645	0	0
T1	3384	979	0	0
T2	33900	33386	0	0
T3	7686	7282	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	46	0	0
T54	92404	2	0	0
T55	9609	0	0	0
T56	22307	0	0	0
T84	77582	0	0	0
T91	0	1	0	0
T92	522	0	0	0
T98	15435	0	0	0
T102	0	5	0	0
T104	0	4	0	0
T105	0	1	0	0
T108	0	2	0	0
T109	0	7	0	0
T194	672	0	0	0
T265	0	4	0	0
T266	0	3	0	0
T267	0	9	0	0
T268	8622	0	0	0
T269	665	0	0	0
T270	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	13974	0	0
T2	33900	215	0	0
T3	7686	43	0	0
T6	15546	0	0	0
T7	0	368	0	0
T8	0	155	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T39	0	78	0	0
T49	629	0	0	0
T77	0	40	0	0
T84	0	425	0	0
T97	0	50	0	0
T98	0	254	0	0
T271	0	261	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	316	0	0
T2	33900	11	0	0
T3	7686	1	0	0
T6	15546	0	0	0
T7	0	5	0	0
T8	0	3	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T39	0	1	0	0
T49	629	0	0	0
T77	0	1	0	0
T84	0	14	0	0
T97	0	1	0	0
T98	0	4	0	0
T271	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5623703	0	0
T1	3384	979	0	0
T2	33900	28203	0	0
T3	7686	5833	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5625402	0	0
T1	3384	984	0	0
T2	33900	28203	0	0
T3	7686	5834	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	425	0	0
T2	33900	11	0	0
T3	7686	2	0	0
T6	15546	0	0	0
T7	0	5	0	0
T8	0	3	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T39	0	5	0	0
T49	629	0	0	0
T54	0	2	0	0
T77	0	1	0	0
T84	0	17	0	0
T97	0	2	0	0
T98	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	367	0	0
T2	33900	11	0	0
T3	7686	1	0	0
T6	15546	0	0	0
T7	0	5	0	0
T8	0	3	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T39	0	3	0	0
T49	629	0	0	0
T54	0	2	0	0
T77	0	1	0	0
T84	0	14	0	0
T97	0	1	0	0
T98	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	316	0	0
T2	33900	11	0	0
T3	7686	1	0	0
T6	15546	0	0	0
T7	0	5	0	0
T8	0	3	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T39	0	1	0	0
T49	629	0	0	0
T77	0	1	0	0
T84	0	14	0	0
T97	0	1	0	0
T98	0	4	0	0
T271	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	316	0	0
T2	33900	11	0	0
T3	7686	1	0	0
T6	15546	0	0	0
T7	0	5	0	0
T8	0	3	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T39	0	1	0	0
T49	629	0	0	0
T77	0	1	0	0
T84	0	14	0	0
T97	0	1	0	0
T98	0	4	0	0
T271	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	13635	0	0
T2	33900	204	0	0
T3	7686	42	0	0
T6	15546	0	0	0
T7	0	363	0	0
T8	0	152	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T39	0	77	0	0
T49	629	0	0	0
T77	0	39	0	0
T84	0	411	0	0
T97	0	49	0	0
T98	0	246	0	0
T271	0	256	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	292	0	0
T2	33900	11	0	0
T3	7686	1	0	0
T6	15546	0	0	0
T7	0	5	0	0
T8	0	3	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T39	0	1	0	0
T49	629	0	0	0
T77	0	1	0	0
T84	0	14	0	0
T97	0	1	0	0
T271	0	5	0	0
T272	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T12,T43
1	0	Covered	T3,T12,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T42
0	1	Covered	T6,T7,T42
1	0	Covered	T89,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T42
1	-	Covered	T6,T7,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T7
DetectSt	168	Covered	T3,T6,T7
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T6,T7,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T7
DebounceSt->IdleSt	163	Covered	T39,T101,T256
DetectSt->IdleSt	186	Covered	T3,T12,T43
DetectSt->StableSt	191	Covered	T6,T7,T42
IdleSt->DebounceSt	148	Covered	T3,T6,T7
StableSt->IdleSt	206	Covered	T6,T7,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T3,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T101,T256
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T3,T12,T43
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T42
DetectSt	-	-	-	-	0	0	-	Covered	T3,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T6,T7,T42
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T42
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	3298	0	0
CntIncr_A	6649655	120525	0	0
CntNoWrap_A	6649655	5986137	0	0
DetectStDropOut_A	6649655	482	0	0
DetectedOut_A	6649655	86175	0	0
DetectedPulseOut_A	6649655	952	0	0
DisabledIdleSt_A	6649655	5494324	0	0
DisabledNoDetection_A	6649655	5496442	0	0
EnterDebounceSt_A	6649655	1670	0	0
EnterDetectSt_A	6649655	1629	0	0
EnterStableSt_A	6649655	952	0	0
PulseIsPulse_A	6649655	952	0	0
StayInStableSt	6649655	85105	0	0
gen_high_event_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_high_level_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_not_sticky_sva.StableStDropOut_A	6649655	806	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	3298	0	0
T3	7686	60	0	0
T6	15546	46	0	0
T7	0	14	0	0
T12	0	48	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T41	0	54	0	0
T42	0	50	0	0
T43	0	50	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	8	0	0
T76	0	26	0	0
T77	0	44	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	120525	0	0
T3	7686	2269	0	0
T6	15546	1150	0	0
T7	0	462	0	0
T12	0	1381	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T41	0	2079	0	0
T42	0	1225	0	0
T43	0	1302	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	229	0	0
T76	0	438	0	0
T77	0	1210	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5986137	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7225	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	482	0	0
T3	7686	10	0	0
T6	15546	0	0	0
T12	0	18	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	1	0	0
T43	0	25	0	0
T49	629	0	0	0
T50	424	0	0	0
T76	0	13	0	0
T97	0	9	0	0
T98	0	4	0	0
T99	0	14	0	0
T100	0	2	0	0
T101	0	23	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	86175	0	0
T6	15546	2928	0	0
T7	23533	418	0	0
T8	32789	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	403	0	0
T41	0	2076	0	0
T42	0	2495	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T77	0	2383	0	0
T243	0	1933	0	0
T257	0	978	0	0
T260	0	703	0	0
T268	0	2058	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	952	0	0
T6	15546	23	0	0
T7	23533	7	0	0
T8	32789	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	5	0	0
T41	0	27	0	0
T42	0	25	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T77	0	22	0	0
T243	0	29	0	0
T257	0	14	0	0
T260	0	17	0	0
T268	0	28	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5494324	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	3331	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5496442	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	3331	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	1670	0	0
T3	7686	30	0	0
T6	15546	23	0	0
T7	0	7	0	0
T12	0	24	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T41	0	27	0	0
T42	0	25	0	0
T43	0	25	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	4	0	0
T76	0	13	0	0
T77	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	1629	0	0
T3	7686	30	0	0
T6	15546	23	0	0
T7	0	7	0	0
T12	0	24	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T41	0	27	0	0
T42	0	25	0	0
T43	0	25	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	4	0	0
T76	0	13	0	0
T77	0	22	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	952	0	0
T6	15546	23	0	0
T7	23533	7	0	0
T8	32789	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	5	0	0
T41	0	27	0	0
T42	0	25	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T77	0	22	0	0
T243	0	29	0	0
T257	0	14	0	0
T260	0	17	0	0
T268	0	28	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	952	0	0
T6	15546	23	0	0
T7	23533	7	0	0
T8	32789	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	5	0	0
T41	0	27	0	0
T42	0	25	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T77	0	22	0	0
T243	0	29	0	0
T257	0	14	0	0
T260	0	17	0	0
T268	0	28	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	85105	0	0
T6	15546	2902	0	0
T7	23533	410	0	0
T8	32789	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	398	0	0
T41	0	2046	0	0
T42	0	2466	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T77	0	2355	0	0
T243	0	1900	0	0
T257	0	960	0	0
T260	0	684	0	0
T268	0	2029	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	806	0	0
T6	15546	20	0	0
T7	23533	6	0	0
T8	32789	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	5	0	0
T41	0	24	0	0
T42	0	21	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T77	0	16	0	0
T243	0	25	0	0
T257	0	10	0	0
T260	0	15	0	0
T268	0	27	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T84,T102,T273
1	0	Covered	T39,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
1	0	Covered	T39,T85,T274

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T7
1	-	Covered	T2,T6,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T7
DetectSt	168	Covered	T2,T6,T7
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T6,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T7
DebounceSt->IdleSt	163	Covered	T6,T83,T268
DetectSt->IdleSt	186	Covered	T84,T39,T102
DetectSt->StableSt	191	Covered	T2,T6,T7
IdleSt->DebounceSt	148	Covered	T2,T6,T7
StableSt->IdleSt	206	Covered	T2,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T83,T268
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T84,T39,T102
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T7
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T7
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	831	0	0
CntIncr_A	6649655	48895	0	0
CntNoWrap_A	6649655	5988604	0	0
DetectStDropOut_A	6649655	53	0	0
DetectedOut_A	6649655	16666	0	0
DetectedPulseOut_A	6649655	335	0	0
DisabledIdleSt_A	6649655	5629346	0	0
DisabledNoDetection_A	6649655	5631055	0	0
EnterDebounceSt_A	6649655	439	0	0
EnterDetectSt_A	6649655	392	0	0
EnterStableSt_A	6649655	335	0	0
PulseIsPulse_A	6649655	335	0	0
StayInStableSt	6649655	16306	0	0
gen_high_level_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_not_sticky_sva.StableStDropOut_A	6649655	307	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	831	0	0
T2	33900	6	0	0
T3	7686	0	0	0
T6	15546	7	0	0
T7	0	2	0	0
T8	0	26	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T35	0	4	0	0
T41	0	4	0	0
T42	0	2	0	0
T49	629	0	0	0
T54	0	6	0	0
T77	0	12	0	0
T83	0	19	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	48895	0	0
T2	33900	495	0	0
T3	7686	0	0	0
T6	15546	182	0	0
T7	0	61	0	0
T8	0	1170	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T35	0	264	0	0
T41	0	144	0	0
T42	0	63	0	0
T49	629	0	0	0
T54	0	216	0	0
T77	0	444	0	0
T83	0	810	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5988604	0	0
T1	3384	979	0	0
T2	33900	33402	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	53	0	0
T39	7361	0	0	0
T56	22307	0	0	0
T84	77582	3	0	0
T92	522	0	0	0
T98	15435	0	0	0
T102	0	6	0	0
T105	0	7	0	0
T194	672	0	0	0
T195	529	0	0	0
T196	445	0	0	0
T235	0	6	0	0
T269	665	0	0	0
T270	404	0	0	0
T273	0	1	0	0
T275	0	1	0	0
T276	0	3	0	0
T277	0	2	0	0
T278	0	6	0	0
T279	0	15	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	16666	0	0
T2	33900	73	0	0
T3	7686	0	0	0
T6	15546	750	0	0
T7	0	70	0	0
T8	0	795	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T35	0	19	0	0
T41	0	116	0	0
T42	0	72	0	0
T49	629	0	0	0
T54	0	169	0	0
T77	0	189	0	0
T83	0	381	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	335	0	0
T2	33900	3	0	0
T3	7686	0	0	0
T6	15546	3	0	0
T7	0	1	0	0
T8	0	13	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T35	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T49	629	0	0	0
T54	0	3	0	0
T77	0	6	0	0
T83	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5629346	0	0
T1	3384	979	0	0
T2	33900	28203	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5631055	0	0
T1	3384	984	0	0
T2	33900	28203	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	439	0	0
T2	33900	3	0	0
T3	7686	0	0	0
T6	15546	4	0	0
T7	0	1	0	0
T8	0	13	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T35	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T49	629	0	0	0
T54	0	3	0	0
T77	0	6	0	0
T83	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	392	0	0
T2	33900	3	0	0
T3	7686	0	0	0
T6	15546	3	0	0
T7	0	1	0	0
T8	0	13	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T35	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T49	629	0	0	0
T54	0	3	0	0
T77	0	6	0	0
T83	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	335	0	0
T2	33900	3	0	0
T3	7686	0	0	0
T6	15546	3	0	0
T7	0	1	0	0
T8	0	13	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T35	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T49	629	0	0	0
T54	0	3	0	0
T77	0	6	0	0
T83	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	335	0	0
T2	33900	3	0	0
T3	7686	0	0	0
T6	15546	3	0	0
T7	0	1	0	0
T8	0	13	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T35	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T49	629	0	0	0
T54	0	3	0	0
T77	0	6	0	0
T83	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	16306	0	0
T2	33900	70	0	0
T3	7686	0	0	0
T6	15546	746	0	0
T7	0	69	0	0
T8	0	782	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T35	0	17	0	0
T41	0	112	0	0
T42	0	71	0	0
T49	629	0	0	0
T54	0	166	0	0
T77	0	178	0	0
T83	0	372	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	307	0	0
T2	33900	3	0	0
T3	7686	0	0	0
T6	15546	2	0	0
T7	0	1	0	0
T8	0	13	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T35	0	2	0	0
T42	0	1	0	0
T49	629	0	0	0
T54	0	3	0	0
T77	0	1	0	0
T83	0	9	0	0
T84	0	5	0	0