Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T7,T12
1	0	Covered	T3,T7,T12

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T42,T41
0	1	Covered	T6,T42,T41
1	0	Covered	T280,T281

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T42,T41
1	-	Covered	T6,T42,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T7
DetectSt	168	Covered	T3,T6,T7
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T6,T42,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T7
DebounceSt->IdleSt	163	Covered	T39,T101,T256
DetectSt->IdleSt	186	Covered	T3,T7,T12
DetectSt->StableSt	191	Covered	T6,T42,T41
IdleSt->DebounceSt	148	Covered	T3,T6,T7
StableSt->IdleSt	206	Covered	T6,T42,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T3,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T101,T256
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T3,T7,T12
DetectSt	-	-	-	-	0	1	-	Covered	T6,T42,T41
DetectSt	-	-	-	-	0	0	-	Covered	T3,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T6,T42,T41
StableSt	-	-	-	-	-	-	0	Covered	T6,T42,T41
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	2837	0	0
CntIncr_A	6649655	108758	0	0
CntNoWrap_A	6649655	5986598	0	0
DetectStDropOut_A	6649655	379	0	0
DetectedOut_A	6649655	76692	0	0
DetectedPulseOut_A	6649655	787	0	0
DisabledIdleSt_A	6649655	5504183	0	0
DisabledNoDetection_A	6649655	5506339	0	0
EnterDebounceSt_A	6649655	1438	0	0
EnterDetectSt_A	6649655	1401	0	0
EnterStableSt_A	6649655	787	0	0
PulseIsPulse_A	6649655	787	0	0
StayInStableSt	6649655	75825	0	0
gen_high_event_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_high_level_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_not_sticky_sva.StableStDropOut_A	6649655	690	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	2837	0	0
T3	7686	30	0	0
T6	15546	64	0	0
T7	0	46	0	0
T12	0	32	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T41	0	54	0	0
T42	0	32	0	0
T43	0	18	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	48	0	0
T76	0	69	0	0
T77	0	62	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	108758	0	0
T3	7686	1129	0	0
T6	15546	1248	0	0
T7	0	1937	0	0
T12	0	908	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T41	0	1809	0	0
T42	0	816	0	0
T43	0	463	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	1248	0	0
T76	0	1195	0	0
T77	0	2515	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5986598	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	7255	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	379	0	0
T3	7686	6	0	0
T6	15546	0	0	0
T7	0	7	0	0
T12	0	14	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T43	0	9	0	0
T49	629	0	0	0
T50	424	0	0	0
T76	0	34	0	0
T77	0	18	0	0
T99	0	11	0	0
T100	0	20	0	0
T101	0	8	0	0
T261	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	76692	0	0
T6	15546	2729	0	0
T7	23533	0	0	0
T8	32789	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	378	0	0
T41	0	2346	0	0
T42	0	615	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T75	0	705	0	0
T97	0	1355	0	0
T258	0	674	0	0
T260	0	919	0	0
T268	0	1383	0	0
T282	0	433	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	787	0	0
T6	15546	32	0	0
T7	23533	0	0	0
T8	32789	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	5	0	0
T41	0	27	0	0
T42	0	16	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T75	0	24	0	0
T97	0	14	0	0
T258	0	15	0	0
T260	0	12	0	0
T268	0	24	0	0
T282	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5504183	0	0
T1	3384	979	0	0
T2	33900	33408	0	0
T3	7686	3331	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5506339	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	3331	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	1438	0	0
T3	7686	15	0	0
T6	15546	32	0	0
T7	0	23	0	0
T12	0	16	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T41	0	27	0	0
T42	0	16	0	0
T43	0	9	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	24	0	0
T76	0	35	0	0
T77	0	31	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	1401	0	0
T3	7686	15	0	0
T6	15546	32	0	0
T7	0	23	0	0
T12	0	16	0	0
T16	504	0	0	0
T17	449	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T41	0	27	0	0
T42	0	16	0	0
T43	0	9	0	0
T49	629	0	0	0
T50	424	0	0	0
T75	0	24	0	0
T76	0	35	0	0
T77	0	31	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	787	0	0
T6	15546	32	0	0
T7	23533	0	0	0
T8	32789	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	5	0	0
T41	0	27	0	0
T42	0	16	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T75	0	24	0	0
T97	0	14	0	0
T258	0	15	0	0
T260	0	12	0	0
T268	0	24	0	0
T282	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	787	0	0
T6	15546	32	0	0
T7	23533	0	0	0
T8	32789	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	5	0	0
T41	0	27	0	0
T42	0	16	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T75	0	24	0	0
T97	0	14	0	0
T258	0	15	0	0
T260	0	12	0	0
T268	0	24	0	0
T282	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	75825	0	0
T6	15546	2696	0	0
T7	23533	0	0	0
T8	32789	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	373	0	0
T41	0	2316	0	0
T42	0	597	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T75	0	679	0	0
T97	0	1341	0	0
T258	0	658	0	0
T260	0	907	0	0
T268	0	1358	0	0
T282	0	410	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	690	0	0
T6	15546	31	0	0
T7	23533	0	0	0
T8	32789	0	0	0
T25	494	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T29	727	0	0	0
T39	0	5	0	0
T41	0	24	0	0
T42	0	14	0	0
T49	629	0	0	0
T50	424	0	0	0
T51	833	0	0	0
T75	0	22	0	0
T97	0	14	0	0
T258	0	14	0	0
T260	0	12	0	0
T268	0	23	0	0
T282	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Covered	T271,T265,T283
1	0	Covered	T39,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Covered	T2,T6,T8
1	0	Covered	T39,T86,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T8
1	-	Covered	T2,T6,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T8
DetectSt	168	Covered	T2,T6,T8
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T6,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T8
DebounceSt->IdleSt	163	Covered	T8,T83,T39
DetectSt->IdleSt	186	Covered	T39,T271,T265
DetectSt->StableSt	191	Covered	T2,T6,T8
IdleSt->DebounceSt	148	Covered	T2,T6,T8
StableSt->IdleSt	206	Covered	T2,T6,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T8
0	1	Covered	T2,T6,T8
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T83,T102
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T8
DetectSt	-	-	-	-	1	-	-	Covered	T39,T271,T265
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T8
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T8
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T8
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6649655	762	0	0
CntIncr_A	6649655	45411	0	0
CntNoWrap_A	6649655	5988673	0	0
DetectStDropOut_A	6649655	45	0	0
DetectedOut_A	6649655	17120	0	0
DetectedPulseOut_A	6649655	315	0	0
DisabledIdleSt_A	6649655	5625220	0	0
DisabledNoDetection_A	6649655	5626939	0	0
EnterDebounceSt_A	6649655	398	0	0
EnterDetectSt_A	6649655	364	0	0
EnterStableSt_A	6649655	315	0	0
PulseIsPulse_A	6649655	315	0	0
StayInStableSt	6649655	16780	0	0
gen_high_level_sva.HighLevelEvent_A	6649655	5991763	0	0
gen_not_sticky_sva.StableStDropOut_A	6649655	281	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	762	0	0
T2	33900	12	0	0
T3	7686	0	0	0
T6	15546	2	0	0
T8	0	13	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T49	629	0	0	0
T54	0	4	0	0
T55	0	2	0	0
T75	0	4	0	0
T83	0	17	0	0
T97	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	45411	0	0
T2	33900	750	0	0
T3	7686	0	0	0
T6	15546	39	0	0
T8	0	838	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T41	0	60	0	0
T42	0	47	0	0
T49	629	0	0	0
T54	0	182	0	0
T55	0	160	0	0
T75	0	160	0	0
T83	0	776	0	0
T97	0	390	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5988673	0	0
T1	3384	979	0	0
T2	33900	33396	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	45	0	0
T80	862	0	0	0
T91	19197	0	0	0
T100	5468	0	0	0
T101	5070	0	0	0
T109	0	2	0	0
T146	655	0	0	0
T250	1117	0	0	0
T265	0	2	0	0
T266	0	4	0	0
T271	24986	4	0	0
T272	7149	0	0	0
T283	0	4	0	0
T284	0	11	0	0
T285	0	4	0	0
T286	0	2	0	0
T287	0	5	0	0
T288	0	1	0	0
T289	556	0	0	0
T290	733	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	17120	0	0
T2	33900	388	0	0
T3	7686	0	0	0
T6	15546	264	0	0
T8	0	142	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T41	0	71	0	0
T42	0	87	0	0
T49	629	0	0	0
T54	0	75	0	0
T55	0	16	0	0
T75	0	91	0	0
T83	0	289	0	0
T97	0	319	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	315	0	0
T2	33900	6	0	0
T3	7686	0	0	0
T6	15546	1	0	0
T8	0	6	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T49	629	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T75	0	2	0	0
T83	0	8	0	0
T97	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5625220	0	0
T1	3384	979	0	0
T2	33900	28203	0	0
T3	7686	7285	0	0
T4	503	102	0	0
T5	502	101	0	0
T13	422	21	0	0
T14	426	25	0	0
T15	427	26	0	0
T16	504	103	0	0
T17	449	48	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5626939	0	0
T1	3384	984	0	0
T2	33900	28203	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	398	0	0
T2	33900	6	0	0
T3	7686	0	0	0
T6	15546	1	0	0
T8	0	7	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T49	629	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T75	0	2	0	0
T83	0	9	0	0
T97	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	364	0	0
T2	33900	6	0	0
T3	7686	0	0	0
T6	15546	1	0	0
T8	0	6	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T49	629	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T75	0	2	0	0
T83	0	8	0	0
T97	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	315	0	0
T2	33900	6	0	0
T3	7686	0	0	0
T6	15546	1	0	0
T8	0	6	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T49	629	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T75	0	2	0	0
T83	0	8	0	0
T97	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	315	0	0
T2	33900	6	0	0
T3	7686	0	0	0
T6	15546	1	0	0
T8	0	6	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T49	629	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T75	0	2	0	0
T83	0	8	0	0
T97	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	16780	0	0
T2	33900	382	0	0
T3	7686	0	0	0
T6	15546	263	0	0
T8	0	136	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T41	0	70	0	0
T42	0	85	0	0
T49	629	0	0	0
T54	0	73	0	0
T55	0	15	0	0
T75	0	87	0	0
T83	0	281	0	0
T97	0	313	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	5991763	0	0
T1	3384	984	0	0
T2	33900	33422	0	0
T3	7686	7286	0	0
T4	503	103	0	0
T5	502	102	0	0
T13	422	22	0	0
T14	426	26	0	0
T15	427	27	0	0
T16	504	104	0	0
T17	449	49	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6649655	281	0	0
T2	33900	6	0	0
T3	7686	0	0	0
T6	15546	1	0	0
T8	0	6	0	0
T14	426	0	0	0
T15	427	0	0	0
T16	504	0	0	0
T17	449	0	0	0
T27	667	0	0	0
T28	594	0	0	0
T41	0	1	0	0
T49	629	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T83	0	8	0	0
T84	0	8	0	0
T91	0	1	0	0
T97	0	6	0	0