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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.09 99.42 96.83 100.00 98.08 98.89 99.71 93.73


Total test records in report: 907
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T789 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2047702033 Jul 11 04:28:03 PM PDT 24 Jul 11 04:28:06 PM PDT 24 2044367125 ps
T790 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.4047691658 Jul 11 04:28:22 PM PDT 24 Jul 11 04:28:25 PM PDT 24 2050815890 ps
T18 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.260599744 Jul 11 04:28:10 PM PDT 24 Jul 11 04:28:53 PM PDT 24 8132047508 ps
T19 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1183112742 Jul 11 04:28:10 PM PDT 24 Jul 11 04:28:18 PM PDT 24 7684229988 ps
T357 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1571886734 Jul 11 04:27:02 PM PDT 24 Jul 11 04:27:10 PM PDT 24 2053654623 ps
T295 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1773515387 Jul 11 04:27:34 PM PDT 24 Jul 11 04:28:33 PM PDT 24 42546759508 ps
T370 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3079272647 Jul 11 04:28:07 PM PDT 24 Jul 11 04:28:10 PM PDT 24 2067719718 ps
T791 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.4015957731 Jul 11 04:28:26 PM PDT 24 Jul 11 04:28:34 PM PDT 24 2012949224 ps
T371 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.212942088 Jul 11 04:27:28 PM PDT 24 Jul 11 04:27:32 PM PDT 24 4063707264 ps
T792 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.3651246033 Jul 11 04:27:56 PM PDT 24 Jul 11 04:27:58 PM PDT 24 2063987026 ps
T291 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3364716910 Jul 11 04:29:08 PM PDT 24 Jul 11 04:29:16 PM PDT 24 2208115394 ps
T358 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2904016571 Jul 11 04:29:07 PM PDT 24 Jul 11 04:29:12 PM PDT 24 2174607278 ps
T292 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3550321272 Jul 11 04:28:25 PM PDT 24 Jul 11 04:28:38 PM PDT 24 45386136430 ps
T793 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2582673052 Jul 11 04:28:29 PM PDT 24 Jul 11 04:28:37 PM PDT 24 2013002836 ps
T794 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.4119658726 Jul 11 04:27:03 PM PDT 24 Jul 11 04:27:11 PM PDT 24 2009519238 ps
T795 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.757718773 Jul 11 04:28:38 PM PDT 24 Jul 11 04:28:40 PM PDT 24 2083648956 ps
T359 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.4230147365 Jul 11 04:28:12 PM PDT 24 Jul 11 04:28:21 PM PDT 24 2274201808 ps
T309 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3268083565 Jul 11 04:27:34 PM PDT 24 Jul 11 04:28:07 PM PDT 24 42906783905 ps
T796 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1243045923 Jul 11 04:28:25 PM PDT 24 Jul 11 04:28:29 PM PDT 24 2025199768 ps
T797 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.122726759 Jul 11 04:28:11 PM PDT 24 Jul 11 04:28:18 PM PDT 24 2016649851 ps
T798 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2413633565 Jul 11 04:29:21 PM PDT 24 Jul 11 04:29:30 PM PDT 24 2012178787 ps
T799 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1224356255 Jul 11 04:27:19 PM PDT 24 Jul 11 04:27:30 PM PDT 24 2682559395 ps
T20 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3435873573 Jul 11 04:27:34 PM PDT 24 Jul 11 04:27:43 PM PDT 24 2053348275 ps
T800 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.4031135290 Jul 11 04:28:04 PM PDT 24 Jul 11 04:28:11 PM PDT 24 2012288398 ps
T303 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.510473171 Jul 11 04:28:24 PM PDT 24 Jul 11 04:30:26 PM PDT 24 42428402127 ps
T801 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.659905431 Jul 11 04:28:38 PM PDT 24 Jul 11 04:28:41 PM PDT 24 2040978074 ps
T306 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1165366999 Jul 11 04:28:16 PM PDT 24 Jul 11 04:28:20 PM PDT 24 2261633270 ps
T802 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3055356422 Jul 11 04:28:19 PM PDT 24 Jul 11 04:28:23 PM PDT 24 2047815643 ps
T803 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1928166009 Jul 11 04:28:17 PM PDT 24 Jul 11 04:28:25 PM PDT 24 2013581632 ps
T296 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.3342985280 Jul 11 04:28:09 PM PDT 24 Jul 11 04:28:17 PM PDT 24 2077895920 ps
T297 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.157243212 Jul 11 04:27:32 PM PDT 24 Jul 11 04:27:39 PM PDT 24 2264012018 ps
T804 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3267490903 Jul 11 04:28:08 PM PDT 24 Jul 11 04:28:15 PM PDT 24 2067064777 ps
T305 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3650366072 Jul 11 04:28:07 PM PDT 24 Jul 11 04:28:25 PM PDT 24 22274045626 ps
T313 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1571833986 Jul 11 04:27:03 PM PDT 24 Jul 11 04:27:08 PM PDT 24 2101455151 ps
T805 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.1116065326 Jul 11 04:27:10 PM PDT 24 Jul 11 04:27:23 PM PDT 24 7976949882 ps
T360 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3448067596 Jul 11 04:28:07 PM PDT 24 Jul 11 04:28:10 PM PDT 24 2116836865 ps
T361 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3899887649 Jul 11 04:28:33 PM PDT 24 Jul 11 04:28:36 PM PDT 24 2114439842 ps
T308 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3093617996 Jul 11 04:28:07 PM PDT 24 Jul 11 04:28:12 PM PDT 24 2139130968 ps
T806 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1359954663 Jul 11 04:27:30 PM PDT 24 Jul 11 04:27:34 PM PDT 24 9531308912 ps
T807 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2384043033 Jul 11 04:27:10 PM PDT 24 Jul 11 04:27:23 PM PDT 24 4033878092 ps
T808 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3010940265 Jul 11 04:28:06 PM PDT 24 Jul 11 04:28:10 PM PDT 24 2106737445 ps
T362 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2548208716 Jul 11 04:27:34 PM PDT 24 Jul 11 04:27:41 PM PDT 24 2045460844 ps
T809 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2178974041 Jul 11 04:28:15 PM PDT 24 Jul 11 04:28:38 PM PDT 24 8034475254 ps
T810 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.187948011 Jul 11 04:28:25 PM PDT 24 Jul 11 04:28:33 PM PDT 24 2012594275 ps
T811 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.3946352708 Jul 11 04:28:09 PM PDT 24 Jul 11 04:28:11 PM PDT 24 2049039886 ps
T812 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.119476508 Jul 11 04:28:08 PM PDT 24 Jul 11 04:28:11 PM PDT 24 4955536533 ps
T813 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.1043838829 Jul 11 04:27:19 PM PDT 24 Jul 11 04:28:23 PM PDT 24 22253730157 ps
T312 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3877784891 Jul 11 04:28:05 PM PDT 24 Jul 11 04:28:13 PM PDT 24 2116197426 ps
T814 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.1601069509 Jul 11 04:27:36 PM PDT 24 Jul 11 04:28:35 PM PDT 24 22224715457 ps
T815 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1052689713 Jul 11 04:27:36 PM PDT 24 Jul 11 04:27:43 PM PDT 24 4047654497 ps
T816 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.467492827 Jul 11 04:27:33 PM PDT 24 Jul 11 04:28:20 PM PDT 24 39194704896 ps
T817 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2568709806 Jul 11 04:28:13 PM PDT 24 Jul 11 04:28:15 PM PDT 24 2044027799 ps
T818 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1126989647 Jul 11 04:28:30 PM PDT 24 Jul 11 04:28:34 PM PDT 24 2030632173 ps
T819 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2180810510 Jul 11 04:27:31 PM PDT 24 Jul 11 04:27:37 PM PDT 24 2012604524 ps
T363 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1047810982 Jul 11 04:27:10 PM PDT 24 Jul 11 04:27:21 PM PDT 24 7574461279 ps
T820 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.2246319138 Jul 11 04:27:11 PM PDT 24 Jul 11 04:27:19 PM PDT 24 2016997854 ps
T821 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2679505563 Jul 11 04:28:16 PM PDT 24 Jul 11 04:28:26 PM PDT 24 4795522527 ps
T822 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.559152362 Jul 11 04:28:10 PM PDT 24 Jul 11 04:28:15 PM PDT 24 2107289195 ps
T823 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.4051954146 Jul 11 04:27:34 PM PDT 24 Jul 11 04:27:44 PM PDT 24 2058301301 ps
T302 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.4178465802 Jul 11 04:28:17 PM PDT 24 Jul 11 04:30:16 PM PDT 24 42453250416 ps
T310 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1230659102 Jul 11 04:27:08 PM PDT 24 Jul 11 04:28:04 PM PDT 24 42610172716 ps
T311 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2165057253 Jul 11 04:28:16 PM PDT 24 Jul 11 04:28:23 PM PDT 24 2170788005 ps
T304 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.128767071 Jul 11 04:27:16 PM PDT 24 Jul 11 04:27:47 PM PDT 24 22283275383 ps
T299 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2853318964 Jul 11 04:28:00 PM PDT 24 Jul 11 04:28:06 PM PDT 24 2422935084 ps
T300 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1689948737 Jul 11 04:28:11 PM PDT 24 Jul 11 04:28:18 PM PDT 24 2083010412 ps
T367 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1206589356 Jul 11 04:28:16 PM PDT 24 Jul 11 04:28:23 PM PDT 24 2068120823 ps
T364 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3546914238 Jul 11 04:28:20 PM PDT 24 Jul 11 04:28:24 PM PDT 24 2074278895 ps
T824 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1893484324 Jul 11 04:27:20 PM PDT 24 Jul 11 04:27:42 PM PDT 24 5436758482 ps
T301 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.4102614177 Jul 11 04:27:13 PM PDT 24 Jul 11 04:27:19 PM PDT 24 2608657836 ps
T825 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.814308679 Jul 11 04:28:17 PM PDT 24 Jul 11 04:28:23 PM PDT 24 2170468641 ps
T365 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3023648236 Jul 11 04:27:13 PM PDT 24 Jul 11 04:27:26 PM PDT 24 2790744888 ps
T826 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3912910694 Jul 11 04:28:19 PM PDT 24 Jul 11 04:28:27 PM PDT 24 2060531239 ps
T827 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.3378219656 Jul 11 04:28:11 PM PDT 24 Jul 11 04:28:41 PM PDT 24 22283652107 ps
T828 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1639234799 Jul 11 04:28:16 PM PDT 24 Jul 11 04:28:21 PM PDT 24 2015595305 ps
T829 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.396548218 Jul 11 04:27:15 PM PDT 24 Jul 11 04:27:19 PM PDT 24 3354245732 ps
T830 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3446361052 Jul 11 04:27:55 PM PDT 24 Jul 11 04:28:28 PM PDT 24 42496966693 ps
T831 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1418825014 Jul 11 04:28:24 PM PDT 24 Jul 11 04:28:37 PM PDT 24 5341690468 ps
T832 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.4176529269 Jul 11 04:28:26 PM PDT 24 Jul 11 04:29:05 PM PDT 24 9161681098 ps
T307 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2412861036 Jul 11 04:27:59 PM PDT 24 Jul 11 04:28:04 PM PDT 24 2496415763 ps
T833 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3523013740 Jul 11 04:27:10 PM PDT 24 Jul 11 04:27:13 PM PDT 24 2247337693 ps
T834 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2844129234 Jul 11 04:28:09 PM PDT 24 Jul 11 04:28:26 PM PDT 24 22269816741 ps
T835 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3502771209 Jul 11 04:27:52 PM PDT 24 Jul 11 04:28:02 PM PDT 24 8615116046 ps
T836 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3870413561 Jul 11 04:28:11 PM PDT 24 Jul 11 04:28:16 PM PDT 24 2259455561 ps
T366 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1450153186 Jul 11 04:29:32 PM PDT 24 Jul 11 04:29:36 PM PDT 24 2066602049 ps
T837 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.2753416404 Jul 11 04:27:33 PM PDT 24 Jul 11 04:27:41 PM PDT 24 2035079288 ps
T838 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1997085596 Jul 11 04:28:35 PM PDT 24 Jul 11 04:28:40 PM PDT 24 2022603144 ps
T314 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3058073589 Jul 11 04:27:33 PM PDT 24 Jul 11 04:27:40 PM PDT 24 2458488338 ps
T839 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1317901068 Jul 11 04:28:03 PM PDT 24 Jul 11 04:28:06 PM PDT 24 2068844329 ps
T840 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1842885150 Jul 11 04:28:27 PM PDT 24 Jul 11 04:30:15 PM PDT 24 42404004962 ps
T841 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.517976516 Jul 11 04:28:05 PM PDT 24 Jul 11 04:28:10 PM PDT 24 2313886318 ps
T842 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.977912635 Jul 11 04:28:14 PM PDT 24 Jul 11 04:28:20 PM PDT 24 2149805552 ps
T843 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2737488616 Jul 11 04:28:26 PM PDT 24 Jul 11 04:28:34 PM PDT 24 2014771212 ps
T844 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3247880259 Jul 11 04:28:22 PM PDT 24 Jul 11 04:28:26 PM PDT 24 2036244759 ps
T845 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.3921070513 Jul 11 04:27:26 PM PDT 24 Jul 11 04:28:57 PM PDT 24 39992162771 ps
T846 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.754690684 Jul 11 04:29:30 PM PDT 24 Jul 11 04:29:33 PM PDT 24 2048567088 ps
T847 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1241189302 Jul 11 04:28:22 PM PDT 24 Jul 11 04:28:29 PM PDT 24 9913334764 ps
T848 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.503161026 Jul 11 04:27:59 PM PDT 24 Jul 11 04:28:05 PM PDT 24 9427611925 ps
T849 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.360922144 Jul 11 04:29:32 PM PDT 24 Jul 11 04:29:39 PM PDT 24 7987603045 ps
T850 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.133020134 Jul 11 04:27:58 PM PDT 24 Jul 11 04:29:53 PM PDT 24 42482852337 ps
T368 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3002623427 Jul 11 04:28:19 PM PDT 24 Jul 11 04:28:23 PM PDT 24 2102253966 ps
T851 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.185585121 Jul 11 04:27:57 PM PDT 24 Jul 11 04:28:00 PM PDT 24 2223179443 ps
T852 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1928669076 Jul 11 04:28:27 PM PDT 24 Jul 11 04:28:35 PM PDT 24 2013072618 ps
T853 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1830408052 Jul 11 04:27:10 PM PDT 24 Jul 11 04:27:15 PM PDT 24 2193961227 ps
T854 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.2385490886 Jul 11 04:29:28 PM PDT 24 Jul 11 04:29:55 PM PDT 24 9359587867 ps
T855 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2130720409 Jul 11 04:28:20 PM PDT 24 Jul 11 04:28:25 PM PDT 24 2118684849 ps
T856 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.4044361757 Jul 11 04:28:13 PM PDT 24 Jul 11 04:29:37 PM PDT 24 42387764744 ps
T857 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.1596598839 Jul 11 04:28:23 PM PDT 24 Jul 11 04:28:31 PM PDT 24 2016117330 ps
T858 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.4085116023 Jul 11 04:27:38 PM PDT 24 Jul 11 04:30:37 PM PDT 24 34479936560 ps
T859 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2103894550 Jul 11 04:28:07 PM PDT 24 Jul 11 04:28:12 PM PDT 24 2171874960 ps
T860 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.2170028752 Jul 11 04:28:09 PM PDT 24 Jul 11 04:28:17 PM PDT 24 2072730332 ps
T861 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.558543129 Jul 11 04:29:28 PM PDT 24 Jul 11 04:29:33 PM PDT 24 2076295700 ps
T862 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2948179856 Jul 11 04:28:18 PM PDT 24 Jul 11 04:28:22 PM PDT 24 2215963693 ps
T863 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.4229422530 Jul 11 04:28:23 PM PDT 24 Jul 11 04:28:45 PM PDT 24 22514214320 ps
T864 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2685463872 Jul 11 04:28:14 PM PDT 24 Jul 11 04:28:16 PM PDT 24 2077317096 ps
T865 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1496404936 Jul 11 04:27:29 PM PDT 24 Jul 11 04:27:32 PM PDT 24 2176537570 ps
T866 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3431104633 Jul 11 04:28:11 PM PDT 24 Jul 11 04:28:13 PM PDT 24 2082369238 ps
T867 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3393766509 Jul 11 04:28:24 PM PDT 24 Jul 11 04:28:30 PM PDT 24 2019340496 ps
T868 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.99088107 Jul 11 04:27:55 PM PDT 24 Jul 11 04:27:58 PM PDT 24 2045414817 ps
T869 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.1042081574 Jul 11 04:28:10 PM PDT 24 Jul 11 04:28:13 PM PDT 24 2172237786 ps
T870 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3191871442 Jul 11 04:27:33 PM PDT 24 Jul 11 04:27:41 PM PDT 24 3214641793 ps
T871 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3901045103 Jul 11 04:28:07 PM PDT 24 Jul 11 04:28:10 PM PDT 24 2049425048 ps
T872 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.2578561600 Jul 11 04:28:05 PM PDT 24 Jul 11 04:28:30 PM PDT 24 9501480946 ps
T873 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2331779334 Jul 11 04:28:16 PM PDT 24 Jul 11 04:28:20 PM PDT 24 2065516076 ps
T874 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.637673297 Jul 11 04:27:30 PM PDT 24 Jul 11 04:27:34 PM PDT 24 2033852968 ps
T875 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1740686600 Jul 11 04:28:17 PM PDT 24 Jul 11 04:28:22 PM PDT 24 2031722075 ps
T876 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.267907665 Jul 11 04:27:03 PM PDT 24 Jul 11 04:27:42 PM PDT 24 39002980702 ps
T877 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3908662014 Jul 11 04:28:40 PM PDT 24 Jul 11 04:28:43 PM PDT 24 2040389747 ps
T878 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1304468224 Jul 11 04:27:26 PM PDT 24 Jul 11 04:27:33 PM PDT 24 2122231106 ps
T879 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2242234731 Jul 11 04:29:22 PM PDT 24 Jul 11 04:29:27 PM PDT 24 2027283537 ps
T880 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3230558523 Jul 11 04:28:12 PM PDT 24 Jul 11 04:28:30 PM PDT 24 22430030929 ps
T881 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3545547404 Jul 11 04:28:12 PM PDT 24 Jul 11 04:28:19 PM PDT 24 2036562427 ps
T882 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2570698910 Jul 11 04:27:58 PM PDT 24 Jul 11 04:28:11 PM PDT 24 2024612694 ps
T883 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1694909924 Jul 11 04:28:11 PM PDT 24 Jul 11 04:28:15 PM PDT 24 2014456431 ps
T884 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.4282177594 Jul 11 04:27:03 PM PDT 24 Jul 11 04:27:06 PM PDT 24 2037914020 ps
T885 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3499130049 Jul 11 04:28:16 PM PDT 24 Jul 11 04:28:20 PM PDT 24 2024014668 ps
T886 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3215983167 Jul 11 04:28:09 PM PDT 24 Jul 11 04:28:16 PM PDT 24 2012665107 ps
T887 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3189460199 Jul 11 04:27:30 PM PDT 24 Jul 11 04:27:33 PM PDT 24 2038707573 ps
T888 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.241273550 Jul 11 04:28:16 PM PDT 24 Jul 11 04:28:24 PM PDT 24 2012672145 ps
T889 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3077423861 Jul 11 04:28:06 PM PDT 24 Jul 11 04:28:24 PM PDT 24 2008990628 ps
T890 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3308250190 Jul 11 04:27:13 PM PDT 24 Jul 11 04:27:22 PM PDT 24 2039079597 ps
T891 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.4227347255 Jul 11 04:28:56 PM PDT 24 Jul 11 04:29:02 PM PDT 24 2021715205 ps
T892 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.509784654 Jul 11 04:28:17 PM PDT 24 Jul 11 04:28:23 PM PDT 24 7261710541 ps
T893 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1653165591 Jul 11 04:27:30 PM PDT 24 Jul 11 04:27:35 PM PDT 24 4060434927 ps
T894 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2186024861 Jul 11 04:29:32 PM PDT 24 Jul 11 04:29:59 PM PDT 24 43024276994 ps
T895 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2953215820 Jul 11 04:27:34 PM PDT 24 Jul 11 04:27:42 PM PDT 24 5024907628 ps
T896 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.399096273 Jul 11 04:27:30 PM PDT 24 Jul 11 04:27:33 PM PDT 24 2121495529 ps
T897 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3543718630 Jul 11 04:28:11 PM PDT 24 Jul 11 04:28:18 PM PDT 24 2025562498 ps
T898 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.798403661 Jul 11 04:27:12 PM PDT 24 Jul 11 04:27:19 PM PDT 24 2012688071 ps
T899 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.1856961293 Jul 11 04:28:06 PM PDT 24 Jul 11 04:28:11 PM PDT 24 2048119553 ps
T900 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.52431704 Jul 11 04:28:40 PM PDT 24 Jul 11 04:28:47 PM PDT 24 2055213019 ps
T901 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1801196754 Jul 11 04:27:34 PM PDT 24 Jul 11 04:27:46 PM PDT 24 2104096678 ps
T902 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2411930099 Jul 11 04:27:34 PM PDT 24 Jul 11 04:27:46 PM PDT 24 2675101190 ps
T903 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3838750441 Jul 11 04:28:14 PM PDT 24 Jul 11 04:28:20 PM PDT 24 2034470923 ps
T904 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3136996532 Jul 11 04:27:12 PM PDT 24 Jul 11 04:27:19 PM PDT 24 5396532830 ps
T905 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2184182237 Jul 11 04:27:35 PM PDT 24 Jul 11 04:27:48 PM PDT 24 2087059087 ps
T906 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2394446808 Jul 11 04:28:15 PM PDT 24 Jul 11 04:28:21 PM PDT 24 2109356180 ps
T907 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1534113238 Jul 11 04:28:25 PM PDT 24 Jul 11 04:28:29 PM PDT 24 2104494694 ps

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.1403895850
Short name T1
Test name
Test status
Simulation time 16921601520 ps
CPU time 9.31 seconds
Started Jul 11 04:54:23 PM PDT 24
Finished Jul 11 04:54:41 PM PDT 24
Peak memory 201780 kb
Host smart-a15bc684-62d6-4517-a3c9-5a936853d4b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403895850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.1403895850
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3138847182
Short name T7
Test name
Test status
Simulation time 117666800884 ps
CPU time 26.58 seconds
Started Jul 11 04:53:08 PM PDT 24
Finished Jul 11 04:53:40 PM PDT 24
Peak memory 201864 kb
Host smart-19b49457-61d1-4edd-bce2-f83004185efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138847182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wi
th_pre_cond.3138847182
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.2015586
Short name T91
Test name
Test status
Simulation time 95986334921 ps
CPU time 62.15 seconds
Started Jul 11 04:53:57 PM PDT 24
Finished Jul 11 04:55:08 PM PDT 24
Peak memory 210328 kb
Host smart-389ac23f-afe9-455b-89c7-8918b6a41f76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015586 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.2015586
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.3993948431
Short name T37
Test name
Test status
Simulation time 55631921324 ps
CPU time 61.87 seconds
Started Jul 11 04:53:24 PM PDT 24
Finished Jul 11 04:54:35 PM PDT 24
Peak memory 210188 kb
Host smart-5deae84a-88ef-416a-a0b4-3af60d07ad69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993948431 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.3993948431
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.1654001007
Short name T39
Test name
Test status
Simulation time 36807034271 ps
CPU time 50.34 seconds
Started Jul 11 04:52:40 PM PDT 24
Finished Jul 11 04:53:39 PM PDT 24
Peak memory 201560 kb
Host smart-8c54988e-f773-4347-a241-25298944ccfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654001007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.1654001007
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.900696793
Short name T46
Test name
Test status
Simulation time 12626000597 ps
CPU time 8.26 seconds
Started Jul 11 04:54:13 PM PDT 24
Finished Jul 11 04:54:30 PM PDT 24
Peak memory 201592 kb
Host smart-d4577982-dab0-402b-aa0f-989020a2dc9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900696793 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_st
ress_all.900696793
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.2776122305
Short name T54
Test name
Test status
Simulation time 462023243897 ps
CPU time 430.89 seconds
Started Jul 11 04:52:51 PM PDT 24
Finished Jul 11 05:00:09 PM PDT 24
Peak memory 201796 kb
Host smart-19cd421d-4780-4943-85b0-cf1405cbc95e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776122305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_st
ress_all.2776122305
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1773515387
Short name T295
Test name
Test status
Simulation time 42546759508 ps
CPU time 55.1 seconds
Started Jul 11 04:27:34 PM PDT 24
Finished Jul 11 04:28:33 PM PDT 24
Peak memory 202092 kb
Host smart-7465c712-d560-493b-9b3f-5ffbc7427c86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773515387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.1773515387
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.2204099339
Short name T85
Test name
Test status
Simulation time 37482627296 ps
CPU time 91.86 seconds
Started Jul 11 04:52:45 PM PDT 24
Finished Jul 11 04:54:24 PM PDT 24
Peak memory 201556 kb
Host smart-3c5a7a1d-904a-4def-bbd0-c7d17315e54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204099339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.2204099339
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3982097834
Short name T298
Test name
Test status
Simulation time 53240544094 ps
CPU time 31.34 seconds
Started Jul 11 04:53:08 PM PDT 24
Finished Jul 11 04:53:46 PM PDT 24
Peak memory 210228 kb
Host smart-fbfc94c2-b236-4c7e-85b8-f1ead70c9452
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982097834 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.3982097834
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.3819281821
Short name T84
Test name
Test status
Simulation time 387911299405 ps
CPU time 106.51 seconds
Started Jul 11 04:54:26 PM PDT 24
Finished Jul 11 04:56:22 PM PDT 24
Peak memory 201876 kb
Host smart-ea840c0b-5af5-408a-b4ff-484b8b7bd531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819281821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s
tress_all.3819281821
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2948212874
Short name T151
Test name
Test status
Simulation time 204550333650 ps
CPU time 132.51 seconds
Started Jul 11 04:54:27 PM PDT 24
Finished Jul 11 04:56:48 PM PDT 24
Peak memory 210144 kb
Host smart-164e76d2-1b27-449d-b468-b87ceb0544ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948212874 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.2948212874
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.3077610889
Short name T87
Test name
Test status
Simulation time 280421178888 ps
CPU time 112.73 seconds
Started Jul 11 04:53:47 PM PDT 24
Finished Jul 11 04:55:48 PM PDT 24
Peak memory 210220 kb
Host smart-62aa4f11-74da-4316-8cb8-dc44d19c0559
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077610889 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.3077610889
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.293373173
Short name T35
Test name
Test status
Simulation time 596580740252 ps
CPU time 83.01 seconds
Started Jul 11 04:53:29 PM PDT 24
Finished Jul 11 04:55:01 PM PDT 24
Peak memory 202092 kb
Host smart-2b8c4368-e20b-4b80-80f0-be13141c91cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293373173 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.293373173
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.2418498361
Short name T103
Test name
Test status
Simulation time 56402752893 ps
CPU time 139.28 seconds
Started Jul 11 04:53:36 PM PDT 24
Finished Jul 11 04:56:05 PM PDT 24
Peak memory 201860 kb
Host smart-b89c664e-0a4d-4223-b062-66a9769018b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418498361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_s
tress_all.2418498361
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.880735637
Short name T197
Test name
Test status
Simulation time 22011616082 ps
CPU time 59.42 seconds
Started Jul 11 04:52:53 PM PDT 24
Finished Jul 11 04:53:58 PM PDT 24
Peak memory 221152 kb
Host smart-9266dc64-e5a6-4afb-a2cc-848515928d2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880735637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.880735637
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.1821745809
Short name T22
Test name
Test status
Simulation time 3300845030 ps
CPU time 5.64 seconds
Started Jul 11 04:52:42 PM PDT 24
Finished Jul 11 04:52:56 PM PDT 24
Peak memory 201564 kb
Host smart-ad29c490-5382-4b04-b28d-cd5c8a45d34e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821745809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ultra_low_pwr.1821745809
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1888147539
Short name T170
Test name
Test status
Simulation time 398705547132 ps
CPU time 92.93 seconds
Started Jul 11 04:52:50 PM PDT 24
Finished Jul 11 04:54:29 PM PDT 24
Peak memory 215856 kb
Host smart-ca79990d-0c85-43bd-83e3-f315c741883f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888147539 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.1888147539
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.858763200
Short name T258
Test name
Test status
Simulation time 79584260314 ps
CPU time 47.82 seconds
Started Jul 11 04:52:46 PM PDT 24
Finished Jul 11 04:53:41 PM PDT 24
Peak memory 201892 kb
Host smart-d8d5bc31-7a3f-40cb-b480-4d9f735d4fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858763200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wit
h_pre_cond.858763200
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.4206535678
Short name T42
Test name
Test status
Simulation time 91936539017 ps
CPU time 220.42 seconds
Started Jul 11 04:53:56 PM PDT 24
Finished Jul 11 04:57:45 PM PDT 24
Peak memory 201944 kb
Host smart-a591a775-5596-4c40-a369-6954c2499884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206535678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.4206535678
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3435873573
Short name T20
Test name
Test status
Simulation time 2053348275 ps
CPU time 5.84 seconds
Started Jul 11 04:27:34 PM PDT 24
Finished Jul 11 04:27:43 PM PDT 24
Peak memory 201724 kb
Host smart-2bc63815-522a-436b-b4aa-b7ac12ef8046
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435873573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.3435873573
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3364716910
Short name T291
Test name
Test status
Simulation time 2208115394 ps
CPU time 4.97 seconds
Started Jul 11 04:29:08 PM PDT 24
Finished Jul 11 04:29:16 PM PDT 24
Peak memory 202028 kb
Host smart-549e321f-82b5-45df-898a-b34103648b1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364716910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.3364716910
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.403266461
Short name T193
Test name
Test status
Simulation time 4503976257 ps
CPU time 9.51 seconds
Started Jul 11 04:53:23 PM PDT 24
Finished Jul 11 04:53:41 PM PDT 24
Peak memory 201544 kb
Host smart-e293c0bf-9e50-49a5-b19a-bebdad12e532
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403266461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctr
l_edge_detect.403266461
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.590807180
Short name T153
Test name
Test status
Simulation time 5469969660 ps
CPU time 2.32 seconds
Started Jul 11 04:53:23 PM PDT 24
Finished Jul 11 04:53:34 PM PDT 24
Peak memory 201548 kb
Host smart-4558fe8f-5696-4232-b361-5e754a968147
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590807180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctr
l_edge_detect.590807180
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2263725324
Short name T155
Test name
Test status
Simulation time 40347599167 ps
CPU time 34.22 seconds
Started Jul 11 04:54:06 PM PDT 24
Finished Jul 11 04:54:49 PM PDT 24
Peak memory 210112 kb
Host smart-46da4d85-6d4e-4698-ae99-f91a59b5b1c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263725324 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.2263725324
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.496803557
Short name T73
Test name
Test status
Simulation time 64310159981 ps
CPU time 39.6 seconds
Started Jul 11 04:53:16 PM PDT 24
Finished Jul 11 04:54:03 PM PDT 24
Peak memory 201504 kb
Host smart-3f5ae7e1-edd0-4588-82af-7618ce6f20ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496803557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctr
l_edge_detect.496803557
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.3088793623
Short name T184
Test name
Test status
Simulation time 15348017314 ps
CPU time 10.63 seconds
Started Jul 11 04:53:27 PM PDT 24
Finished Jul 11 04:53:47 PM PDT 24
Peak memory 201572 kb
Host smart-4c2fb4db-7a96-4692-b0f4-e6f422205d85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088793623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.3088793623
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.1480061828
Short name T230
Test name
Test status
Simulation time 8915431838 ps
CPU time 23.68 seconds
Started Jul 11 04:53:38 PM PDT 24
Finished Jul 11 04:54:11 PM PDT 24
Peak memory 201556 kb
Host smart-ea6dcaa8-d773-4f50-883e-4c2fab4ccddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480061828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.1480061828
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2252307471
Short name T378
Test name
Test status
Simulation time 141278697891 ps
CPU time 87.31 seconds
Started Jul 11 04:53:20 PM PDT 24
Finished Jul 11 04:54:55 PM PDT 24
Peak memory 201820 kb
Host smart-725aa47f-f8d2-493f-b190-357b63348d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252307471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w
ith_pre_cond.2252307471
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.1492071481
Short name T11
Test name
Test status
Simulation time 547212160562 ps
CPU time 39.68 seconds
Started Jul 11 04:52:56 PM PDT 24
Finished Jul 11 04:53:42 PM PDT 24
Peak memory 201824 kb
Host smart-cb582001-a439-4823-8df4-8761827b0716
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492071481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.1492071481
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.1358165023
Short name T89
Test name
Test status
Simulation time 143772109582 ps
CPU time 95.41 seconds
Started Jul 11 04:53:15 PM PDT 24
Finished Jul 11 04:54:58 PM PDT 24
Peak memory 201876 kb
Host smart-e4346d5e-2b11-4af3-b5b7-04615a5108a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358165023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_w
ith_pre_cond.1358165023
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.1855512338
Short name T106
Test name
Test status
Simulation time 98659704836 ps
CPU time 54.49 seconds
Started Jul 11 04:54:31 PM PDT 24
Finished Jul 11 04:55:34 PM PDT 24
Peak memory 210228 kb
Host smart-21e633ea-dbcb-456a-991d-ce33a8b86680
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855512338 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.1855512338
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.3586549133
Short name T287
Test name
Test status
Simulation time 79863959043 ps
CPU time 211.61 seconds
Started Jul 11 04:53:43 PM PDT 24
Finished Jul 11 04:57:23 PM PDT 24
Peak memory 202084 kb
Host smart-8153df77-be54-41c6-be17-338a08f4e596
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586549133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.3586549133
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.1337419704
Short name T380
Test name
Test status
Simulation time 81224991681 ps
CPU time 50.88 seconds
Started Jul 11 04:54:39 PM PDT 24
Finished Jul 11 04:55:36 PM PDT 24
Peak memory 201836 kb
Host smart-df742a72-8784-4ec3-b0f9-4d11bd0224b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337419704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.1337419704
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.1001721872
Short name T251
Test name
Test status
Simulation time 2013751759 ps
CPU time 6.03 seconds
Started Jul 11 04:53:22 PM PDT 24
Finished Jul 11 04:53:36 PM PDT 24
Peak memory 201536 kb
Host smart-9c55f450-545e-4474-a7eb-d7ed5e724764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001721872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.1001721872
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.4023507391
Short name T23
Test name
Test status
Simulation time 1684547731566 ps
CPU time 221.56 seconds
Started Jul 11 04:52:55 PM PDT 24
Finished Jul 11 04:56:43 PM PDT 24
Peak memory 201516 kb
Host smart-59de57c3-eba9-4327-8964-12266614d6a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023507391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.4023507391
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3864114271
Short name T259
Test name
Test status
Simulation time 51784560980 ps
CPU time 28.96 seconds
Started Jul 11 04:54:39 PM PDT 24
Finished Jul 11 04:55:14 PM PDT 24
Peak memory 201928 kb
Host smart-9fecd844-8029-44bc-8239-1042f947e114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864114271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.3864114271
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.3354109121
Short name T224
Test name
Test status
Simulation time 139917484806 ps
CPU time 49.43 seconds
Started Jul 11 04:54:21 PM PDT 24
Finished Jul 11 04:55:19 PM PDT 24
Peak memory 201768 kb
Host smart-e1cc4f43-3f1c-466e-a52d-708668cf8339
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354109121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.3354109121
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2412861036
Short name T307
Test name
Test status
Simulation time 2496415763 ps
CPU time 3.65 seconds
Started Jul 11 04:27:59 PM PDT 24
Finished Jul 11 04:28:04 PM PDT 24
Peak memory 202080 kb
Host smart-17c9c107-f809-44ba-b2e5-3b701f9c1a74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412861036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_erro
rs.2412861036
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3295792695
Short name T281
Test name
Test status
Simulation time 106809601404 ps
CPU time 128.85 seconds
Started Jul 11 04:53:03 PM PDT 24
Finished Jul 11 04:55:17 PM PDT 24
Peak memory 201764 kb
Host smart-67e91b62-de0e-4479-9331-50c24a1bf3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295792695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.3295792695
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.769169690
Short name T55
Test name
Test status
Simulation time 48048663061 ps
CPU time 113.74 seconds
Started Jul 11 04:53:08 PM PDT 24
Finished Jul 11 04:55:08 PM PDT 24
Peak memory 210556 kb
Host smart-a44186e9-d70f-40c3-904d-4097609ace70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769169690 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.769169690
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.2675600137
Short name T396
Test name
Test status
Simulation time 70821378641 ps
CPU time 165.62 seconds
Started Jul 11 04:53:47 PM PDT 24
Finished Jul 11 04:56:41 PM PDT 24
Peak memory 201760 kb
Host smart-39e08a53-93c4-4505-9d76-02c0c2896be2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675600137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.2675600137
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1517950203
Short name T387
Test name
Test status
Simulation time 117662801290 ps
CPU time 80.16 seconds
Started Jul 11 04:52:51 PM PDT 24
Finished Jul 11 04:54:17 PM PDT 24
Peak memory 201928 kb
Host smart-a242332d-0837-44be-b355-059523d47382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517950203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.1517950203
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.2113852304
Short name T30
Test name
Test status
Simulation time 6123895888 ps
CPU time 4.03 seconds
Started Jul 11 04:27:34 PM PDT 24
Finished Jul 11 04:27:42 PM PDT 24
Peak memory 201872 kb
Host smart-cd3bbc40-6078-4a2b-8d7b-79a6d4699367
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113852304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.2113852304
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.133203260
Short name T6
Test name
Test status
Simulation time 77732218960 ps
CPU time 51.09 seconds
Started Jul 11 04:53:29 PM PDT 24
Finished Jul 11 04:54:29 PM PDT 24
Peak memory 201840 kb
Host smart-84af2763-2afe-4e1a-b424-b8c0840aed60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133203260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_wi
th_pre_cond.133203260
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.54302480
Short name T147
Test name
Test status
Simulation time 3610265897 ps
CPU time 8.03 seconds
Started Jul 11 04:53:38 PM PDT 24
Finished Jul 11 04:53:56 PM PDT 24
Peak memory 201592 kb
Host smart-893da8d3-1524-40cc-a0e7-3b68bc7ae812
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54302480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl
_edge_detect.54302480
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1230659102
Short name T310
Test name
Test status
Simulation time 42610172716 ps
CPU time 53.27 seconds
Started Jul 11 04:27:08 PM PDT 24
Finished Jul 11 04:28:04 PM PDT 24
Peak memory 202056 kb
Host smart-88b44e68-e6c4-4190-8101-023384066bf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230659102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.1230659102
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3181485699
Short name T379
Test name
Test status
Simulation time 62338031162 ps
CPU time 82.8 seconds
Started Jul 11 04:53:16 PM PDT 24
Finished Jul 11 04:54:46 PM PDT 24
Peak memory 201824 kb
Host smart-f6d1e25d-27e5-4d1d-8119-3fbb8d3ef2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181485699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_w
ith_pre_cond.3181485699
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.770808671
Short name T397
Test name
Test status
Simulation time 56088910342 ps
CPU time 71.83 seconds
Started Jul 11 04:53:40 PM PDT 24
Finished Jul 11 04:55:02 PM PDT 24
Peak memory 210132 kb
Host smart-1fe61470-64a1-4d85-87e5-eae2b1f1514c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770808671 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.770808671
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2002928785
Short name T403
Test name
Test status
Simulation time 452258130877 ps
CPU time 63.25 seconds
Started Jul 11 04:53:33 PM PDT 24
Finished Jul 11 04:54:46 PM PDT 24
Peak memory 210212 kb
Host smart-5402fa35-7006-4f28-bb96-0dbb99677385
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002928785 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.2002928785
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.117166024
Short name T399
Test name
Test status
Simulation time 147520408310 ps
CPU time 99.71 seconds
Started Jul 11 04:54:32 PM PDT 24
Finished Jul 11 04:56:20 PM PDT 24
Peak memory 202156 kb
Host smart-048dda36-cecb-423e-beaf-79fdc203ae00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117166024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_wi
th_pre_cond.117166024
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3023520907
Short name T220
Test name
Test status
Simulation time 166603161318 ps
CPU time 114.19 seconds
Started Jul 11 04:54:36 PM PDT 24
Finished Jul 11 04:56:37 PM PDT 24
Peak memory 201940 kb
Host smart-8bd75b0c-00c6-45e1-acdf-59fb3acdf11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023520907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_w
ith_pre_cond.3023520907
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.333250
Short name T373
Test name
Test status
Simulation time 100220821697 ps
CPU time 137.87 seconds
Started Jul 11 04:53:36 PM PDT 24
Finished Jul 11 04:56:03 PM PDT 24
Peak memory 201844 kb
Host smart-40ccfa0b-be2f-4454-ac3c-795538efa4e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_
combo_detect.333250
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.1446701362
Short name T219
Test name
Test status
Simulation time 4843034290 ps
CPU time 3.86 seconds
Started Jul 11 04:52:53 PM PDT 24
Finished Jul 11 04:53:03 PM PDT 24
Peak memory 201644 kb
Host smart-ae3f0e36-1aed-4b95-8d01-9a7f0a061fe7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446701362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.1446701362
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.1380529279
Short name T217
Test name
Test status
Simulation time 4132587319 ps
CPU time 8.06 seconds
Started Jul 11 04:53:47 PM PDT 24
Finished Jul 11 04:54:04 PM PDT 24
Peak memory 201624 kb
Host smart-e3faa0d5-6aa4-4042-a02c-818b00edb51f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380529279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.1380529279
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.3578321204
Short name T158
Test name
Test status
Simulation time 3225407022 ps
CPU time 6.98 seconds
Started Jul 11 04:54:14 PM PDT 24
Finished Jul 11 04:54:29 PM PDT 24
Peak memory 201548 kb
Host smart-edad6904-f710-4794-9611-8525e2e4d1a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578321204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_edge_detect.3578321204
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.2182615876
Short name T223
Test name
Test status
Simulation time 66988309430 ps
CPU time 177.54 seconds
Started Jul 11 04:52:37 PM PDT 24
Finished Jul 11 04:55:44 PM PDT 24
Peak memory 201896 kb
Host smart-e058ef49-c9a0-47f9-b97e-77e6497a146c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182615876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_combo_detect.2182615876
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.3095845991
Short name T319
Test name
Test status
Simulation time 2518521072 ps
CPU time 3.78 seconds
Started Jul 11 04:52:38 PM PDT 24
Finished Jul 11 04:52:52 PM PDT 24
Peak memory 201532 kb
Host smart-b0f2ecbd-9ac9-4fa9-be85-c2df7deadfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095845991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.3095845991
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.2755038742
Short name T59
Test name
Test status
Simulation time 2477029194 ps
CPU time 3.96 seconds
Started Jul 11 04:52:42 PM PDT 24
Finished Jul 11 04:52:54 PM PDT 24
Peak memory 201640 kb
Host smart-f1c84b74-0077-4346-8f75-f13267cb7f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755038742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.2755038742
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.1537640748
Short name T278
Test name
Test status
Simulation time 66856987472 ps
CPU time 81.34 seconds
Started Jul 11 04:53:13 PM PDT 24
Finished Jul 11 04:54:42 PM PDT 24
Peak memory 201868 kb
Host smart-daa3786b-ffb9-44da-92b3-828367f6cd27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537640748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.1537640748
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.2509991154
Short name T77
Test name
Test status
Simulation time 103159866549 ps
CPU time 41.8 seconds
Started Jul 11 04:53:10 PM PDT 24
Finished Jul 11 04:53:59 PM PDT 24
Peak memory 201812 kb
Host smart-9b1a01c2-44f1-40e0-aa6e-8cd6818ed5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509991154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_w
ith_pre_cond.2509991154
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1669120049
Short name T406
Test name
Test status
Simulation time 466938586660 ps
CPU time 73.85 seconds
Started Jul 11 04:53:17 PM PDT 24
Finished Jul 11 04:54:39 PM PDT 24
Peak memory 201652 kb
Host smart-031df3e6-890d-4fe6-9987-47b36a45ff76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669120049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.1669120049
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.327988428
Short name T280
Test name
Test status
Simulation time 200343868578 ps
CPU time 70.1 seconds
Started Jul 11 04:53:29 PM PDT 24
Finished Jul 11 04:54:48 PM PDT 24
Peak memory 201764 kb
Host smart-b62ec887-bec9-41bb-b43b-91906ab4fc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327988428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_wi
th_pre_cond.327988428
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.1504628225
Short name T719
Test name
Test status
Simulation time 72995544136 ps
CPU time 94.31 seconds
Started Jul 11 04:53:21 PM PDT 24
Finished Jul 11 04:55:04 PM PDT 24
Peak memory 201956 kb
Host smart-bb030691-9053-4e7d-86a7-8fd4834487a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504628225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_w
ith_pre_cond.1504628225
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.305623054
Short name T107
Test name
Test status
Simulation time 39724202022 ps
CPU time 8.63 seconds
Started Jul 11 04:53:34 PM PDT 24
Finished Jul 11 04:53:52 PM PDT 24
Peak memory 201852 kb
Host smart-953dd924-0195-4336-b15e-0fbee94e5900
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305623054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_combo_detect.305623054
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.3237517527
Short name T274
Test name
Test status
Simulation time 57203123753 ps
CPU time 38.96 seconds
Started Jul 11 04:53:46 PM PDT 24
Finished Jul 11 04:54:33 PM PDT 24
Peak memory 201916 kb
Host smart-1c29b852-52ee-4359-93c8-13793fcfc2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237517527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_w
ith_pre_cond.3237517527
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.2683559655
Short name T261
Test name
Test status
Simulation time 29846074843 ps
CPU time 20.42 seconds
Started Jul 11 04:54:05 PM PDT 24
Finished Jul 11 04:54:34 PM PDT 24
Peak memory 201860 kb
Host smart-f5f5e124-3b18-405f-8ab6-20f523baa373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683559655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.2683559655
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1968154419
Short name T160
Test name
Test status
Simulation time 61859497506 ps
CPU time 20.19 seconds
Started Jul 11 04:54:32 PM PDT 24
Finished Jul 11 04:54:59 PM PDT 24
Peak memory 201880 kb
Host smart-05b9c093-a444-45dc-9023-e99b948e76dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968154419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.1968154419
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.4019064997
Short name T257
Test name
Test status
Simulation time 101104787924 ps
CPU time 133.61 seconds
Started Jul 11 04:54:33 PM PDT 24
Finished Jul 11 04:56:54 PM PDT 24
Peak memory 201884 kb
Host smart-2ca7f2bc-8ec2-4320-99d9-6cb7166df297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019064997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.4019064997
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.962541265
Short name T255
Test name
Test status
Simulation time 55000602604 ps
CPU time 78.41 seconds
Started Jul 11 04:54:27 PM PDT 24
Finished Jul 11 04:55:54 PM PDT 24
Peak memory 201840 kb
Host smart-1afddbd5-30cc-4c08-9a8d-6bdd2f52d5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962541265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_wi
th_pre_cond.962541265
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3023648236
Short name T365
Test name
Test status
Simulation time 2790744888 ps
CPU time 10.88 seconds
Started Jul 11 04:27:13 PM PDT 24
Finished Jul 11 04:27:26 PM PDT 24
Peak memory 201988 kb
Host smart-fa9f1585-5d5d-49da-80fb-40ffc7e0b4bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023648236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.3023648236
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.467492827
Short name T816
Test name
Test status
Simulation time 39194704896 ps
CPU time 42.97 seconds
Started Jul 11 04:27:33 PM PDT 24
Finished Jul 11 04:28:20 PM PDT 24
Peak memory 202044 kb
Host smart-c8cc619c-7ee8-4585-87fb-36ea31ef1fdf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467492827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_
csr_bit_bash.467492827
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1052689713
Short name T815
Test name
Test status
Simulation time 4047654497 ps
CPU time 3.68 seconds
Started Jul 11 04:27:36 PM PDT 24
Finished Jul 11 04:27:43 PM PDT 24
Peak memory 201812 kb
Host smart-4725e55d-ae59-4b9c-b3ea-60ca32e2c8e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052689713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.1052689713
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3523013740
Short name T833
Test name
Test status
Simulation time 2247337693 ps
CPU time 1.43 seconds
Started Jul 11 04:27:10 PM PDT 24
Finished Jul 11 04:27:13 PM PDT 24
Peak memory 201940 kb
Host smart-38088495-7217-493e-8d49-ec623d02afc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523013740 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3523013740
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1571886734
Short name T357
Test name
Test status
Simulation time 2053654623 ps
CPU time 6.01 seconds
Started Jul 11 04:27:02 PM PDT 24
Finished Jul 11 04:27:10 PM PDT 24
Peak memory 201756 kb
Host smart-15fa53cc-a421-45af-a84a-88252212484b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571886734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.1571886734
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3189460199
Short name T887
Test name
Test status
Simulation time 2038707573 ps
CPU time 1.94 seconds
Started Jul 11 04:27:30 PM PDT 24
Finished Jul 11 04:27:33 PM PDT 24
Peak memory 200920 kb
Host smart-455ffc0d-d28a-4bae-96ec-8ba6a9bab86d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189460199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.3189460199
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1241189302
Short name T847
Test name
Test status
Simulation time 9913334764 ps
CPU time 4.36 seconds
Started Jul 11 04:28:22 PM PDT 24
Finished Jul 11 04:28:29 PM PDT 24
Peak memory 201972 kb
Host smart-b34f30a4-1a14-41fb-9068-34bbfd8f2641
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241189302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_same_csr_outstanding.1241189302
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1801196754
Short name T901
Test name
Test status
Simulation time 2104096678 ps
CPU time 7.3 seconds
Started Jul 11 04:27:34 PM PDT 24
Finished Jul 11 04:27:46 PM PDT 24
Peak memory 201144 kb
Host smart-2b4a306b-4cac-49cb-b658-1d55d4bf61bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801196754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.1801196754
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2411930099
Short name T902
Test name
Test status
Simulation time 2675101190 ps
CPU time 8.31 seconds
Started Jul 11 04:27:34 PM PDT 24
Finished Jul 11 04:27:46 PM PDT 24
Peak memory 201964 kb
Host smart-982abf2c-56c4-4197-ae0f-59603a1603ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411930099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.2411930099
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.267907665
Short name T876
Test name
Test status
Simulation time 39002980702 ps
CPU time 37.08 seconds
Started Jul 11 04:27:03 PM PDT 24
Finished Jul 11 04:27:42 PM PDT 24
Peak memory 202092 kb
Host smart-b51f3913-9dd1-4ce3-b212-038e799d1147
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267907665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_
csr_bit_bash.267907665
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.212942088
Short name T371
Test name
Test status
Simulation time 4063707264 ps
CPU time 2.5 seconds
Started Jul 11 04:27:28 PM PDT 24
Finished Jul 11 04:27:32 PM PDT 24
Peak memory 201736 kb
Host smart-bef8cb96-0b83-47a6-b601-505b95cc10c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212942088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_
csr_hw_reset.212942088
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1571833986
Short name T313
Test name
Test status
Simulation time 2101455151 ps
CPU time 3.56 seconds
Started Jul 11 04:27:03 PM PDT 24
Finished Jul 11 04:27:08 PM PDT 24
Peak memory 201736 kb
Host smart-e69a4a60-47f1-4a64-bda9-d5d486942867
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571833986 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1571833986
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.4119658726
Short name T794
Test name
Test status
Simulation time 2009519238 ps
CPU time 6.2 seconds
Started Jul 11 04:27:03 PM PDT 24
Finished Jul 11 04:27:11 PM PDT 24
Peak memory 201552 kb
Host smart-6cb4a82f-f99a-48aa-a409-93dee7246078
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119658726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_tes
t.4119658726
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3136996532
Short name T904
Test name
Test status
Simulation time 5396532830 ps
CPU time 5.45 seconds
Started Jul 11 04:27:12 PM PDT 24
Finished Jul 11 04:27:19 PM PDT 24
Peak memory 202108 kb
Host smart-3571bdc7-edb0-444b-b760-c9c759e8174c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136996532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.3136996532
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3308250190
Short name T890
Test name
Test status
Simulation time 2039079597 ps
CPU time 6.98 seconds
Started Jul 11 04:27:13 PM PDT 24
Finished Jul 11 04:27:22 PM PDT 24
Peak memory 201940 kb
Host smart-b0dd56c4-9626-4514-8664-2d034a67d43c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308250190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.3308250190
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.128767071
Short name T304
Test name
Test status
Simulation time 22283275383 ps
CPU time 29.59 seconds
Started Jul 11 04:27:16 PM PDT 24
Finished Jul 11 04:27:47 PM PDT 24
Peak memory 202096 kb
Host smart-3b3c6a2d-7ae4-453b-92b1-6e356291b171
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128767071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_tl_intg_err.128767071
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2130720409
Short name T855
Test name
Test status
Simulation time 2118684849 ps
CPU time 3.46 seconds
Started Jul 11 04:28:20 PM PDT 24
Finished Jul 11 04:28:25 PM PDT 24
Peak memory 201728 kb
Host smart-77155449-d38a-4b80-a759-85e632b67133
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130720409 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2130720409
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3002623427
Short name T368
Test name
Test status
Simulation time 2102253966 ps
CPU time 2.22 seconds
Started Jul 11 04:28:19 PM PDT 24
Finished Jul 11 04:28:23 PM PDT 24
Peak memory 201672 kb
Host smart-819db98a-15f6-4d3c-946d-2af1811f8785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002623427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.3002623427
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.4031135290
Short name T800
Test name
Test status
Simulation time 2012288398 ps
CPU time 5.63 seconds
Started Jul 11 04:28:04 PM PDT 24
Finished Jul 11 04:28:11 PM PDT 24
Peak memory 201656 kb
Host smart-e551cb63-e824-4e89-b2e8-108a91b4c4ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031135290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.4031135290
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.509784654
Short name T892
Test name
Test status
Simulation time 7261710541 ps
CPU time 4.06 seconds
Started Jul 11 04:28:17 PM PDT 24
Finished Jul 11 04:28:23 PM PDT 24
Peak memory 202068 kb
Host smart-8bda2a33-cdf1-4e6b-9a3a-4e5f0cc3b415
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509784654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.sysrst_ctrl_same_csr_outstanding.509784654
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3650366072
Short name T305
Test name
Test status
Simulation time 22274045626 ps
CPU time 16.92 seconds
Started Jul 11 04:28:07 PM PDT 24
Finished Jul 11 04:28:25 PM PDT 24
Peak memory 202116 kb
Host smart-9a020ee0-d543-4d95-9115-ff5627900877
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650366072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.3650366072
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3093617996
Short name T308
Test name
Test status
Simulation time 2139130968 ps
CPU time 3.79 seconds
Started Jul 11 04:28:07 PM PDT 24
Finished Jul 11 04:28:12 PM PDT 24
Peak memory 201820 kb
Host smart-e890b1ed-c4b1-443e-b8ba-a066ea7cbd5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093617996 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3093617996
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2030635668
Short name T31
Test name
Test status
Simulation time 2131233886 ps
CPU time 1.97 seconds
Started Jul 11 04:28:07 PM PDT 24
Finished Jul 11 04:28:10 PM PDT 24
Peak memory 201676 kb
Host smart-f09e839b-cc78-4662-bda6-e9eec2a1d7ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030635668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.2030635668
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1740686600
Short name T875
Test name
Test status
Simulation time 2031722075 ps
CPU time 1.83 seconds
Started Jul 11 04:28:17 PM PDT 24
Finished Jul 11 04:28:22 PM PDT 24
Peak memory 201500 kb
Host smart-5a57ce0f-a03a-4a2b-85ba-168f3c93c3ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740686600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_te
st.1740686600
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.503161026
Short name T848
Test name
Test status
Simulation time 9427611925 ps
CPU time 4.75 seconds
Started Jul 11 04:27:59 PM PDT 24
Finished Jul 11 04:28:05 PM PDT 24
Peak memory 202096 kb
Host smart-78c5244d-47b0-42be-98cd-860948b82bdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503161026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.sysrst_ctrl_same_csr_outstanding.503161026
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.517976516
Short name T841
Test name
Test status
Simulation time 2313886318 ps
CPU time 3.41 seconds
Started Jul 11 04:28:05 PM PDT 24
Finished Jul 11 04:28:10 PM PDT 24
Peak memory 202032 kb
Host smart-f5c3bc53-82bd-4027-b582-97ab73ce47f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517976516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_error
s.517976516
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.4229422530
Short name T863
Test name
Test status
Simulation time 22514214320 ps
CPU time 14.45 seconds
Started Jul 11 04:28:23 PM PDT 24
Finished Jul 11 04:28:45 PM PDT 24
Peak memory 202080 kb
Host smart-4f795063-2227-49dc-9bd3-bbf2249ce2d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229422530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.4229422530
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.977912635
Short name T842
Test name
Test status
Simulation time 2149805552 ps
CPU time 3.91 seconds
Started Jul 11 04:28:14 PM PDT 24
Finished Jul 11 04:28:20 PM PDT 24
Peak memory 201960 kb
Host smart-d9648d73-2bff-42a7-96ae-6cb9f733505d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977912635 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.977912635
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3448067596
Short name T360
Test name
Test status
Simulation time 2116836865 ps
CPU time 2.22 seconds
Started Jul 11 04:28:07 PM PDT 24
Finished Jul 11 04:28:10 PM PDT 24
Peak memory 201664 kb
Host smart-c8b96c18-5634-4832-a3f2-0fb427c47994
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448067596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_
rw.3448067596
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2331779334
Short name T873
Test name
Test status
Simulation time 2065516076 ps
CPU time 1.06 seconds
Started Jul 11 04:28:16 PM PDT 24
Finished Jul 11 04:28:20 PM PDT 24
Peak memory 201344 kb
Host smart-2793c993-f186-4019-ab5e-3e2b409bbc17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331779334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.2331779334
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.360922144
Short name T849
Test name
Test status
Simulation time 7987603045 ps
CPU time 6.13 seconds
Started Jul 11 04:29:32 PM PDT 24
Finished Jul 11 04:29:39 PM PDT 24
Peak memory 202184 kb
Host smart-954c2afa-6699-47d8-83c5-24d8b7dd340a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360922144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.sysrst_ctrl_same_csr_outstanding.360922144
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2103894550
Short name T859
Test name
Test status
Simulation time 2171874960 ps
CPU time 4 seconds
Started Jul 11 04:28:07 PM PDT 24
Finished Jul 11 04:28:12 PM PDT 24
Peak memory 210244 kb
Host smart-b732207e-cb76-4272-8947-246cab63f952
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103894550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.2103894550
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2844129234
Short name T834
Test name
Test status
Simulation time 22269816741 ps
CPU time 15.09 seconds
Started Jul 11 04:28:09 PM PDT 24
Finished Jul 11 04:28:26 PM PDT 24
Peak memory 202052 kb
Host smart-9ef8f3e3-6c98-4700-a8f7-30fcebf8e978
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844129234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.2844129234
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3267490903
Short name T804
Test name
Test status
Simulation time 2067064777 ps
CPU time 5.95 seconds
Started Jul 11 04:28:08 PM PDT 24
Finished Jul 11 04:28:15 PM PDT 24
Peak memory 201724 kb
Host smart-d3377592-daf0-4d5a-ac48-14699e61ddb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267490903 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3267490903
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3545547404
Short name T881
Test name
Test status
Simulation time 2036562427 ps
CPU time 5.98 seconds
Started Jul 11 04:28:12 PM PDT 24
Finished Jul 11 04:28:19 PM PDT 24
Peak memory 200972 kb
Host smart-5d89df70-4c17-42ec-9256-2ee011abc03e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545547404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.3545547404
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2047702033
Short name T789
Test name
Test status
Simulation time 2044367125 ps
CPU time 2 seconds
Started Jul 11 04:28:03 PM PDT 24
Finished Jul 11 04:28:06 PM PDT 24
Peak memory 201500 kb
Host smart-3ea060b2-5598-48cf-9ad1-5960c00c7d23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047702033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.2047702033
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.4176529269
Short name T832
Test name
Test status
Simulation time 9161681098 ps
CPU time 36.81 seconds
Started Jul 11 04:28:26 PM PDT 24
Finished Jul 11 04:29:05 PM PDT 24
Peak memory 202084 kb
Host smart-57eb045c-5560-4823-8606-94c3ce7fe98c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176529269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.4176529269
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1689948737
Short name T300
Test name
Test status
Simulation time 2083010412 ps
CPU time 6.2 seconds
Started Jul 11 04:28:11 PM PDT 24
Finished Jul 11 04:28:18 PM PDT 24
Peak memory 201936 kb
Host smart-0e9a70c1-f1ee-4241-ab25-59d519829a83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689948737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_erro
rs.1689948737
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3899943642
Short name T32
Test name
Test status
Simulation time 42422633072 ps
CPU time 107.25 seconds
Started Jul 11 04:28:18 PM PDT 24
Finished Jul 11 04:30:08 PM PDT 24
Peak memory 202072 kb
Host smart-c03ffced-f5da-4695-b183-ca9a36a9aede
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899943642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.3899943642
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3877784891
Short name T312
Test name
Test status
Simulation time 2116197426 ps
CPU time 6.29 seconds
Started Jul 11 04:28:05 PM PDT 24
Finished Jul 11 04:28:13 PM PDT 24
Peak memory 202208 kb
Host smart-824faa8c-e322-4506-99a9-3f40c5ae4f9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877784891 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3877784891
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3838750441
Short name T903
Test name
Test status
Simulation time 2034470923 ps
CPU time 5.8 seconds
Started Jul 11 04:28:14 PM PDT 24
Finished Jul 11 04:28:20 PM PDT 24
Peak memory 201652 kb
Host smart-99df540b-28f4-4867-b86a-6f857f5b061f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838750441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_
rw.3838750441
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3431104633
Short name T866
Test name
Test status
Simulation time 2082369238 ps
CPU time 1.23 seconds
Started Jul 11 04:28:11 PM PDT 24
Finished Jul 11 04:28:13 PM PDT 24
Peak memory 201464 kb
Host smart-280e282c-69c5-45e9-b8b0-c7916c7f6d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431104633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.3431104633
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1418825014
Short name T831
Test name
Test status
Simulation time 5341690468 ps
CPU time 10.9 seconds
Started Jul 11 04:28:24 PM PDT 24
Finished Jul 11 04:28:37 PM PDT 24
Peak memory 202028 kb
Host smart-12e61255-b61b-4067-bc86-006e683d232c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418825014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.1418825014
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2853318964
Short name T299
Test name
Test status
Simulation time 2422935084 ps
CPU time 3.7 seconds
Started Jul 11 04:28:00 PM PDT 24
Finished Jul 11 04:28:06 PM PDT 24
Peak memory 202036 kb
Host smart-7b98c4b2-cb6d-463a-9b17-527a0debb54d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853318964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.2853318964
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2186024861
Short name T894
Test name
Test status
Simulation time 43024276994 ps
CPU time 26.56 seconds
Started Jul 11 04:29:32 PM PDT 24
Finished Jul 11 04:29:59 PM PDT 24
Peak memory 202108 kb
Host smart-3f7966e4-f80e-4cf4-a0f8-1f55f5f27fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186024861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.2186024861
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3010940265
Short name T808
Test name
Test status
Simulation time 2106737445 ps
CPU time 2.13 seconds
Started Jul 11 04:28:06 PM PDT 24
Finished Jul 11 04:28:10 PM PDT 24
Peak memory 201724 kb
Host smart-e0e5c9f9-9696-433b-b29c-70b5ce7fd442
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010940265 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3010940265
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1450153186
Short name T366
Test name
Test status
Simulation time 2066602049 ps
CPU time 3.27 seconds
Started Jul 11 04:29:32 PM PDT 24
Finished Jul 11 04:29:36 PM PDT 24
Peak memory 201844 kb
Host smart-d4931376-435b-470f-8436-2c9407fb7780
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450153186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.1450153186
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2582673052
Short name T793
Test name
Test status
Simulation time 2013002836 ps
CPU time 5.38 seconds
Started Jul 11 04:28:29 PM PDT 24
Finished Jul 11 04:28:37 PM PDT 24
Peak memory 201576 kb
Host smart-9d87522d-1110-4d21-bd57-e0a57522ace0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582673052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.2582673052
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1183112742
Short name T19
Test name
Test status
Simulation time 7684229988 ps
CPU time 5.58 seconds
Started Jul 11 04:28:10 PM PDT 24
Finished Jul 11 04:28:18 PM PDT 24
Peak memory 202096 kb
Host smart-1a3f94ec-8008-4415-83ca-5acbb11da406
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183112742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.1183112742
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.814308679
Short name T825
Test name
Test status
Simulation time 2170468641 ps
CPU time 2.59 seconds
Started Jul 11 04:28:17 PM PDT 24
Finished Jul 11 04:28:23 PM PDT 24
Peak memory 202048 kb
Host smart-d8578080-1456-423a-9b6a-500af416fa56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814308679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_error
s.814308679
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1842885150
Short name T840
Test name
Test status
Simulation time 42404004962 ps
CPU time 104.93 seconds
Started Jul 11 04:28:27 PM PDT 24
Finished Jul 11 04:30:15 PM PDT 24
Peak memory 202048 kb
Host smart-69d4661a-92af-45a5-b5b5-ad8194f8fb59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842885150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.1842885150
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1317901068
Short name T839
Test name
Test status
Simulation time 2068844329 ps
CPU time 2.01 seconds
Started Jul 11 04:28:03 PM PDT 24
Finished Jul 11 04:28:06 PM PDT 24
Peak memory 201820 kb
Host smart-e96e916c-8b1d-470f-af91-2f489bb17a15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317901068 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1317901068
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3899887649
Short name T361
Test name
Test status
Simulation time 2114439842 ps
CPU time 1.42 seconds
Started Jul 11 04:28:33 PM PDT 24
Finished Jul 11 04:28:36 PM PDT 24
Peak memory 201668 kb
Host smart-4611abc5-83ca-4b58-9469-47c60fb163f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899887649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.3899887649
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2570698910
Short name T882
Test name
Test status
Simulation time 2024612694 ps
CPU time 2.68 seconds
Started Jul 11 04:27:58 PM PDT 24
Finished Jul 11 04:28:11 PM PDT 24
Peak memory 201520 kb
Host smart-8491b5c1-bec9-44b6-bd09-fb9fc7ca8e5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570698910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.2570698910
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2679505563
Short name T821
Test name
Test status
Simulation time 4795522527 ps
CPU time 6.85 seconds
Started Jul 11 04:28:16 PM PDT 24
Finished Jul 11 04:28:26 PM PDT 24
Peak memory 201924 kb
Host smart-97daf114-3598-44af-adc0-dc2fd366eac7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679505563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.2679505563
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3543718630
Short name T897
Test name
Test status
Simulation time 2025562498 ps
CPU time 5.99 seconds
Started Jul 11 04:28:11 PM PDT 24
Finished Jul 11 04:28:18 PM PDT 24
Peak memory 201852 kb
Host smart-eb146cc7-4832-4e40-b618-bae0f3f590c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543718630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.3543718630
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3550321272
Short name T292
Test name
Test status
Simulation time 45386136430 ps
CPU time 10.65 seconds
Started Jul 11 04:28:25 PM PDT 24
Finished Jul 11 04:28:38 PM PDT 24
Peak memory 202064 kb
Host smart-8db85ff1-954a-4eec-ab9b-8dcb673846e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550321272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.3550321272
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2948179856
Short name T862
Test name
Test status
Simulation time 2215963693 ps
CPU time 1.63 seconds
Started Jul 11 04:28:18 PM PDT 24
Finished Jul 11 04:28:22 PM PDT 24
Peak memory 201856 kb
Host smart-ccfd4854-055f-4341-8601-10b815178193
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948179856 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2948179856
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1642545243
Short name T369
Test name
Test status
Simulation time 2066058368 ps
CPU time 2.2 seconds
Started Jul 11 04:29:16 PM PDT 24
Finished Jul 11 04:29:22 PM PDT 24
Peak memory 200864 kb
Host smart-54614c41-d2a8-42aa-b2de-6c0a9ba0d218
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642545243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.1642545243
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.754690684
Short name T846
Test name
Test status
Simulation time 2048567088 ps
CPU time 1.56 seconds
Started Jul 11 04:29:30 PM PDT 24
Finished Jul 11 04:29:33 PM PDT 24
Peak memory 201580 kb
Host smart-53ede942-51c0-4056-82d2-a5b3c18e29ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754690684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_tes
t.754690684
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.2385490886
Short name T854
Test name
Test status
Simulation time 9359587867 ps
CPU time 25.58 seconds
Started Jul 11 04:29:28 PM PDT 24
Finished Jul 11 04:29:55 PM PDT 24
Peak memory 202136 kb
Host smart-4ce7c91d-29ab-426d-8369-2e4d05ba15a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385490886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_same_csr_outstanding.2385490886
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.558543129
Short name T861
Test name
Test status
Simulation time 2076295700 ps
CPU time 2.55 seconds
Started Jul 11 04:29:28 PM PDT 24
Finished Jul 11 04:29:33 PM PDT 24
Peak memory 201984 kb
Host smart-4919e435-cbaa-4f6d-b201-eee6e930d611
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558543129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_error
s.558543129
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3230558523
Short name T880
Test name
Test status
Simulation time 22430030929 ps
CPU time 16.83 seconds
Started Jul 11 04:28:12 PM PDT 24
Finished Jul 11 04:28:30 PM PDT 24
Peak memory 202088 kb
Host smart-15266a16-2619-4478-973f-82ae6c25e8c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230558523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_tl_intg_err.3230558523
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.559152362
Short name T822
Test name
Test status
Simulation time 2107289195 ps
CPU time 2.43 seconds
Started Jul 11 04:28:10 PM PDT 24
Finished Jul 11 04:28:15 PM PDT 24
Peak memory 201724 kb
Host smart-f7048da5-4a42-4c32-8e5f-c4637c39c10e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559152362 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.559152362
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2904016571
Short name T358
Test name
Test status
Simulation time 2174607278 ps
CPU time 1.75 seconds
Started Jul 11 04:29:07 PM PDT 24
Finished Jul 11 04:29:12 PM PDT 24
Peak memory 201864 kb
Host smart-85d9bd40-5bcf-421d-8864-a0b6be91a981
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904016571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.2904016571
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3215983167
Short name T886
Test name
Test status
Simulation time 2012665107 ps
CPU time 5.38 seconds
Started Jul 11 04:28:09 PM PDT 24
Finished Jul 11 04:28:16 PM PDT 24
Peak memory 201656 kb
Host smart-1b27f95c-0b01-4de2-85fe-0353b71d1f40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215983167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.3215983167
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.119476508
Short name T812
Test name
Test status
Simulation time 4955536533 ps
CPU time 2.31 seconds
Started Jul 11 04:28:08 PM PDT 24
Finished Jul 11 04:28:11 PM PDT 24
Peak memory 202112 kb
Host smart-c166dad2-d33b-4ab4-aa58-3a74eee6da0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119476508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.sysrst_ctrl_same_csr_outstanding.119476508
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3870413561
Short name T836
Test name
Test status
Simulation time 2259455561 ps
CPU time 3.14 seconds
Started Jul 11 04:28:11 PM PDT 24
Finished Jul 11 04:28:16 PM PDT 24
Peak memory 202060 kb
Host smart-308c0b23-f9a4-4067-8f64-136119a31d6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870413561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.3870413561
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.510473171
Short name T303
Test name
Test status
Simulation time 42428402127 ps
CPU time 119.44 seconds
Started Jul 11 04:28:24 PM PDT 24
Finished Jul 11 04:30:26 PM PDT 24
Peak memory 202116 kb
Host smart-8199f9f5-d9dc-400a-bf32-d175e5301e3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510473171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_tl_intg_err.510473171
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1165366999
Short name T306
Test name
Test status
Simulation time 2261633270 ps
CPU time 1.28 seconds
Started Jul 11 04:28:16 PM PDT 24
Finished Jul 11 04:28:20 PM PDT 24
Peak memory 201928 kb
Host smart-7d4b2b55-4904-49ca-a55c-bb2d7d97576f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165366999 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1165366999
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2685463872
Short name T864
Test name
Test status
Simulation time 2077317096 ps
CPU time 2.05 seconds
Started Jul 11 04:28:14 PM PDT 24
Finished Jul 11 04:28:16 PM PDT 24
Peak memory 201676 kb
Host smart-90f8612e-6fa8-4461-8a38-691ba3cb8568
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685463872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.2685463872
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.659905431
Short name T801
Test name
Test status
Simulation time 2040978074 ps
CPU time 1.86 seconds
Started Jul 11 04:28:38 PM PDT 24
Finished Jul 11 04:28:41 PM PDT 24
Peak memory 201544 kb
Host smart-8c7859bc-2028-4b52-a56e-ced9de5578d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659905431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_tes
t.659905431
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2178974041
Short name T809
Test name
Test status
Simulation time 8034475254 ps
CPU time 21.15 seconds
Started Jul 11 04:28:15 PM PDT 24
Finished Jul 11 04:28:38 PM PDT 24
Peak memory 202064 kb
Host smart-0abab72f-8844-4149-815d-4488697137d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178974041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.2178974041
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.3378219656
Short name T827
Test name
Test status
Simulation time 22283652107 ps
CPU time 29.3 seconds
Started Jul 11 04:28:11 PM PDT 24
Finished Jul 11 04:28:41 PM PDT 24
Peak memory 202116 kb
Host smart-5980d062-bed2-42b6-a00f-f413059d8a7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378219656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.3378219656
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.4230147365
Short name T359
Test name
Test status
Simulation time 2274201808 ps
CPU time 7.58 seconds
Started Jul 11 04:28:12 PM PDT 24
Finished Jul 11 04:28:21 PM PDT 24
Peak memory 202008 kb
Host smart-69b315fd-bfbf-4a6f-8236-1c429d2bcb3f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230147365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.4230147365
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1047810982
Short name T363
Test name
Test status
Simulation time 7574461279 ps
CPU time 8.39 seconds
Started Jul 11 04:27:10 PM PDT 24
Finished Jul 11 04:27:21 PM PDT 24
Peak memory 202044 kb
Host smart-07c4eb46-1b49-4e9c-882f-4bd740f79877
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047810982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.1047810982
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2384043033
Short name T807
Test name
Test status
Simulation time 4033878092 ps
CPU time 11.17 seconds
Started Jul 11 04:27:10 PM PDT 24
Finished Jul 11 04:27:23 PM PDT 24
Peak memory 201792 kb
Host smart-f04fdcf0-32f2-42d1-998c-5138b4b670a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384043033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.2384043033
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2184182237
Short name T905
Test name
Test status
Simulation time 2087059087 ps
CPU time 6.06 seconds
Started Jul 11 04:27:35 PM PDT 24
Finished Jul 11 04:27:48 PM PDT 24
Peak memory 201772 kb
Host smart-962e2433-7fe7-481a-ad26-19ccc754822b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184182237 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2184182237
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.4051954146
Short name T823
Test name
Test status
Simulation time 2058301301 ps
CPU time 1.98 seconds
Started Jul 11 04:27:34 PM PDT 24
Finished Jul 11 04:27:44 PM PDT 24
Peak memory 201624 kb
Host smart-618703b6-9cf2-4dac-8d43-07e1be6a9058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051954146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.4051954146
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.4282177594
Short name T884
Test name
Test status
Simulation time 2037914020 ps
CPU time 1.95 seconds
Started Jul 11 04:27:03 PM PDT 24
Finished Jul 11 04:27:06 PM PDT 24
Peak memory 201520 kb
Host smart-b5c64422-8304-4414-9b31-0acb7e290e16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282177594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.4282177594
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1893484324
Short name T824
Test name
Test status
Simulation time 5436758482 ps
CPU time 21.48 seconds
Started Jul 11 04:27:20 PM PDT 24
Finished Jul 11 04:27:42 PM PDT 24
Peak memory 202084 kb
Host smart-31bc3e21-dd60-49a6-8604-a00f6d0e3e97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893484324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.1893484324
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1830408052
Short name T853
Test name
Test status
Simulation time 2193961227 ps
CPU time 1.78 seconds
Started Jul 11 04:27:10 PM PDT 24
Finished Jul 11 04:27:15 PM PDT 24
Peak memory 202080 kb
Host smart-2ad938c4-a3f8-4723-9ff0-6b524fffa1dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830408052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.1830408052
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.4044361757
Short name T856
Test name
Test status
Simulation time 42387764744 ps
CPU time 82.9 seconds
Started Jul 11 04:28:13 PM PDT 24
Finished Jul 11 04:29:37 PM PDT 24
Peak memory 202068 kb
Host smart-baae8fe6-b457-4021-9343-c47a9fc050f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044361757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.4044361757
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2737488616
Short name T843
Test name
Test status
Simulation time 2014771212 ps
CPU time 5.73 seconds
Started Jul 11 04:28:26 PM PDT 24
Finished Jul 11 04:28:34 PM PDT 24
Peak memory 201564 kb
Host smart-dba08119-e445-401a-b7ae-5553f1b38f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737488616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.2737488616
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1534113238
Short name T907
Test name
Test status
Simulation time 2104494694 ps
CPU time 1.01 seconds
Started Jul 11 04:28:25 PM PDT 24
Finished Jul 11 04:28:29 PM PDT 24
Peak memory 201496 kb
Host smart-8e83895c-dc59-4821-af49-d5856ab6436e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534113238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.1534113238
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3055356422
Short name T802
Test name
Test status
Simulation time 2047815643 ps
CPU time 1.74 seconds
Started Jul 11 04:28:19 PM PDT 24
Finished Jul 11 04:28:23 PM PDT 24
Peak memory 201652 kb
Host smart-19dfe739-ff67-4291-a955-6c63807f9332
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055356422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.3055356422
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1928669076
Short name T852
Test name
Test status
Simulation time 2013072618 ps
CPU time 5.87 seconds
Started Jul 11 04:28:27 PM PDT 24
Finished Jul 11 04:28:35 PM PDT 24
Peak memory 201600 kb
Host smart-ee5b9805-0603-459b-bbbb-e6c268f1d556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928669076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.1928669076
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.298872641
Short name T787
Test name
Test status
Simulation time 2034967717 ps
CPU time 1.98 seconds
Started Jul 11 04:28:19 PM PDT 24
Finished Jul 11 04:28:23 PM PDT 24
Peak memory 201556 kb
Host smart-51c78588-5ef1-49fc-a268-6252f2febb95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298872641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_tes
t.298872641
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1126989647
Short name T818
Test name
Test status
Simulation time 2030632173 ps
CPU time 1.87 seconds
Started Jul 11 04:28:30 PM PDT 24
Finished Jul 11 04:28:34 PM PDT 24
Peak memory 202044 kb
Host smart-1b7d78ce-276d-464f-a33f-847163137ce2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126989647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.1126989647
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.1856961293
Short name T899
Test name
Test status
Simulation time 2048119553 ps
CPU time 1.96 seconds
Started Jul 11 04:28:06 PM PDT 24
Finished Jul 11 04:28:11 PM PDT 24
Peak memory 201680 kb
Host smart-f5286852-64d6-436b-9759-9bb41be64041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856961293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.1856961293
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1928166009
Short name T803
Test name
Test status
Simulation time 2013581632 ps
CPU time 5.32 seconds
Started Jul 11 04:28:17 PM PDT 24
Finished Jul 11 04:28:25 PM PDT 24
Peak memory 201652 kb
Host smart-d630e979-1b83-4d65-97e9-ec5055e39a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928166009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.1928166009
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3247880259
Short name T844
Test name
Test status
Simulation time 2036244759 ps
CPU time 1.84 seconds
Started Jul 11 04:28:22 PM PDT 24
Finished Jul 11 04:28:26 PM PDT 24
Peak memory 201504 kb
Host smart-a4e09bd3-5f93-46e7-bd27-0f8a32d7b246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247880259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te
st.3247880259
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.3946352708
Short name T811
Test name
Test status
Simulation time 2049039886 ps
CPU time 1.55 seconds
Started Jul 11 04:28:09 PM PDT 24
Finished Jul 11 04:28:11 PM PDT 24
Peak memory 201556 kb
Host smart-8a4b0fcb-aa9c-4fed-a0a3-4dcb89329efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946352708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.3946352708
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3191871442
Short name T870
Test name
Test status
Simulation time 3214641793 ps
CPU time 4.85 seconds
Started Jul 11 04:27:33 PM PDT 24
Finished Jul 11 04:27:41 PM PDT 24
Peak memory 202032 kb
Host smart-59c093b8-d159-4c3e-96b5-26cef60f04a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191871442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_aliasing.3191871442
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.4085116023
Short name T858
Test name
Test status
Simulation time 34479936560 ps
CPU time 176.61 seconds
Started Jul 11 04:27:38 PM PDT 24
Finished Jul 11 04:30:37 PM PDT 24
Peak memory 201976 kb
Host smart-da638228-7f3d-4a79-b09f-bb6ae0e890eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085116023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.4085116023
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.399096273
Short name T896
Test name
Test status
Simulation time 2121495529 ps
CPU time 1.71 seconds
Started Jul 11 04:27:30 PM PDT 24
Finished Jul 11 04:27:33 PM PDT 24
Peak memory 200756 kb
Host smart-a409b738-28d1-48ef-b18d-6a73e9c60c8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399096273 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.399096273
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1206589356
Short name T367
Test name
Test status
Simulation time 2068120823 ps
CPU time 3.53 seconds
Started Jul 11 04:28:16 PM PDT 24
Finished Jul 11 04:28:23 PM PDT 24
Peak memory 201700 kb
Host smart-09c865c6-b087-43ca-b1dd-ada0898a4b82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206589356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.1206589356
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.2246319138
Short name T820
Test name
Test status
Simulation time 2016997854 ps
CPU time 5.68 seconds
Started Jul 11 04:27:11 PM PDT 24
Finished Jul 11 04:27:19 PM PDT 24
Peak memory 201476 kb
Host smart-9821e25e-8306-41ab-adc5-d50c48a977c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246319138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.2246319138
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.1116065326
Short name T805
Test name
Test status
Simulation time 7976949882 ps
CPU time 10.7 seconds
Started Jul 11 04:27:10 PM PDT 24
Finished Jul 11 04:27:23 PM PDT 24
Peak memory 202100 kb
Host smart-e37369d7-e5e6-4c6e-a30e-7964b4230300
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116065326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.1116065326
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.4102614177
Short name T301
Test name
Test status
Simulation time 2608657836 ps
CPU time 3.87 seconds
Started Jul 11 04:27:13 PM PDT 24
Finished Jul 11 04:27:19 PM PDT 24
Peak memory 202100 kb
Host smart-31f00d04-f2a0-4f55-8a58-1e8cb7a5f67c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102614177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.4102614177
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3901045103
Short name T871
Test name
Test status
Simulation time 2049425048 ps
CPU time 1.45 seconds
Started Jul 11 04:28:07 PM PDT 24
Finished Jul 11 04:28:10 PM PDT 24
Peak memory 201532 kb
Host smart-ad14857f-2801-41ee-888d-55bfa2748cbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901045103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.3901045103
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.122726759
Short name T797
Test name
Test status
Simulation time 2016649851 ps
CPU time 5.6 seconds
Started Jul 11 04:28:11 PM PDT 24
Finished Jul 11 04:28:18 PM PDT 24
Peak memory 201528 kb
Host smart-575ab4ec-2811-4b82-84ba-01d050c80004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122726759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_tes
t.122726759
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.4227347255
Short name T891
Test name
Test status
Simulation time 2021715205 ps
CPU time 4.08 seconds
Started Jul 11 04:28:56 PM PDT 24
Finished Jul 11 04:29:02 PM PDT 24
Peak memory 201744 kb
Host smart-89dd8614-973c-46e6-90aa-dc7bd941f482
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227347255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.4227347255
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2413633565
Short name T798
Test name
Test status
Simulation time 2012178787 ps
CPU time 5.38 seconds
Started Jul 11 04:29:21 PM PDT 24
Finished Jul 11 04:29:30 PM PDT 24
Peak memory 200752 kb
Host smart-2d0fa238-a742-47cb-b1f0-9b00e2ef3c34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413633565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.2413633565
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1639234799
Short name T828
Test name
Test status
Simulation time 2015595305 ps
CPU time 3.03 seconds
Started Jul 11 04:28:16 PM PDT 24
Finished Jul 11 04:28:21 PM PDT 24
Peak memory 201320 kb
Host smart-4d8f9cbd-923c-474b-9945-d117be26ba0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639234799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.1639234799
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2568709806
Short name T817
Test name
Test status
Simulation time 2044027799 ps
CPU time 1.55 seconds
Started Jul 11 04:28:13 PM PDT 24
Finished Jul 11 04:28:15 PM PDT 24
Peak memory 201556 kb
Host smart-c1c74593-c235-4ace-8162-90aabf6bcccb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568709806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.2568709806
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1694909924
Short name T883
Test name
Test status
Simulation time 2014456431 ps
CPU time 3.07 seconds
Started Jul 11 04:28:11 PM PDT 24
Finished Jul 11 04:28:15 PM PDT 24
Peak memory 201652 kb
Host smart-8f39d0ef-4803-431f-ac34-abf79eb9d373
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694909924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.1694909924
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3499130049
Short name T885
Test name
Test status
Simulation time 2024014668 ps
CPU time 2.73 seconds
Started Jul 11 04:28:16 PM PDT 24
Finished Jul 11 04:28:20 PM PDT 24
Peak memory 201376 kb
Host smart-7540fe99-add8-4197-b7f0-beff1d54c474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499130049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.3499130049
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.187948011
Short name T810
Test name
Test status
Simulation time 2012594275 ps
CPU time 5.64 seconds
Started Jul 11 04:28:25 PM PDT 24
Finished Jul 11 04:28:33 PM PDT 24
Peak memory 201632 kb
Host smart-355e2cec-dc46-43b9-a73d-96f785573038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187948011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_tes
t.187948011
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3077423861
Short name T889
Test name
Test status
Simulation time 2008990628 ps
CPU time 5.34 seconds
Started Jul 11 04:28:06 PM PDT 24
Finished Jul 11 04:28:24 PM PDT 24
Peak memory 201600 kb
Host smart-afdedcd6-0bab-48c3-b662-ad9907234224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077423861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.3077423861
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1224356255
Short name T799
Test name
Test status
Simulation time 2682559395 ps
CPU time 9.4 seconds
Started Jul 11 04:27:19 PM PDT 24
Finished Jul 11 04:27:30 PM PDT 24
Peak memory 201152 kb
Host smart-b7ec02d7-fd03-4256-a0e8-82bc7b021320
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224356255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_aliasing.1224356255
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.3921070513
Short name T845
Test name
Test status
Simulation time 39992162771 ps
CPU time 89.26 seconds
Started Jul 11 04:27:26 PM PDT 24
Finished Jul 11 04:28:57 PM PDT 24
Peak memory 202056 kb
Host smart-be56b4e3-92b5-4357-a507-41ec34ad254e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921070513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.3921070513
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1653165591
Short name T893
Test name
Test status
Simulation time 4060434927 ps
CPU time 3.04 seconds
Started Jul 11 04:27:30 PM PDT 24
Finished Jul 11 04:27:35 PM PDT 24
Peak memory 201760 kb
Host smart-3a9dadce-6240-47d6-870a-eb8e22bdcfe3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653165591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_hw_reset.1653165591
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1304468224
Short name T878
Test name
Test status
Simulation time 2122231106 ps
CPU time 5.72 seconds
Started Jul 11 04:27:26 PM PDT 24
Finished Jul 11 04:27:33 PM PDT 24
Peak memory 201812 kb
Host smart-a646e543-a035-422c-b575-5076fbe6e1a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304468224 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1304468224
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.79176887
Short name T33
Test name
Test status
Simulation time 2065520863 ps
CPU time 2.06 seconds
Started Jul 11 04:27:27 PM PDT 24
Finished Jul 11 04:27:38 PM PDT 24
Peak memory 201736 kb
Host smart-0f70997a-74f3-4eb6-9ce3-d9cce6a627b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79176887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw.79176887
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.798403661
Short name T898
Test name
Test status
Simulation time 2012688071 ps
CPU time 5.87 seconds
Started Jul 11 04:27:12 PM PDT 24
Finished Jul 11 04:27:19 PM PDT 24
Peak memory 201524 kb
Host smart-6185de40-dffc-4aca-a058-8cd280a4815f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798403661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test
.798403661
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2953215820
Short name T895
Test name
Test status
Simulation time 5024907628 ps
CPU time 4.06 seconds
Started Jul 11 04:27:34 PM PDT 24
Finished Jul 11 04:27:42 PM PDT 24
Peak memory 202048 kb
Host smart-fab15e64-e577-42e4-9d7b-cb1529a9e7a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953215820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.2953215820
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.157243212
Short name T297
Test name
Test status
Simulation time 2264012018 ps
CPU time 2.81 seconds
Started Jul 11 04:27:32 PM PDT 24
Finished Jul 11 04:27:39 PM PDT 24
Peak memory 202076 kb
Host smart-e6cd15f8-c3dc-4c9d-9126-6cb5e6abbd1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157243212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors
.157243212
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.1043838829
Short name T813
Test name
Test status
Simulation time 22253730157 ps
CPU time 62.54 seconds
Started Jul 11 04:27:19 PM PDT 24
Finished Jul 11 04:28:23 PM PDT 24
Peak memory 201300 kb
Host smart-cbc60643-0555-4551-844e-d39661d2a9fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043838829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_tl_intg_err.1043838829
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.757718773
Short name T795
Test name
Test status
Simulation time 2083648956 ps
CPU time 1.16 seconds
Started Jul 11 04:28:38 PM PDT 24
Finished Jul 11 04:28:40 PM PDT 24
Peak memory 201724 kb
Host smart-33b9fef6-4b63-4500-ac20-d24fe39f5287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757718773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_tes
t.757718773
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3908662014
Short name T877
Test name
Test status
Simulation time 2040389747 ps
CPU time 2.12 seconds
Started Jul 11 04:28:40 PM PDT 24
Finished Jul 11 04:28:43 PM PDT 24
Peak memory 201616 kb
Host smart-ae684656-8397-411c-89c9-1be791f0ac5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908662014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.3908662014
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.3627421401
Short name T788
Test name
Test status
Simulation time 2018977462 ps
CPU time 4.01 seconds
Started Jul 11 04:28:23 PM PDT 24
Finished Jul 11 04:28:29 PM PDT 24
Peak memory 201484 kb
Host smart-2aefb28d-caa8-4f85-a74a-71aa109b6121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627421401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.3627421401
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3393766509
Short name T867
Test name
Test status
Simulation time 2019340496 ps
CPU time 3.38 seconds
Started Jul 11 04:28:24 PM PDT 24
Finished Jul 11 04:28:30 PM PDT 24
Peak memory 201536 kb
Host smart-33c9a3ba-1080-47f4-9547-23bfbca4d01e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393766509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_te
st.3393766509
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.241273550
Short name T888
Test name
Test status
Simulation time 2012672145 ps
CPU time 5.48 seconds
Started Jul 11 04:28:16 PM PDT 24
Finished Jul 11 04:28:24 PM PDT 24
Peak memory 201636 kb
Host smart-003f2f45-134a-4248-b081-9d40fa289479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241273550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_tes
t.241273550
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1243045923
Short name T796
Test name
Test status
Simulation time 2025199768 ps
CPU time 2.08 seconds
Started Jul 11 04:28:25 PM PDT 24
Finished Jul 11 04:28:29 PM PDT 24
Peak memory 201568 kb
Host smart-3018b36d-bdbd-4894-b6d2-94a66381f0b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243045923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.1243045923
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.4015957731
Short name T791
Test name
Test status
Simulation time 2012949224 ps
CPU time 5.77 seconds
Started Jul 11 04:28:26 PM PDT 24
Finished Jul 11 04:28:34 PM PDT 24
Peak memory 201552 kb
Host smart-9f1a904a-5819-4421-bbfc-f2a7066c3cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015957731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.4015957731
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.4047691658
Short name T790
Test name
Test status
Simulation time 2050815890 ps
CPU time 1.86 seconds
Started Jul 11 04:28:22 PM PDT 24
Finished Jul 11 04:28:25 PM PDT 24
Peak memory 201516 kb
Host smart-d69264b5-6d2b-492c-962e-7601be278507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047691658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.4047691658
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1997085596
Short name T838
Test name
Test status
Simulation time 2022603144 ps
CPU time 3.05 seconds
Started Jul 11 04:28:35 PM PDT 24
Finished Jul 11 04:28:40 PM PDT 24
Peak memory 201684 kb
Host smart-2fbc31b9-cdf8-46d5-a125-764e478cb481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997085596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.1997085596
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2242234731
Short name T879
Test name
Test status
Simulation time 2027283537 ps
CPU time 1.85 seconds
Started Jul 11 04:29:22 PM PDT 24
Finished Jul 11 04:29:27 PM PDT 24
Peak memory 200944 kb
Host smart-f767613a-041b-4b3a-8288-6b2d2e6a64e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242234731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.2242234731
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1496404936
Short name T865
Test name
Test status
Simulation time 2176537570 ps
CPU time 1.46 seconds
Started Jul 11 04:27:29 PM PDT 24
Finished Jul 11 04:27:32 PM PDT 24
Peak memory 201808 kb
Host smart-328141e5-fd69-4ac1-a7be-11cd51600447
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496404936 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1496404936
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2548208716
Short name T362
Test name
Test status
Simulation time 2045460844 ps
CPU time 2.81 seconds
Started Jul 11 04:27:34 PM PDT 24
Finished Jul 11 04:27:41 PM PDT 24
Peak memory 201792 kb
Host smart-e694358d-7499-4df6-8bb8-08e5a941003d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548208716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.2548208716
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2180810510
Short name T819
Test name
Test status
Simulation time 2012604524 ps
CPU time 5.35 seconds
Started Jul 11 04:27:31 PM PDT 24
Finished Jul 11 04:27:37 PM PDT 24
Peak memory 201656 kb
Host smart-55cb25a6-892d-4925-a4c6-2043cd05b790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180810510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_tes
t.2180810510
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1359954663
Short name T806
Test name
Test status
Simulation time 9531308912 ps
CPU time 3.01 seconds
Started Jul 11 04:27:30 PM PDT 24
Finished Jul 11 04:27:34 PM PDT 24
Peak memory 202068 kb
Host smart-cacca06a-af35-4cdc-b30c-0b09d8a16987
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359954663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.1359954663
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.396548218
Short name T829
Test name
Test status
Simulation time 3354245732 ps
CPU time 2.02 seconds
Started Jul 11 04:27:15 PM PDT 24
Finished Jul 11 04:27:19 PM PDT 24
Peak memory 202096 kb
Host smart-0cc384ba-f62b-4a48-8020-c10d55d9f440
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396548218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors
.396548218
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.1601069509
Short name T814
Test name
Test status
Simulation time 22224715457 ps
CPU time 56.14 seconds
Started Jul 11 04:27:36 PM PDT 24
Finished Jul 11 04:28:35 PM PDT 24
Peak memory 202076 kb
Host smart-b6b48d0b-4be5-44cf-9fa9-f48ec763b8b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601069509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.1601069509
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2165057253
Short name T311
Test name
Test status
Simulation time 2170788005 ps
CPU time 3.81 seconds
Started Jul 11 04:28:16 PM PDT 24
Finished Jul 11 04:28:23 PM PDT 24
Peak memory 201144 kb
Host smart-85beab2f-3ef1-4d94-9ab1-823737ed74ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165057253 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2165057253
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.2753416404
Short name T837
Test name
Test status
Simulation time 2035079288 ps
CPU time 5.46 seconds
Started Jul 11 04:27:33 PM PDT 24
Finished Jul 11 04:27:41 PM PDT 24
Peak memory 201660 kb
Host smart-6d7f8f88-a23f-4a14-9c11-2fd49c70c27f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753416404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.2753416404
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.637673297
Short name T874
Test name
Test status
Simulation time 2033852968 ps
CPU time 2.3 seconds
Started Jul 11 04:27:30 PM PDT 24
Finished Jul 11 04:27:34 PM PDT 24
Peak memory 201280 kb
Host smart-e59aee8f-e78e-41a6-9682-96743477072b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637673297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test
.637673297
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3502771209
Short name T835
Test name
Test status
Simulation time 8615116046 ps
CPU time 9.07 seconds
Started Jul 11 04:27:52 PM PDT 24
Finished Jul 11 04:28:02 PM PDT 24
Peak memory 202112 kb
Host smart-86c7c6a0-0a75-42f5-8e51-c66a346ed25e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502771209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.3502771209
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3058073589
Short name T314
Test name
Test status
Simulation time 2458488338 ps
CPU time 3.62 seconds
Started Jul 11 04:27:33 PM PDT 24
Finished Jul 11 04:27:40 PM PDT 24
Peak memory 202028 kb
Host smart-0d5177c1-002e-49a6-b369-5738b438d1ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058073589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.3058073589
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3268083565
Short name T309
Test name
Test status
Simulation time 42906783905 ps
CPU time 29.12 seconds
Started Jul 11 04:27:34 PM PDT 24
Finished Jul 11 04:28:07 PM PDT 24
Peak memory 202136 kb
Host smart-9e3ecde6-7771-44b9-9868-783589984076
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268083565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.3268083565
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3912910694
Short name T826
Test name
Test status
Simulation time 2060531239 ps
CPU time 6.2 seconds
Started Jul 11 04:28:19 PM PDT 24
Finished Jul 11 04:28:27 PM PDT 24
Peak memory 201840 kb
Host smart-7247eb11-c09a-495f-8910-d37a935bbfcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912910694 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3912910694
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3546914238
Short name T364
Test name
Test status
Simulation time 2074278895 ps
CPU time 1.83 seconds
Started Jul 11 04:28:20 PM PDT 24
Finished Jul 11 04:28:24 PM PDT 24
Peak memory 201744 kb
Host smart-1ef80715-0030-4b6f-8abe-28c0c4d7ca7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546914238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.3546914238
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.3651246033
Short name T792
Test name
Test status
Simulation time 2063987026 ps
CPU time 1.44 seconds
Started Jul 11 04:27:56 PM PDT 24
Finished Jul 11 04:27:58 PM PDT 24
Peak memory 201928 kb
Host smart-983c430f-8670-4752-b39d-527555e2b3f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651246033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.3651246033
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3872173423
Short name T21
Test name
Test status
Simulation time 5520586432 ps
CPU time 2.32 seconds
Started Jul 11 04:28:06 PM PDT 24
Finished Jul 11 04:28:10 PM PDT 24
Peak memory 201296 kb
Host smart-9f992c23-ed95-40bb-bb3a-3d9b7a0d46ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872173423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.3872173423
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.3342985280
Short name T296
Test name
Test status
Simulation time 2077895920 ps
CPU time 6.75 seconds
Started Jul 11 04:28:09 PM PDT 24
Finished Jul 11 04:28:17 PM PDT 24
Peak memory 202388 kb
Host smart-5fd340e6-6c06-48c1-8283-402c5439a020
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342985280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.3342985280
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.4178465802
Short name T302
Test name
Test status
Simulation time 42453250416 ps
CPU time 116.33 seconds
Started Jul 11 04:28:17 PM PDT 24
Finished Jul 11 04:30:16 PM PDT 24
Peak memory 202100 kb
Host smart-b5723321-df2c-450c-acf4-8c10d96c977d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178465802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.4178465802
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.185585121
Short name T851
Test name
Test status
Simulation time 2223179443 ps
CPU time 2.43 seconds
Started Jul 11 04:27:57 PM PDT 24
Finished Jul 11 04:28:00 PM PDT 24
Peak memory 201920 kb
Host smart-07a93a6c-ecbb-4893-9120-bfe0732bc27f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185585121 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.185585121
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.1042081574
Short name T869
Test name
Test status
Simulation time 2172237786 ps
CPU time 1.15 seconds
Started Jul 11 04:28:10 PM PDT 24
Finished Jul 11 04:28:13 PM PDT 24
Peak memory 201884 kb
Host smart-512e2a37-f933-475a-a6a8-c1941d1f7910
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042081574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.1042081574
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.99088107
Short name T868
Test name
Test status
Simulation time 2045414817 ps
CPU time 1.89 seconds
Started Jul 11 04:27:55 PM PDT 24
Finished Jul 11 04:27:58 PM PDT 24
Peak memory 201524 kb
Host smart-099b5368-9cd6-43af-93e1-632104d87d32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99088107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test.99088107
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.2578561600
Short name T872
Test name
Test status
Simulation time 9501480946 ps
CPU time 23.11 seconds
Started Jul 11 04:28:05 PM PDT 24
Finished Jul 11 04:28:30 PM PDT 24
Peak memory 202060 kb
Host smart-1728a031-01ba-4f09-889d-449168eb1805
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578561600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.2578561600
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.2170028752
Short name T860
Test name
Test status
Simulation time 2072730332 ps
CPU time 6.77 seconds
Started Jul 11 04:28:09 PM PDT 24
Finished Jul 11 04:28:17 PM PDT 24
Peak memory 201936 kb
Host smart-daecf658-927e-4f85-8361-ea39448aa718
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170028752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.2170028752
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3446361052
Short name T830
Test name
Test status
Simulation time 42496966693 ps
CPU time 31.67 seconds
Started Jul 11 04:27:55 PM PDT 24
Finished Jul 11 04:28:28 PM PDT 24
Peak memory 202088 kb
Host smart-20c403f6-285c-41f0-b6dd-7029d00eb937
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446361052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.3446361052
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.52431704
Short name T900
Test name
Test status
Simulation time 2055213019 ps
CPU time 6.11 seconds
Started Jul 11 04:28:40 PM PDT 24
Finished Jul 11 04:28:47 PM PDT 24
Peak memory 201692 kb
Host smart-042a9bbc-3159-4c43-bcb8-0982f04fbd55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52431704 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.52431704
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3079272647
Short name T370
Test name
Test status
Simulation time 2067719718 ps
CPU time 2.11 seconds
Started Jul 11 04:28:07 PM PDT 24
Finished Jul 11 04:28:10 PM PDT 24
Peak memory 201532 kb
Host smart-857a9759-907a-4460-86d1-b4ec044293c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079272647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.3079272647
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.1596598839
Short name T857
Test name
Test status
Simulation time 2016117330 ps
CPU time 5.77 seconds
Started Jul 11 04:28:23 PM PDT 24
Finished Jul 11 04:28:31 PM PDT 24
Peak memory 201472 kb
Host smart-eaddc796-58f2-4764-b9e5-5cd37ee28f9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596598839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.1596598839
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.260599744
Short name T18
Test name
Test status
Simulation time 8132047508 ps
CPU time 40.9 seconds
Started Jul 11 04:28:10 PM PDT 24
Finished Jul 11 04:28:53 PM PDT 24
Peak memory 202068 kb
Host smart-50e76afc-40b6-414e-9c09-1f1c3409b0e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260599744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
sysrst_ctrl_same_csr_outstanding.260599744
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2394446808
Short name T906
Test name
Test status
Simulation time 2109356180 ps
CPU time 3.79 seconds
Started Jul 11 04:28:15 PM PDT 24
Finished Jul 11 04:28:21 PM PDT 24
Peak memory 201940 kb
Host smart-6bb6a1fe-5921-45c8-bb76-2539b19dc5a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394446808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.2394446808
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.133020134
Short name T850
Test name
Test status
Simulation time 42482852337 ps
CPU time 113.14 seconds
Started Jul 11 04:27:58 PM PDT 24
Finished Jul 11 04:29:53 PM PDT 24
Peak memory 202068 kb
Host smart-43a388f7-6fd5-4963-a793-c56704bea39f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133020134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_tl_intg_err.133020134
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.657063304
Short name T541
Test name
Test status
Simulation time 2015684321 ps
CPU time 5.7 seconds
Started Jul 11 04:52:39 PM PDT 24
Finished Jul 11 04:52:55 PM PDT 24
Peak memory 201480 kb
Host smart-c70f1368-e8b6-4797-a05a-c9af071052bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657063304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test
.657063304
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.206837723
Short name T252
Test name
Test status
Simulation time 3323869269 ps
CPU time 9.11 seconds
Started Jul 11 04:52:39 PM PDT 24
Finished Jul 11 04:52:58 PM PDT 24
Peak memory 201652 kb
Host smart-53658f22-ac1c-48f4-b2c8-91bbe7ddbe17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206837723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.206837723
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.620648334
Short name T233
Test name
Test status
Simulation time 2444929031 ps
CPU time 1.34 seconds
Started Jul 11 04:52:43 PM PDT 24
Finished Jul 11 04:52:52 PM PDT 24
Peak memory 201620 kb
Host smart-8f66aae0-2afd-4183-a17f-ed52cd3f7f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620648334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.620648334
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2610660624
Short name T721
Test name
Test status
Simulation time 2270069895 ps
CPU time 2.04 seconds
Started Jul 11 04:52:44 PM PDT 24
Finished Jul 11 04:52:54 PM PDT 24
Peak memory 201588 kb
Host smart-e36e2fd0-f73e-43c4-b9de-f6a649a0fcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610660624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2610660624
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1254985533
Short name T3
Test name
Test status
Simulation time 38428406027 ps
CPU time 52.01 seconds
Started Jul 11 04:52:40 PM PDT 24
Finished Jul 11 04:53:41 PM PDT 24
Peak memory 201888 kb
Host smart-8fa7adf2-ec69-472b-a26f-01636e8222eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254985533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.1254985533
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.1212117055
Short name T775
Test name
Test status
Simulation time 2515253759 ps
CPU time 2.7 seconds
Started Jul 11 04:52:39 PM PDT 24
Finished Jul 11 04:52:51 PM PDT 24
Peak memory 201564 kb
Host smart-233ace8a-4afe-4b90-9872-0b008c7a702e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212117055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ec_pwr_on_rst.1212117055
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.239845940
Short name T203
Test name
Test status
Simulation time 2635936133 ps
CPU time 2.32 seconds
Started Jul 11 04:52:39 PM PDT 24
Finished Jul 11 04:52:51 PM PDT 24
Peak memory 201560 kb
Host smart-3dd57747-b65f-430b-b6c1-52a079c0edc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239845940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.239845940
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.1943413225
Short name T473
Test name
Test status
Simulation time 2473862450 ps
CPU time 4.77 seconds
Started Jul 11 04:52:44 PM PDT 24
Finished Jul 11 04:52:56 PM PDT 24
Peak memory 201620 kb
Host smart-b50ad7e1-6d72-4035-b85b-cac850ea1d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943413225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.1943413225
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.557303628
Short name T779
Test name
Test status
Simulation time 2107146467 ps
CPU time 6.27 seconds
Started Jul 11 04:52:41 PM PDT 24
Finished Jul 11 04:52:56 PM PDT 24
Peak memory 201516 kb
Host smart-62a30704-a991-42ad-85bd-5efdbf74ae4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557303628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.557303628
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.1520644491
Short name T294
Test name
Test status
Simulation time 42023004851 ps
CPU time 55.76 seconds
Started Jul 11 04:52:39 PM PDT 24
Finished Jul 11 04:53:44 PM PDT 24
Peak memory 221720 kb
Host smart-045af096-7181-480c-9ce5-ab30f2082a76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520644491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.1520644491
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.3643530134
Short name T699
Test name
Test status
Simulation time 2136000976 ps
CPU time 2.08 seconds
Started Jul 11 04:52:34 PM PDT 24
Finished Jul 11 04:52:47 PM PDT 24
Peak memory 201476 kb
Host smart-0e61cac5-7afb-40af-a7a1-345940b72168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643530134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.3643530134
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.3621151782
Short name T47
Test name
Test status
Simulation time 8194900872 ps
CPU time 4.82 seconds
Started Jul 11 04:52:42 PM PDT 24
Finished Jul 11 04:52:55 PM PDT 24
Peak memory 201648 kb
Host smart-03152509-8f7f-4926-bb13-39d262f440d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621151782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.3621151782
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.4289768061
Short name T329
Test name
Test status
Simulation time 246019684119 ps
CPU time 46.61 seconds
Started Jul 11 04:52:40 PM PDT 24
Finished Jul 11 04:53:36 PM PDT 24
Peak memory 210164 kb
Host smart-3dfec6b7-afef-4d68-a5aa-7622097aa549
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289768061 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.4289768061
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.466477291
Short name T535
Test name
Test status
Simulation time 2025269721 ps
CPU time 2.02 seconds
Started Jul 11 04:52:50 PM PDT 24
Finished Jul 11 04:52:58 PM PDT 24
Peak memory 201636 kb
Host smart-0a89dcbf-be8c-40f9-a211-936946272531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466477291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test
.466477291
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1300365315
Short name T211
Test name
Test status
Simulation time 3488812873 ps
CPU time 9.39 seconds
Started Jul 11 04:52:53 PM PDT 24
Finished Jul 11 04:53:08 PM PDT 24
Peak memory 201696 kb
Host smart-a48c4474-b245-4fd8-8fa0-10c4247f3f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300365315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.1300365315
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.1541489682
Short name T375
Test name
Test status
Simulation time 109885536235 ps
CPU time 142.67 seconds
Started Jul 11 04:52:40 PM PDT 24
Finished Jul 11 04:55:12 PM PDT 24
Peak memory 202136 kb
Host smart-2af3deb7-2edd-41be-927b-ca6c6204ce54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541489682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_combo_detect.1541489682
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.1838822157
Short name T601
Test name
Test status
Simulation time 2171112561 ps
CPU time 3.34 seconds
Started Jul 11 04:52:37 PM PDT 24
Finished Jul 11 04:52:50 PM PDT 24
Peak memory 201636 kb
Host smart-18c79a12-0b1a-41fd-9503-4ec3813c429f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838822157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.1838822157
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3377797374
Short name T769
Test name
Test status
Simulation time 2274321203 ps
CPU time 3.54 seconds
Started Jul 11 04:52:41 PM PDT 24
Finished Jul 11 04:52:53 PM PDT 24
Peak memory 201504 kb
Host smart-65596d58-6202-406c-8c98-e0dc5f2d39a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377797374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3377797374
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.2814788882
Short name T737
Test name
Test status
Simulation time 60123208015 ps
CPU time 73.99 seconds
Started Jul 11 04:52:48 PM PDT 24
Finished Jul 11 04:54:09 PM PDT 24
Peak memory 201868 kb
Host smart-29ff3b53-9481-492e-bd94-5eb3b62281c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814788882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.2814788882
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.22201743
Short name T52
Test name
Test status
Simulation time 3599056794 ps
CPU time 5.08 seconds
Started Jul 11 04:52:38 PM PDT 24
Finished Jul 11 04:52:53 PM PDT 24
Peak memory 201480 kb
Host smart-f4c5a9b6-3316-4a5c-a5c3-78b1fa010a85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22201743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_ec_pwr_on_rst.22201743
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.1183441585
Short name T180
Test name
Test status
Simulation time 4281676983 ps
CPU time 3.01 seconds
Started Jul 11 04:52:39 PM PDT 24
Finished Jul 11 04:52:52 PM PDT 24
Peak memory 201540 kb
Host smart-81cc93dc-6b25-4409-8382-a00361bd0668
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183441585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.1183441585
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.3988563191
Short name T482
Test name
Test status
Simulation time 2623500555 ps
CPU time 2.34 seconds
Started Jul 11 04:52:39 PM PDT 24
Finished Jul 11 04:52:51 PM PDT 24
Peak memory 201860 kb
Host smart-eefa68a9-3915-4ea7-aeab-9c954b44d460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988563191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.3988563191
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.4091142956
Short name T577
Test name
Test status
Simulation time 2082382648 ps
CPU time 5.56 seconds
Started Jul 11 04:52:39 PM PDT 24
Finished Jul 11 04:52:54 PM PDT 24
Peak memory 201480 kb
Host smart-a3d92b3d-9577-49a0-a941-7afc8569db00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091142956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.4091142956
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.1536243399
Short name T635
Test name
Test status
Simulation time 2508624242 ps
CPU time 7.23 seconds
Started Jul 11 04:52:39 PM PDT 24
Finished Jul 11 04:52:56 PM PDT 24
Peak memory 201864 kb
Host smart-2e7f6d14-3933-4c9d-bb9d-b79ff88573af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536243399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.1536243399
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.2486695758
Short name T316
Test name
Test status
Simulation time 22178564059 ps
CPU time 9.34 seconds
Started Jul 11 04:52:47 PM PDT 24
Finished Jul 11 04:53:03 PM PDT 24
Peak memory 221216 kb
Host smart-5c09ba0d-d32d-45ff-a85c-3367f4e31d44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486695758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.2486695758
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.2655376231
Short name T342
Test name
Test status
Simulation time 2111342431 ps
CPU time 5.61 seconds
Started Jul 11 04:52:38 PM PDT 24
Finished Jul 11 04:52:53 PM PDT 24
Peak memory 201536 kb
Host smart-e5948c00-2b93-4b2d-85ea-98e011acd794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655376231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.2655376231
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.457407344
Short name T95
Test name
Test status
Simulation time 7731731549 ps
CPU time 4.11 seconds
Started Jul 11 04:52:38 PM PDT 24
Finished Jul 11 04:52:52 PM PDT 24
Peak memory 201512 kb
Host smart-703dba9f-d6d2-4d27-b726-ac491544c3fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457407344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_ultra_low_pwr.457407344
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.1137159171
Short name T446
Test name
Test status
Simulation time 2024922244 ps
CPU time 3.21 seconds
Started Jul 11 04:53:10 PM PDT 24
Finished Jul 11 04:53:20 PM PDT 24
Peak memory 201500 kb
Host smart-93040c04-6b68-4d61-9182-556de138c91e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137159171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.1137159171
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2149612806
Short name T677
Test name
Test status
Simulation time 3721104365 ps
CPU time 3.07 seconds
Started Jul 11 04:53:04 PM PDT 24
Finished Jul 11 04:53:13 PM PDT 24
Peak memory 201596 kb
Host smart-84bbad24-edd4-43ea-91fa-fd1b8c3365e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149612806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.2
149612806
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.444743677
Short name T272
Test name
Test status
Simulation time 35745322725 ps
CPU time 85.47 seconds
Started Jul 11 04:53:03 PM PDT 24
Finished Jul 11 04:54:34 PM PDT 24
Peak memory 201804 kb
Host smart-46ec2d28-af4c-42b4-b860-a749dc052ff4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444743677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_combo_detect.444743677
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.4013653196
Short name T724
Test name
Test status
Simulation time 3327997854 ps
CPU time 3.6 seconds
Started Jul 11 04:53:05 PM PDT 24
Finished Jul 11 04:53:14 PM PDT 24
Peak memory 201480 kb
Host smart-a4ff67db-c960-46b6-8d3c-0863ba0ae7cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013653196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.4013653196
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.4216250113
Short name T146
Test name
Test status
Simulation time 3273078084 ps
CPU time 5.62 seconds
Started Jul 11 04:53:07 PM PDT 24
Finished Jul 11 04:53:19 PM PDT 24
Peak memory 201528 kb
Host smart-cf7a485b-e677-465c-8ced-de04171d5ec5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216250113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_edge_detect.4216250113
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.1420957840
Short name T484
Test name
Test status
Simulation time 2630597609 ps
CPU time 2.35 seconds
Started Jul 11 04:53:07 PM PDT 24
Finished Jul 11 04:53:15 PM PDT 24
Peak memory 201632 kb
Host smart-b5e1df1b-b220-4627-9be8-57f48a271192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420957840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.1420957840
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.3025236345
Short name T500
Test name
Test status
Simulation time 2471268706 ps
CPU time 2.26 seconds
Started Jul 11 04:53:11 PM PDT 24
Finished Jul 11 04:53:20 PM PDT 24
Peak memory 201484 kb
Host smart-0d3d3e88-5b01-48b2-b1b0-40c0d72463ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025236345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.3025236345
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3705332986
Short name T639
Test name
Test status
Simulation time 2177991747 ps
CPU time 1.94 seconds
Started Jul 11 04:53:09 PM PDT 24
Finished Jul 11 04:53:17 PM PDT 24
Peak memory 201524 kb
Host smart-61157894-6653-492c-8073-f7f4122cb163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705332986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.3705332986
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.3341161021
Short name T701
Test name
Test status
Simulation time 2526611112 ps
CPU time 2.21 seconds
Started Jul 11 04:53:02 PM PDT 24
Finished Jul 11 04:53:10 PM PDT 24
Peak memory 201632 kb
Host smart-1fc2d67f-e8cc-4bd4-9a47-9bf18ede3f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341161021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.3341161021
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.688350556
Short name T501
Test name
Test status
Simulation time 2108575012 ps
CPU time 5.96 seconds
Started Jul 11 04:54:18 PM PDT 24
Finished Jul 11 04:54:32 PM PDT 24
Peak memory 201488 kb
Host smart-cefe340b-23db-4201-9853-f9d399e28d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688350556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.688350556
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.1400709359
Short name T780
Test name
Test status
Simulation time 7119884648 ps
CPU time 17.79 seconds
Started Jul 11 04:53:07 PM PDT 24
Finished Jul 11 04:53:30 PM PDT 24
Peak memory 201544 kb
Host smart-798f71ee-2187-41a8-8bda-edc66f5f7b23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400709359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.1400709359
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1032620849
Short name T24
Test name
Test status
Simulation time 33313210063 ps
CPU time 82.36 seconds
Started Jul 11 04:53:03 PM PDT 24
Finished Jul 11 04:54:31 PM PDT 24
Peak memory 218360 kb
Host smart-ac7fbd1c-c744-40fb-a427-062157fac6cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032620849 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.1032620849
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.4185966529
Short name T136
Test name
Test status
Simulation time 8388742096 ps
CPU time 7.09 seconds
Started Jul 11 04:53:05 PM PDT 24
Finished Jul 11 04:53:18 PM PDT 24
Peak memory 201552 kb
Host smart-c2d1e090-84de-46f2-95a7-8d3941236a30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185966529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.4185966529
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.1395564966
Short name T483
Test name
Test status
Simulation time 2032196856 ps
CPU time 1.93 seconds
Started Jul 11 04:53:08 PM PDT 24
Finished Jul 11 04:53:16 PM PDT 24
Peak memory 201540 kb
Host smart-cdd61c48-e1e2-43bc-a740-92976aed8b81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395564966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.1395564966
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2543569250
Short name T630
Test name
Test status
Simulation time 2917329995 ps
CPU time 2.4 seconds
Started Jul 11 04:53:12 PM PDT 24
Finished Jul 11 04:53:21 PM PDT 24
Peak memory 201708 kb
Host smart-39db993a-4683-4d3e-906d-6bd41f528c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543569250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.2
543569250
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.651909249
Short name T235
Test name
Test status
Simulation time 67730633382 ps
CPU time 44.69 seconds
Started Jul 11 04:53:10 PM PDT 24
Finished Jul 11 04:54:01 PM PDT 24
Peak memory 201784 kb
Host smart-1e840d4b-c8fb-4999-8e59-5c41a1f34281
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651909249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_combo_detect.651909249
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.4045348845
Short name T120
Test name
Test status
Simulation time 3696527796 ps
CPU time 2.89 seconds
Started Jul 11 04:53:07 PM PDT 24
Finished Jul 11 04:53:16 PM PDT 24
Peak memory 201504 kb
Host smart-a6db05e1-37ba-4815-81f1-0c267f29ef76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045348845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ec_pwr_on_rst.4045348845
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.905838288
Short name T218
Test name
Test status
Simulation time 3051520886 ps
CPU time 3.11 seconds
Started Jul 11 04:53:10 PM PDT 24
Finished Jul 11 04:53:20 PM PDT 24
Peak memory 201504 kb
Host smart-d323362b-34e5-423e-aefc-0aa031b67b22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905838288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctr
l_edge_detect.905838288
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.2313855540
Short name T69
Test name
Test status
Simulation time 2626863854 ps
CPU time 2.58 seconds
Started Jul 11 04:53:12 PM PDT 24
Finished Jul 11 04:53:21 PM PDT 24
Peak memory 201644 kb
Host smart-146cd4af-a6d9-4858-a6ee-ed0e12c010f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313855540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.2313855540
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.3558281143
Short name T653
Test name
Test status
Simulation time 2470549479 ps
CPU time 6.91 seconds
Started Jul 11 04:53:06 PM PDT 24
Finished Jul 11 04:53:18 PM PDT 24
Peak memory 201560 kb
Host smart-d81159c8-dfcb-4c12-944e-45bc81c5526d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558281143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.3558281143
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.1672553222
Short name T262
Test name
Test status
Simulation time 2171740308 ps
CPU time 1.99 seconds
Started Jul 11 04:53:14 PM PDT 24
Finished Jul 11 04:53:24 PM PDT 24
Peak memory 201464 kb
Host smart-f26f6700-76a0-4b9a-a640-04cea1c02720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672553222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.1672553222
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.3692444316
Short name T133
Test name
Test status
Simulation time 2524874129 ps
CPU time 2.46 seconds
Started Jul 11 04:53:08 PM PDT 24
Finished Jul 11 04:53:17 PM PDT 24
Peak memory 201564 kb
Host smart-51ea0225-a274-4bd0-90a8-1b0c504eea18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692444316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.3692444316
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.104254923
Short name T57
Test name
Test status
Simulation time 2135773312 ps
CPU time 1.88 seconds
Started Jul 11 04:53:09 PM PDT 24
Finished Jul 11 04:53:17 PM PDT 24
Peak memory 201524 kb
Host smart-a9c0e2a2-2550-4a50-97dc-3cce8ef3cd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104254923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.104254923
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.2813883835
Short name T733
Test name
Test status
Simulation time 6502602081 ps
CPU time 18.12 seconds
Started Jul 11 04:53:10 PM PDT 24
Finished Jul 11 04:53:35 PM PDT 24
Peak memory 201600 kb
Host smart-82734d7d-edaf-44c0-9ab2-e676251bb242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813883835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s
tress_all.2813883835
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.377272328
Short name T430
Test name
Test status
Simulation time 2026617687 ps
CPU time 1.96 seconds
Started Jul 11 04:53:16 PM PDT 24
Finished Jul 11 04:53:25 PM PDT 24
Peak memory 201520 kb
Host smart-f725b709-54bd-4302-8ad8-c8ffe19867d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377272328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_tes
t.377272328
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.503290056
Short name T520
Test name
Test status
Simulation time 3607209081 ps
CPU time 10.08 seconds
Started Jul 11 04:58:11 PM PDT 24
Finished Jul 11 04:58:32 PM PDT 24
Peak memory 201708 kb
Host smart-ecfec9fd-da8f-46df-9a14-f5f620accb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503290056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.503290056
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.3058900376
Short name T425
Test name
Test status
Simulation time 3769238599 ps
CPU time 10.59 seconds
Started Jul 11 04:53:19 PM PDT 24
Finished Jul 11 04:53:38 PM PDT 24
Peak memory 201604 kb
Host smart-9a1ea450-f0c0-4e57-9c71-b443acf936ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058900376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ec_pwr_on_rst.3058900376
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.3734939249
Short name T148
Test name
Test status
Simulation time 3354192941 ps
CPU time 2.51 seconds
Started Jul 11 04:53:14 PM PDT 24
Finished Jul 11 04:53:23 PM PDT 24
Peak memory 201532 kb
Host smart-96548527-dc59-4866-8747-97ceebe4fddd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734939249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.3734939249
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.2393317927
Short name T175
Test name
Test status
Simulation time 2612925879 ps
CPU time 7.22 seconds
Started Jul 11 04:53:16 PM PDT 24
Finished Jul 11 04:53:31 PM PDT 24
Peak memory 201528 kb
Host smart-1bfa09c7-7d9b-4468-b506-260a2eca3f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393317927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.2393317927
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.1351349537
Short name T675
Test name
Test status
Simulation time 2511440521 ps
CPU time 1.4 seconds
Started Jul 11 04:53:10 PM PDT 24
Finished Jul 11 04:53:18 PM PDT 24
Peak memory 201644 kb
Host smart-fdd274d3-6e94-440d-80bc-1d8b0a11bdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351349537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.1351349537
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.4223348766
Short name T558
Test name
Test status
Simulation time 2254146282 ps
CPU time 6.32 seconds
Started Jul 11 04:53:09 PM PDT 24
Finished Jul 11 04:53:21 PM PDT 24
Peak memory 201572 kb
Host smart-40a5cdd7-516d-4317-9436-2a04af322162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223348766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.4223348766
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.3212273937
Short name T431
Test name
Test status
Simulation time 2513541162 ps
CPU time 7.41 seconds
Started Jul 11 04:53:10 PM PDT 24
Finished Jul 11 04:53:24 PM PDT 24
Peak memory 201860 kb
Host smart-8ae3f893-bcb6-482a-8bbf-15f6802d82e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212273937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.3212273937
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.1454253251
Short name T452
Test name
Test status
Simulation time 2119622062 ps
CPU time 3.24 seconds
Started Jul 11 04:53:09 PM PDT 24
Finished Jul 11 04:53:19 PM PDT 24
Peak memory 201744 kb
Host smart-02309a2d-1016-47ee-9d60-aee23a0e79b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454253251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.1454253251
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.4161546350
Short name T187
Test name
Test status
Simulation time 14467027518 ps
CPU time 24.12 seconds
Started Jul 11 04:53:19 PM PDT 24
Finished Jul 11 04:53:52 PM PDT 24
Peak memory 201672 kb
Host smart-46893520-7e36-4a7f-a8aa-e1c418371958
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161546350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_s
tress_all.4161546350
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.869047193
Short name T670
Test name
Test status
Simulation time 9959253743 ps
CPU time 2.97 seconds
Started Jul 11 04:53:14 PM PDT 24
Finished Jul 11 04:53:25 PM PDT 24
Peak memory 201572 kb
Host smart-202c5062-becd-4ac2-9ceb-99be88ba4433
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869047193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_ultra_low_pwr.869047193
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.2427385975
Short name T651
Test name
Test status
Simulation time 2016765716 ps
CPU time 3.24 seconds
Started Jul 11 04:53:13 PM PDT 24
Finished Jul 11 04:53:23 PM PDT 24
Peak memory 201528 kb
Host smart-bca4400f-9cfe-4bfe-9641-013df63928cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427385975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.2427385975
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2169804093
Short name T28
Test name
Test status
Simulation time 2972424410 ps
CPU time 2.54 seconds
Started Jul 11 04:53:14 PM PDT 24
Finished Jul 11 04:53:23 PM PDT 24
Peak memory 201620 kb
Host smart-7de09f3e-70b3-42e5-87b5-03e30de7ce0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169804093 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.2
169804093
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.1641846300
Short name T105
Test name
Test status
Simulation time 37540737746 ps
CPU time 24.61 seconds
Started Jul 11 04:53:13 PM PDT 24
Finished Jul 11 04:53:45 PM PDT 24
Peak memory 201780 kb
Host smart-536c5594-a76f-4912-b1b4-2f1559c87499
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641846300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.1641846300
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.4044602649
Short name T289
Test name
Test status
Simulation time 2781925003 ps
CPU time 7.56 seconds
Started Jul 11 04:53:11 PM PDT 24
Finished Jul 11 04:53:25 PM PDT 24
Peak memory 201608 kb
Host smart-73fd9104-79e5-4b96-bdad-34044aace168
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044602649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.4044602649
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.2249987776
Short name T595
Test name
Test status
Simulation time 2638996968 ps
CPU time 1.53 seconds
Started Jul 11 04:53:17 PM PDT 24
Finished Jul 11 04:53:27 PM PDT 24
Peak memory 201624 kb
Host smart-e9ae0d1e-129c-4dc0-96bc-a2eab6854737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249987776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.2249987776
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.662407217
Short name T178
Test name
Test status
Simulation time 2455638240 ps
CPU time 4.94 seconds
Started Jul 11 04:53:09 PM PDT 24
Finished Jul 11 04:53:20 PM PDT 24
Peak memory 201600 kb
Host smart-88dfcbc4-4d2b-40c1-8d27-a661b6e29a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662407217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.662407217
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.753823100
Short name T130
Test name
Test status
Simulation time 2214534401 ps
CPU time 1.63 seconds
Started Jul 11 04:53:10 PM PDT 24
Finished Jul 11 04:53:18 PM PDT 24
Peak memory 201640 kb
Host smart-4f440b86-ca70-460f-be2b-2ce94f6006b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753823100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.753823100
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.1767896150
Short name T424
Test name
Test status
Simulation time 2535076175 ps
CPU time 2.23 seconds
Started Jul 11 04:53:07 PM PDT 24
Finished Jul 11 04:53:15 PM PDT 24
Peak memory 201524 kb
Host smart-35808307-b8ef-4170-a802-d2be4f7247dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767896150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.1767896150
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.2097850724
Short name T115
Test name
Test status
Simulation time 2134366556 ps
CPU time 1.92 seconds
Started Jul 11 04:53:13 PM PDT 24
Finished Jul 11 04:53:21 PM PDT 24
Peak memory 201396 kb
Host smart-f6ef7270-646b-4767-9663-54f3eb0c5071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097850724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.2097850724
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.3404032834
Short name T67
Test name
Test status
Simulation time 6671472651 ps
CPU time 5.2 seconds
Started Jul 11 04:53:11 PM PDT 24
Finished Jul 11 04:53:23 PM PDT 24
Peak memory 201508 kb
Host smart-085af822-59ce-44aa-99f1-d39133dde74c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404032834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_s
tress_all.3404032834
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.587766010
Short name T341
Test name
Test status
Simulation time 60621866066 ps
CPU time 148.61 seconds
Started Jul 11 04:53:09 PM PDT 24
Finished Jul 11 04:55:44 PM PDT 24
Peak memory 210320 kb
Host smart-e2f138c6-5c95-470a-9fd2-17e5b2579cc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587766010 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.587766010
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.233204657
Short name T691
Test name
Test status
Simulation time 2061445296 ps
CPU time 1.37 seconds
Started Jul 11 04:53:16 PM PDT 24
Finished Jul 11 04:53:25 PM PDT 24
Peak memory 201520 kb
Host smart-3e5f7927-57da-4023-9e29-213365f044ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233204657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_tes
t.233204657
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2119923536
Short name T515
Test name
Test status
Simulation time 283795245852 ps
CPU time 198.74 seconds
Started Jul 11 04:53:15 PM PDT 24
Finished Jul 11 04:56:41 PM PDT 24
Peak memory 201596 kb
Host smart-fd337e26-d4a0-4de9-9809-336ed922c180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119923536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.2
119923536
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.3917919401
Short name T102
Test name
Test status
Simulation time 19683882793 ps
CPU time 12.65 seconds
Started Jul 11 04:53:16 PM PDT 24
Finished Jul 11 04:53:36 PM PDT 24
Peak memory 201720 kb
Host smart-20bea090-7c9a-4ab5-b3da-c0980226ee3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917919401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.3917919401
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.3509699117
Short name T585
Test name
Test status
Simulation time 36033846366 ps
CPU time 98.24 seconds
Started Jul 11 04:53:15 PM PDT 24
Finished Jul 11 04:55:01 PM PDT 24
Peak memory 201832 kb
Host smart-5152f715-3cae-4b72-85ae-150ff93a5a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509699117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w
ith_pre_cond.3509699117
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.20200824
Short name T415
Test name
Test status
Simulation time 3970735114 ps
CPU time 1.92 seconds
Started Jul 11 04:53:16 PM PDT 24
Finished Jul 11 04:53:25 PM PDT 24
Peak memory 201496 kb
Host smart-8eb7a924-56ea-4e53-be82-6694ea9fb274
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20200824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_ec_pwr_on_rst.20200824
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.2559173264
Short name T199
Test name
Test status
Simulation time 4183272742 ps
CPU time 8.85 seconds
Started Jul 11 04:53:18 PM PDT 24
Finished Jul 11 04:53:34 PM PDT 24
Peak memory 201568 kb
Host smart-75e1c01a-d363-441f-b3d2-181a3f6cf068
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559173264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_edge_detect.2559173264
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.3768600050
Short name T244
Test name
Test status
Simulation time 2701585955 ps
CPU time 1.21 seconds
Started Jul 11 04:53:28 PM PDT 24
Finished Jul 11 04:53:38 PM PDT 24
Peak memory 201636 kb
Host smart-ca76212c-bfb5-47b4-b2ad-7b416ade66d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768600050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.3768600050
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.2003369150
Short name T599
Test name
Test status
Simulation time 2481911546 ps
CPU time 3.75 seconds
Started Jul 11 04:53:15 PM PDT 24
Finished Jul 11 04:53:26 PM PDT 24
Peak memory 201528 kb
Host smart-582088d0-5327-4c46-a59e-6e69f0b6e602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003369150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.2003369150
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.2942635214
Short name T760
Test name
Test status
Simulation time 2048407300 ps
CPU time 5.86 seconds
Started Jul 11 04:53:13 PM PDT 24
Finished Jul 11 04:53:26 PM PDT 24
Peak memory 201508 kb
Host smart-1f02d29e-df46-496d-8f9b-0b3337b489c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942635214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.2942635214
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.686163330
Short name T344
Test name
Test status
Simulation time 2586787836 ps
CPU time 1.33 seconds
Started Jul 11 04:53:10 PM PDT 24
Finished Jul 11 04:53:18 PM PDT 24
Peak memory 201640 kb
Host smart-fd8f73b3-0d31-477d-8c91-a7cb0b4245f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686163330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.686163330
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.480506725
Short name T727
Test name
Test status
Simulation time 2152238880 ps
CPU time 1.47 seconds
Started Jul 11 04:53:09 PM PDT 24
Finished Jul 11 04:53:16 PM PDT 24
Peak memory 201480 kb
Host smart-85b98841-a3c8-42f5-91ce-420456d8f6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480506725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.480506725
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.2756452218
Short name T407
Test name
Test status
Simulation time 261976056602 ps
CPU time 26.68 seconds
Started Jul 11 04:53:18 PM PDT 24
Finished Jul 11 04:53:52 PM PDT 24
Peak memory 201680 kb
Host smart-d8c10481-fbcf-4244-8f50-6f68f48815ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756452218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.2756452218
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.720400580
Short name T126
Test name
Test status
Simulation time 9706505274 ps
CPU time 2.86 seconds
Started Jul 11 04:53:17 PM PDT 24
Finished Jul 11 04:53:28 PM PDT 24
Peak memory 201652 kb
Host smart-a74c9b95-0c8b-4fec-8d78-16d57c39cc5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720400580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_ultra_low_pwr.720400580
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.966105510
Short name T509
Test name
Test status
Simulation time 2047759132 ps
CPU time 1.94 seconds
Started Jul 11 04:53:18 PM PDT 24
Finished Jul 11 04:53:28 PM PDT 24
Peak memory 201496 kb
Host smart-5cbf6bd1-05bc-4e88-9bec-01f0deaa55ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966105510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_tes
t.966105510
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2106305180
Short name T440
Test name
Test status
Simulation time 3677544858 ps
CPU time 9.35 seconds
Started Jul 11 04:53:16 PM PDT 24
Finished Jul 11 04:53:33 PM PDT 24
Peak memory 201616 kb
Host smart-2e06f763-65a3-4f89-bed8-45055bc9740c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106305180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2
106305180
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.2672396918
Short name T83
Test name
Test status
Simulation time 179700858144 ps
CPU time 249.83 seconds
Started Jul 11 04:53:14 PM PDT 24
Finished Jul 11 04:57:31 PM PDT 24
Peak memory 201896 kb
Host smart-8691293b-a7c4-4783-9bb5-30b5b6b68926
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672396918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.2672396918
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.817999737
Short name T629
Test name
Test status
Simulation time 4003440887 ps
CPU time 1.34 seconds
Started Jul 11 04:53:15 PM PDT 24
Finished Jul 11 04:53:24 PM PDT 24
Peak memory 201512 kb
Host smart-c552bcbf-1260-405c-94b7-5ad0ecacb780
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817999737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_ec_pwr_on_rst.817999737
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.4086055611
Short name T522
Test name
Test status
Simulation time 2606566625 ps
CPU time 2.43 seconds
Started Jul 11 04:53:28 PM PDT 24
Finished Jul 11 04:53:39 PM PDT 24
Peak memory 201620 kb
Host smart-ba1ccbd2-e441-4e8f-8c87-95494d0a184d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086055611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.4086055611
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.951366315
Short name T778
Test name
Test status
Simulation time 2733473703 ps
CPU time 1.02 seconds
Started Jul 11 04:53:19 PM PDT 24
Finished Jul 11 04:53:28 PM PDT 24
Peak memory 201508 kb
Host smart-8e3dfee7-a847-4e36-9892-fa7a00d61789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951366315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.951366315
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.1545060919
Short name T234
Test name
Test status
Simulation time 2468670518 ps
CPU time 2.04 seconds
Started Jul 11 04:53:18 PM PDT 24
Finished Jul 11 04:53:28 PM PDT 24
Peak memory 201532 kb
Host smart-313b1f8e-a1e0-48e6-ae1f-ec0a59f9e08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545060919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.1545060919
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.3241550539
Short name T14
Test name
Test status
Simulation time 2132676888 ps
CPU time 6.13 seconds
Started Jul 11 04:53:15 PM PDT 24
Finished Jul 11 04:53:29 PM PDT 24
Peak memory 201488 kb
Host smart-47e8a8c1-73ce-4265-93d0-47703f0a1120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241550539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.3241550539
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.1915379476
Short name T642
Test name
Test status
Simulation time 2538518196 ps
CPU time 2.39 seconds
Started Jul 11 04:53:19 PM PDT 24
Finished Jul 11 04:53:29 PM PDT 24
Peak memory 201596 kb
Host smart-37f5cb23-7b01-416b-9850-619d0d4aec7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915379476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.1915379476
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.4271292865
Short name T471
Test name
Test status
Simulation time 2110984450 ps
CPU time 5.69 seconds
Started Jul 11 04:53:20 PM PDT 24
Finished Jul 11 04:53:34 PM PDT 24
Peak memory 201460 kb
Host smart-f07d7ee7-e58d-4f21-87a6-4b221e61b5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271292865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.4271292865
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.1146952528
Short name T242
Test name
Test status
Simulation time 15316253277 ps
CPU time 11.72 seconds
Started Jul 11 04:53:18 PM PDT 24
Finished Jul 11 04:53:37 PM PDT 24
Peak memory 201504 kb
Host smart-b3783766-a811-4f74-b89a-03f7d10761e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146952528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.1146952528
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.3190549871
Short name T56
Test name
Test status
Simulation time 111536242930 ps
CPU time 69.96 seconds
Started Jul 11 04:53:22 PM PDT 24
Finished Jul 11 04:54:40 PM PDT 24
Peak memory 218376 kb
Host smart-c35890a0-9166-4c59-b8db-87d106838c5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190549871 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.3190549871
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1301956377
Short name T141
Test name
Test status
Simulation time 13531651568 ps
CPU time 2.69 seconds
Started Jul 11 04:53:15 PM PDT 24
Finished Jul 11 04:53:25 PM PDT 24
Peak memory 201612 kb
Host smart-e7ed035a-7896-4ed7-baac-6f9a449f60a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301956377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.1301956377
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.509425682
Short name T409
Test name
Test status
Simulation time 2023354779 ps
CPU time 1.82 seconds
Started Jul 11 04:53:15 PM PDT 24
Finished Jul 11 04:53:24 PM PDT 24
Peak memory 201524 kb
Host smart-8e9d22ec-94a1-446c-95d4-55951176500c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509425682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_tes
t.509425682
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1418986333
Short name T96
Test name
Test status
Simulation time 3032112556 ps
CPU time 8.42 seconds
Started Jul 11 04:53:13 PM PDT 24
Finished Jul 11 04:53:28 PM PDT 24
Peak memory 201540 kb
Host smart-c397fb77-7c6b-4874-ace7-5c2d7af7b4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418986333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.1
418986333
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.1290850826
Short name T395
Test name
Test status
Simulation time 101959204123 ps
CPU time 246.69 seconds
Started Jul 11 04:53:22 PM PDT 24
Finished Jul 11 04:57:37 PM PDT 24
Peak memory 201820 kb
Host smart-da9c3f5a-c938-4769-9daa-41107c620eaa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290850826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.1290850826
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2381956191
Short name T256
Test name
Test status
Simulation time 22585894212 ps
CPU time 32.58 seconds
Started Jul 11 04:53:18 PM PDT 24
Finished Jul 11 04:53:58 PM PDT 24
Peak memory 201808 kb
Host smart-ab34096d-934a-40af-95f3-5f6b9380ef9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381956191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w
ith_pre_cond.2381956191
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1085670413
Short name T427
Test name
Test status
Simulation time 3895070335 ps
CPU time 9.58 seconds
Started Jul 11 04:53:22 PM PDT 24
Finished Jul 11 04:53:41 PM PDT 24
Peak memory 201532 kb
Host smart-59cd4b58-cc11-44b6-9449-20b78b6e5971
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085670413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.1085670413
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.4181114983
Short name T513
Test name
Test status
Simulation time 2618089779 ps
CPU time 3.71 seconds
Started Jul 11 04:53:17 PM PDT 24
Finished Jul 11 04:53:29 PM PDT 24
Peak memory 201556 kb
Host smart-e2998dcb-62f5-4e65-a52c-37bbde97921e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181114983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.4181114983
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.1721627457
Short name T603
Test name
Test status
Simulation time 2485151239 ps
CPU time 3.77 seconds
Started Jul 11 04:53:19 PM PDT 24
Finished Jul 11 04:53:30 PM PDT 24
Peak memory 201616 kb
Host smart-9fb95fe1-602c-40c2-8203-366f3ec4b8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721627457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.1721627457
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.3418749511
Short name T698
Test name
Test status
Simulation time 2061114080 ps
CPU time 5.64 seconds
Started Jul 11 04:53:17 PM PDT 24
Finished Jul 11 04:53:30 PM PDT 24
Peak memory 201572 kb
Host smart-c52a3c00-057a-4798-9725-a1e761a5abe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418749511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.3418749511
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.3743302178
Short name T5
Test name
Test status
Simulation time 2511334395 ps
CPU time 7.48 seconds
Started Jul 11 04:53:22 PM PDT 24
Finished Jul 11 04:53:38 PM PDT 24
Peak memory 201552 kb
Host smart-1ea3add5-c4e1-491d-9be8-dd031a5af72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743302178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.3743302178
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.2045413559
Short name T461
Test name
Test status
Simulation time 2151363647 ps
CPU time 1.49 seconds
Started Jul 11 04:53:18 PM PDT 24
Finished Jul 11 04:53:27 PM PDT 24
Peak memory 201460 kb
Host smart-927da837-7c78-4d76-b359-976674662780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045413559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.2045413559
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.3763550782
Short name T317
Test name
Test status
Simulation time 9513058318 ps
CPU time 5.68 seconds
Started Jul 11 04:53:15 PM PDT 24
Finished Jul 11 04:53:28 PM PDT 24
Peak memory 201600 kb
Host smart-0c3b3be5-7309-46b8-875f-cf2fdb8849e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763550782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.3763550782
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.3520285773
Short name T80
Test name
Test status
Simulation time 4314119795 ps
CPU time 3.44 seconds
Started Jul 11 04:53:22 PM PDT 24
Finished Jul 11 04:53:34 PM PDT 24
Peak memory 201540 kb
Host smart-87eaa765-6f84-4f5a-b223-d777b9625bd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520285773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.3520285773
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1334590722
Short name T490
Test name
Test status
Simulation time 3325972935 ps
CPU time 7.05 seconds
Started Jul 11 04:53:22 PM PDT 24
Finished Jul 11 04:53:37 PM PDT 24
Peak memory 201624 kb
Host smart-5ad8c371-cce1-4fd3-840d-28359c76badb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334590722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.1
334590722
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.3028968576
Short name T746
Test name
Test status
Simulation time 91386436807 ps
CPU time 226.86 seconds
Started Jul 11 04:53:13 PM PDT 24
Finished Jul 11 04:57:07 PM PDT 24
Peak memory 201824 kb
Host smart-33c3fe76-0360-4f7d-8d52-da5e87ed2690
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028968576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_combo_detect.3028968576
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.349950347
Short name T99
Test name
Test status
Simulation time 23833694754 ps
CPU time 58.67 seconds
Started Jul 11 04:53:17 PM PDT 24
Finished Jul 11 04:54:24 PM PDT 24
Peak memory 202184 kb
Host smart-d0517e0d-6123-4d25-bce8-4f01eef7a856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349950347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_wi
th_pre_cond.349950347
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.558766889
Short name T322
Test name
Test status
Simulation time 3609451177 ps
CPU time 1.35 seconds
Started Jul 11 04:53:22 PM PDT 24
Finished Jul 11 04:53:32 PM PDT 24
Peak memory 201536 kb
Host smart-4a3a328d-155e-4d8f-9f3c-5d900a92758f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558766889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_ec_pwr_on_rst.558766889
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.275436352
Short name T157
Test name
Test status
Simulation time 4827519185 ps
CPU time 4.64 seconds
Started Jul 11 04:53:15 PM PDT 24
Finished Jul 11 04:53:28 PM PDT 24
Peak memory 201612 kb
Host smart-e3d62477-6882-42ba-ab50-2bdb16cb0b2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275436352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctr
l_edge_detect.275436352
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1861909895
Short name T753
Test name
Test status
Simulation time 2611009311 ps
CPU time 7.74 seconds
Started Jul 11 04:53:16 PM PDT 24
Finished Jul 11 04:53:31 PM PDT 24
Peak memory 201528 kb
Host smart-fbf613a3-d4f8-498a-b623-7d873016133e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861909895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.1861909895
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.2298953364
Short name T64
Test name
Test status
Simulation time 2465468703 ps
CPU time 2.34 seconds
Started Jul 11 04:53:19 PM PDT 24
Finished Jul 11 04:53:30 PM PDT 24
Peak memory 201532 kb
Host smart-a5db297c-5f0b-46e7-9494-5ad2a0712c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298953364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.2298953364
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.1712935724
Short name T426
Test name
Test status
Simulation time 2226387284 ps
CPU time 1.65 seconds
Started Jul 11 04:53:18 PM PDT 24
Finished Jul 11 04:53:27 PM PDT 24
Peak memory 201524 kb
Host smart-e5144875-64fc-4554-89ac-b00e0f7c2a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712935724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.1712935724
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.2686030487
Short name T68
Test name
Test status
Simulation time 2512571278 ps
CPU time 7.18 seconds
Started Jul 11 04:53:16 PM PDT 24
Finished Jul 11 04:53:31 PM PDT 24
Peak memory 201528 kb
Host smart-1cc76cba-f377-4b78-bb1a-ea5cadc4b583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686030487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.2686030487
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.3282803465
Short name T631
Test name
Test status
Simulation time 2118115585 ps
CPU time 3.07 seconds
Started Jul 11 04:53:18 PM PDT 24
Finished Jul 11 04:53:28 PM PDT 24
Peak memory 201524 kb
Host smart-976b021c-8165-48b1-aed3-93111666fe89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282803465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.3282803465
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.2164069293
Short name T526
Test name
Test status
Simulation time 7268492499 ps
CPU time 1.95 seconds
Started Jul 11 04:53:22 PM PDT 24
Finished Jul 11 04:53:32 PM PDT 24
Peak memory 201600 kb
Host smart-2c73bd76-3bc5-47cf-ba9d-4bbf2af77c50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164069293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_s
tress_all.2164069293
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.667921251
Short name T110
Test name
Test status
Simulation time 44641953410 ps
CPU time 26.69 seconds
Started Jul 11 04:53:26 PM PDT 24
Finished Jul 11 04:54:01 PM PDT 24
Peak memory 218396 kb
Host smart-1fcc8f8d-b660-490e-be33-0d1652c1a56c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667921251 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.667921251
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.420616365
Short name T139
Test name
Test status
Simulation time 9185100693 ps
CPU time 3.96 seconds
Started Jul 11 04:53:19 PM PDT 24
Finished Jul 11 04:53:31 PM PDT 24
Peak memory 201596 kb
Host smart-11d64c82-8784-4219-8714-e6f29de21219
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420616365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_ultra_low_pwr.420616365
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.4052185453
Short name T739
Test name
Test status
Simulation time 2009654894 ps
CPU time 5.84 seconds
Started Jul 11 04:53:26 PM PDT 24
Finished Jul 11 04:53:40 PM PDT 24
Peak memory 201520 kb
Host smart-7357f1ae-f418-4763-8fac-55f3045e85a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052185453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.4052185453
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1800648891
Short name T324
Test name
Test status
Simulation time 3253583874 ps
CPU time 7.5 seconds
Started Jul 11 04:53:20 PM PDT 24
Finished Jul 11 04:53:35 PM PDT 24
Peak memory 201692 kb
Host smart-cb51f531-6ad9-4089-b8ff-656ad8e97600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800648891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.1
800648891
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.1415640943
Short name T686
Test name
Test status
Simulation time 64400094826 ps
CPU time 58.48 seconds
Started Jul 11 04:53:22 PM PDT 24
Finished Jul 11 04:54:29 PM PDT 24
Peak memory 201896 kb
Host smart-79e6edaa-ace0-403c-8ae5-b9f86022a3d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415640943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.1415640943
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.405028948
Short name T404
Test name
Test status
Simulation time 583005168887 ps
CPU time 1595.76 seconds
Started Jul 11 04:53:27 PM PDT 24
Finished Jul 11 05:20:11 PM PDT 24
Peak memory 201596 kb
Host smart-8addf9ca-aa32-4f3a-ae37-c385e1aa8547
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405028948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_ec_pwr_on_rst.405028948
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1138033183
Short name T534
Test name
Test status
Simulation time 2628498418 ps
CPU time 2.39 seconds
Started Jul 11 04:53:20 PM PDT 24
Finished Jul 11 04:53:30 PM PDT 24
Peak memory 201640 kb
Host smart-65e58ef0-dd99-4b33-943c-a87b35c997b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138033183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.1138033183
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.4238635751
Short name T82
Test name
Test status
Simulation time 2478238483 ps
CPU time 2.28 seconds
Started Jul 11 04:53:22 PM PDT 24
Finished Jul 11 04:53:32 PM PDT 24
Peak memory 201536 kb
Host smart-a7b2a546-ba84-46e4-963a-f6076219d8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238635751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.4238635751
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.2646897479
Short name T213
Test name
Test status
Simulation time 2177427248 ps
CPU time 2.03 seconds
Started Jul 11 04:53:23 PM PDT 24
Finished Jul 11 04:53:34 PM PDT 24
Peak memory 201532 kb
Host smart-e0639ac0-7609-4f30-b086-4865b936b7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646897479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.2646897479
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.3098133664
Short name T690
Test name
Test status
Simulation time 2527980351 ps
CPU time 2.38 seconds
Started Jul 11 04:53:27 PM PDT 24
Finished Jul 11 04:53:38 PM PDT 24
Peak memory 201528 kb
Host smart-5c6b79e9-c755-4946-af4b-1c3922307b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098133664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.3098133664
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.2118362886
Short name T457
Test name
Test status
Simulation time 2164353615 ps
CPU time 1.16 seconds
Started Jul 11 04:53:29 PM PDT 24
Finished Jul 11 04:53:39 PM PDT 24
Peak memory 201532 kb
Host smart-9f941585-817e-40ba-86c1-425aeebdf49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118362886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.2118362886
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.3046579897
Short name T285
Test name
Test status
Simulation time 123838726569 ps
CPU time 76.64 seconds
Started Jul 11 04:53:21 PM PDT 24
Finished Jul 11 04:54:46 PM PDT 24
Peak memory 201776 kb
Host smart-b615592c-d86f-43d4-883a-ed80a707c8fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046579897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.3046579897
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.2052372410
Short name T53
Test name
Test status
Simulation time 32862358366 ps
CPU time 86.89 seconds
Started Jul 11 04:53:23 PM PDT 24
Finished Jul 11 04:54:58 PM PDT 24
Peak memory 218388 kb
Host smart-71b5171d-4ed2-4939-a3f0-6c11660f47ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052372410 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.2052372410
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.340510256
Short name T140
Test name
Test status
Simulation time 4397012372 ps
CPU time 4.32 seconds
Started Jul 11 04:53:21 PM PDT 24
Finished Jul 11 04:53:33 PM PDT 24
Peak memory 201612 kb
Host smart-d0fd7172-3631-49e3-9724-f1fe4025aeff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340510256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_ultra_low_pwr.340510256
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.1114112951
Short name T134
Test name
Test status
Simulation time 2014781617 ps
CPU time 5.62 seconds
Started Jul 11 04:53:30 PM PDT 24
Finished Jul 11 04:53:44 PM PDT 24
Peak memory 201620 kb
Host smart-87b51d83-6e7d-4d3c-94e3-edf3989c5364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114112951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.1114112951
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1667701511
Short name T510
Test name
Test status
Simulation time 3578057203 ps
CPU time 9.7 seconds
Started Jul 11 04:53:22 PM PDT 24
Finished Jul 11 04:53:40 PM PDT 24
Peak memory 201688 kb
Host smart-467240f1-67f5-4b5b-8d9b-1c8311ea8a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667701511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.1
667701511
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.2203391506
Short name T283
Test name
Test status
Simulation time 159578958261 ps
CPU time 386.45 seconds
Started Jul 11 04:53:32 PM PDT 24
Finished Jul 11 05:00:08 PM PDT 24
Peak memory 201896 kb
Host smart-16ad95df-dbca-48d1-9f58-f59b7a0bac87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203391506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.2203391506
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.2699358503
Short name T606
Test name
Test status
Simulation time 3622304857 ps
CPU time 5.45 seconds
Started Jul 11 04:53:24 PM PDT 24
Finished Jul 11 04:53:38 PM PDT 24
Peak memory 201504 kb
Host smart-4fd528c1-7715-4cba-a934-59143b12577e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699358503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ec_pwr_on_rst.2699358503
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.73328327
Short name T92
Test name
Test status
Simulation time 2612806874 ps
CPU time 1.99 seconds
Started Jul 11 04:53:21 PM PDT 24
Finished Jul 11 04:53:30 PM PDT 24
Peak memory 201632 kb
Host smart-30466973-bb07-4738-b463-a043800d8f6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73328327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl
_edge_detect.73328327
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.3831265532
Short name T729
Test name
Test status
Simulation time 2610571921 ps
CPU time 6.78 seconds
Started Jul 11 04:53:27 PM PDT 24
Finished Jul 11 04:53:42 PM PDT 24
Peak memory 201528 kb
Host smart-da0ebbc0-2515-47c4-82af-27bb010bf2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831265532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.3831265532
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.577533143
Short name T66
Test name
Test status
Simulation time 2464019548 ps
CPU time 8.14 seconds
Started Jul 11 04:53:34 PM PDT 24
Finished Jul 11 04:53:52 PM PDT 24
Peak memory 201640 kb
Host smart-578f5d51-1f54-4015-9dbc-63ff76d6c881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577533143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.577533143
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.2732051934
Short name T237
Test name
Test status
Simulation time 2179447926 ps
CPU time 2.02 seconds
Started Jul 11 04:53:29 PM PDT 24
Finished Jul 11 04:53:40 PM PDT 24
Peak memory 201528 kb
Host smart-068b4319-389f-402e-a9a9-4f3916a1f49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732051934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.2732051934
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.2656541895
Short name T60
Test name
Test status
Simulation time 2513694214 ps
CPU time 7.56 seconds
Started Jul 11 04:53:43 PM PDT 24
Finished Jul 11 04:54:00 PM PDT 24
Peak memory 201632 kb
Host smart-a9dcb442-69ab-4599-be1c-e6b91e7e6815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656541895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.2656541895
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.3431919312
Short name T128
Test name
Test status
Simulation time 2136202408 ps
CPU time 2.02 seconds
Started Jul 11 04:53:33 PM PDT 24
Finished Jul 11 04:53:44 PM PDT 24
Peak memory 201500 kb
Host smart-22bcbc36-6adc-402e-b09e-4db1b90acfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431919312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.3431919312
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.2085864665
Short name T377
Test name
Test status
Simulation time 164966374078 ps
CPU time 447.6 seconds
Started Jul 11 04:53:23 PM PDT 24
Finished Jul 11 05:00:59 PM PDT 24
Peak memory 201780 kb
Host smart-8129d49c-c5c1-4f83-8093-84b6bc7cb97e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085864665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.2085864665
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.4231787175
Short name T405
Test name
Test status
Simulation time 967327907491 ps
CPU time 47.81 seconds
Started Jul 11 04:53:23 PM PDT 24
Finished Jul 11 04:54:19 PM PDT 24
Peak memory 201616 kb
Host smart-6db298e5-873b-4b05-896f-a273ad3198ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231787175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ultra_low_pwr.4231787175
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.3360495493
Short name T163
Test name
Test status
Simulation time 2013737908 ps
CPU time 5.03 seconds
Started Jul 11 04:52:55 PM PDT 24
Finished Jul 11 04:53:06 PM PDT 24
Peak memory 201536 kb
Host smart-8fd658b3-e97d-421a-b9c5-cc8cf8848400
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360495493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.3360495493
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.2894746274
Short name T411
Test name
Test status
Simulation time 3723411216 ps
CPU time 2.69 seconds
Started Jul 11 04:52:46 PM PDT 24
Finished Jul 11 04:52:56 PM PDT 24
Peak memory 201656 kb
Host smart-d88d17c3-5f0c-4890-b33b-796b7c4c5aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894746274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.2894746274
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.2040260708
Short name T277
Test name
Test status
Simulation time 51995961480 ps
CPU time 135.63 seconds
Started Jul 11 04:52:45 PM PDT 24
Finished Jul 11 04:55:08 PM PDT 24
Peak memory 201784 kb
Host smart-273703c6-e510-4544-b7f5-cabf2887ec12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040260708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.2040260708
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.4193497830
Short name T612
Test name
Test status
Simulation time 2452292763 ps
CPU time 2.36 seconds
Started Jul 11 04:52:47 PM PDT 24
Finished Jul 11 04:52:56 PM PDT 24
Peak memory 201552 kb
Host smart-0b4088d2-aac6-45a2-b7d3-856a922cbcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193497830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.4193497830
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1091989657
Short name T74
Test name
Test status
Simulation time 2519480692 ps
CPU time 6.95 seconds
Started Jul 11 04:52:45 PM PDT 24
Finished Jul 11 04:52:59 PM PDT 24
Peak memory 201560 kb
Host smart-efe44119-aaa2-4422-be87-b46717d58a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091989657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1091989657
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.2308851731
Short name T622
Test name
Test status
Simulation time 2717868002 ps
CPU time 5.62 seconds
Started Jul 11 04:52:43 PM PDT 24
Finished Jul 11 04:52:56 PM PDT 24
Peak memory 201512 kb
Host smart-dbee113c-51fc-483d-af4c-e2b4db137489
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308851731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.2308851731
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.3811371339
Short name T182
Test name
Test status
Simulation time 3705729936 ps
CPU time 9.88 seconds
Started Jul 11 04:52:45 PM PDT 24
Finished Jul 11 04:53:02 PM PDT 24
Peak memory 201644 kb
Host smart-a2ec6064-6dcc-4c8e-b6dd-34def699d42c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811371339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.3811371339
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3969641736
Short name T666
Test name
Test status
Simulation time 2631579828 ps
CPU time 2.28 seconds
Started Jul 11 04:52:53 PM PDT 24
Finished Jul 11 04:53:01 PM PDT 24
Peak memory 201628 kb
Host smart-01ec1de0-e6d2-4e0a-8fc5-d1838094bc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969641736 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.3969641736
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.1822276063
Short name T63
Test name
Test status
Simulation time 2456314291 ps
CPU time 6.49 seconds
Started Jul 11 04:52:48 PM PDT 24
Finished Jul 11 04:53:01 PM PDT 24
Peak memory 201624 kb
Host smart-25b4d21c-3d04-438f-bc30-54ff280bd6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822276063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.1822276063
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.3970433155
Short name T454
Test name
Test status
Simulation time 2270112014 ps
CPU time 3.78 seconds
Started Jul 11 04:52:44 PM PDT 24
Finished Jul 11 04:52:55 PM PDT 24
Peak memory 201540 kb
Host smart-728309f8-6f13-4e24-9a7a-65ff9782d0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970433155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.3970433155
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.1960668511
Short name T617
Test name
Test status
Simulation time 2509123312 ps
CPU time 7.52 seconds
Started Jul 11 04:52:44 PM PDT 24
Finished Jul 11 04:52:59 PM PDT 24
Peak memory 201628 kb
Host smart-79712fff-1e8c-48d8-8a90-85973c947fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960668511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.1960668511
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.1511450781
Short name T315
Test name
Test status
Simulation time 42041508006 ps
CPU time 52.61 seconds
Started Jul 11 04:52:47 PM PDT 24
Finished Jul 11 04:53:47 PM PDT 24
Peak memory 221176 kb
Host smart-9d29481a-da8f-48dc-9803-d144e217fdf8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511450781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.1511450781
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.1986464784
Short name T559
Test name
Test status
Simulation time 2136209738 ps
CPU time 2.05 seconds
Started Jul 11 04:52:47 PM PDT 24
Finished Jul 11 04:52:56 PM PDT 24
Peak memory 201480 kb
Host smart-278982d8-fdc7-4de2-b5bc-f7c92b6956e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986464784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.1986464784
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.67731164
Short name T44
Test name
Test status
Simulation time 16237224785 ps
CPU time 21.68 seconds
Started Jul 11 04:52:47 PM PDT 24
Finished Jul 11 04:53:15 PM PDT 24
Peak memory 201840 kb
Host smart-f44483c9-57e1-498c-8073-482c1ababfc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67731164 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.67731164
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.3879121900
Short name T637
Test name
Test status
Simulation time 2012805616 ps
CPU time 5.55 seconds
Started Jul 11 04:53:26 PM PDT 24
Finished Jul 11 04:53:39 PM PDT 24
Peak memory 201612 kb
Host smart-0acef89b-b573-43d8-b710-645d0a25e4c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879121900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.3879121900
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.39757781
Short name T29
Test name
Test status
Simulation time 3637328224 ps
CPU time 2.7 seconds
Started Jul 11 04:53:21 PM PDT 24
Finished Jul 11 04:53:32 PM PDT 24
Peak memory 201628 kb
Host smart-3fa9cddb-604a-417d-b98a-5ad073e881b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39757781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.39757781
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.4257691083
Short name T212
Test name
Test status
Simulation time 131972278089 ps
CPU time 84.41 seconds
Started Jul 11 04:53:28 PM PDT 24
Finished Jul 11 04:55:01 PM PDT 24
Peak memory 201456 kb
Host smart-9b3973d0-f228-4566-a777-757372061e07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257691083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_combo_detect.4257691083
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.4047751689
Short name T58
Test name
Test status
Simulation time 3049610113 ps
CPU time 2.75 seconds
Started Jul 11 04:53:28 PM PDT 24
Finished Jul 11 04:53:40 PM PDT 24
Peak memory 201212 kb
Host smart-3dd6ec82-ee07-44af-80cf-ff5655c51ffb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047751689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.4047751689
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.1130315621
Short name T38
Test name
Test status
Simulation time 3370925543 ps
CPU time 9.51 seconds
Started Jul 11 04:53:22 PM PDT 24
Finished Jul 11 04:53:40 PM PDT 24
Peak memory 201616 kb
Host smart-efdf970e-828d-49a9-9b67-d668a59b6a86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130315621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.1130315621
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3110296435
Short name T346
Test name
Test status
Simulation time 2612288588 ps
CPU time 7.38 seconds
Started Jul 11 04:53:33 PM PDT 24
Finished Jul 11 04:53:50 PM PDT 24
Peak memory 201620 kb
Host smart-013ca33d-e7f2-4cc8-85db-2f9956311895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110296435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.3110296435
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.1666860248
Short name T332
Test name
Test status
Simulation time 2518441539 ps
CPU time 1.56 seconds
Started Jul 11 04:53:18 PM PDT 24
Finished Jul 11 04:53:27 PM PDT 24
Peak memory 201632 kb
Host smart-75830d97-cef9-4cec-a56d-b488fd0dcefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666860248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.1666860248
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.5175202
Short name T414
Test name
Test status
Simulation time 2279239912 ps
CPU time 1.5 seconds
Started Jul 11 04:53:23 PM PDT 24
Finished Jul 11 04:53:33 PM PDT 24
Peak memory 201648 kb
Host smart-11bade25-735a-403a-8f38-8fc0d1cd21a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5175202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.5175202
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.3143053794
Short name T166
Test name
Test status
Simulation time 2514519473 ps
CPU time 4.85 seconds
Started Jul 11 04:53:26 PM PDT 24
Finished Jul 11 04:53:38 PM PDT 24
Peak memory 201624 kb
Host smart-c9fe0a92-9f2c-47d3-bac9-d5c3614c727f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143053794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.3143053794
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.1176011577
Short name T576
Test name
Test status
Simulation time 2150376034 ps
CPU time 1.27 seconds
Started Jul 11 04:53:19 PM PDT 24
Finished Jul 11 04:53:28 PM PDT 24
Peak memory 201560 kb
Host smart-fb2c0c11-8800-44bc-93e7-421dd490c01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176011577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.1176011577
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.4120301316
Short name T339
Test name
Test status
Simulation time 6246522245 ps
CPU time 3.96 seconds
Started Jul 11 04:53:25 PM PDT 24
Finished Jul 11 04:53:37 PM PDT 24
Peak memory 201460 kb
Host smart-02ac2247-2cd5-4495-8045-cb71c88aa0cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120301316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ultra_low_pwr.4120301316
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.2899126265
Short name T270
Test name
Test status
Simulation time 2020176561 ps
CPU time 3.89 seconds
Started Jul 11 04:53:28 PM PDT 24
Finished Jul 11 04:53:41 PM PDT 24
Peak memory 201520 kb
Host smart-f43d7b71-525a-4859-86a7-316ff1608faf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899126265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.2899126265
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1435271570
Short name T592
Test name
Test status
Simulation time 3436236842 ps
CPU time 2.22 seconds
Started Jul 11 04:53:32 PM PDT 24
Finished Jul 11 04:53:44 PM PDT 24
Peak memory 201680 kb
Host smart-22fb2924-e1e0-4f2c-b285-b52629d1b5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435271570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.1
435271570
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3775081935
Short name T741
Test name
Test status
Simulation time 59992855740 ps
CPU time 156.24 seconds
Started Jul 11 04:53:31 PM PDT 24
Finished Jul 11 04:56:15 PM PDT 24
Peak memory 201756 kb
Host smart-f23a53c8-959f-4cd8-8dae-034be1f60c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775081935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.3775081935
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.409220852
Short name T636
Test name
Test status
Simulation time 4386239501 ps
CPU time 5.86 seconds
Started Jul 11 04:53:28 PM PDT 24
Finished Jul 11 04:53:43 PM PDT 24
Peak memory 201620 kb
Host smart-c0d17f1e-f777-417f-a3c4-e81c6b681b90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409220852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_ec_pwr_on_rst.409220852
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.1288309443
Short name T40
Test name
Test status
Simulation time 5545034373 ps
CPU time 10.61 seconds
Started Jul 11 04:53:28 PM PDT 24
Finished Jul 11 04:53:48 PM PDT 24
Peak memory 201596 kb
Host smart-81e237c7-0e9e-4260-8fbf-fd67ec695f14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288309443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.1288309443
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.1168981348
Short name T71
Test name
Test status
Simulation time 2653533610 ps
CPU time 1.75 seconds
Started Jul 11 04:53:27 PM PDT 24
Finished Jul 11 04:53:37 PM PDT 24
Peak memory 201636 kb
Host smart-5d4f0f4a-ce4b-4be4-96f1-48a9e8095c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168981348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.1168981348
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.101879393
Short name T527
Test name
Test status
Simulation time 2469982407 ps
CPU time 7.15 seconds
Started Jul 11 04:53:21 PM PDT 24
Finished Jul 11 04:53:35 PM PDT 24
Peak memory 201612 kb
Host smart-3a49303e-75fd-49d2-a11f-87374286dfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101879393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.101879393
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.4000992053
Short name T441
Test name
Test status
Simulation time 2260233402 ps
CPU time 3.47 seconds
Started Jul 11 04:53:22 PM PDT 24
Finished Jul 11 04:53:34 PM PDT 24
Peak memory 201616 kb
Host smart-9ace24fe-138a-4e39-a8e5-6054ec63dd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000992053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.4000992053
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.2062994763
Short name T638
Test name
Test status
Simulation time 2572713503 ps
CPU time 1.42 seconds
Started Jul 11 04:53:30 PM PDT 24
Finished Jul 11 04:53:40 PM PDT 24
Peak memory 201632 kb
Host smart-9834e781-8c04-49ee-abef-77a9e58faf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062994763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.2062994763
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.3000136089
Short name T546
Test name
Test status
Simulation time 2111648378 ps
CPU time 5.49 seconds
Started Jul 11 04:53:24 PM PDT 24
Finished Jul 11 04:53:38 PM PDT 24
Peak memory 201452 kb
Host smart-2bb96d48-0c0c-486d-b36e-022a5bd9cfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000136089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.3000136089
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.1740316719
Short name T505
Test name
Test status
Simulation time 9304967745 ps
CPU time 6.62 seconds
Started Jul 11 04:53:28 PM PDT 24
Finished Jul 11 04:53:44 PM PDT 24
Peak memory 201608 kb
Host smart-efc24648-42c8-4f99-b881-42b27cce2b06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740316719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.1740316719
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.1520167103
Short name T239
Test name
Test status
Simulation time 48588502809 ps
CPU time 57.13 seconds
Started Jul 11 04:53:25 PM PDT 24
Finished Jul 11 04:54:31 PM PDT 24
Peak memory 210084 kb
Host smart-79e6d0eb-8448-4310-ae0b-27c79154b9cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520167103 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.1520167103
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.363966530
Short name T34
Test name
Test status
Simulation time 9457998302 ps
CPU time 4 seconds
Started Jul 11 04:53:29 PM PDT 24
Finished Jul 11 04:53:42 PM PDT 24
Peak memory 201544 kb
Host smart-cbd8d3f4-2e85-420b-80c8-c4e8427447e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363966530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_ultra_low_pwr.363966530
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.1859392641
Short name T419
Test name
Test status
Simulation time 2021335416 ps
CPU time 5.4 seconds
Started Jul 11 04:53:31 PM PDT 24
Finished Jul 11 04:53:45 PM PDT 24
Peak memory 201592 kb
Host smart-671d38e3-9fbe-41e7-a8ee-8790a87e178d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859392641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.1859392641
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.3631394104
Short name T668
Test name
Test status
Simulation time 3194479558 ps
CPU time 2.85 seconds
Started Jul 11 04:53:27 PM PDT 24
Finished Jul 11 04:53:38 PM PDT 24
Peak memory 201676 kb
Host smart-550e564e-a6e8-421c-a436-93b71ff0d0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631394104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.3
631394104
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.1695248230
Short name T286
Test name
Test status
Simulation time 61850767219 ps
CPU time 11.43 seconds
Started Jul 11 04:53:28 PM PDT 24
Finished Jul 11 04:53:49 PM PDT 24
Peak memory 201892 kb
Host smart-5060ab4a-fdcb-4fb3-9e47-e780609dcc17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695248230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.1695248230
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1363360174
Short name T708
Test name
Test status
Simulation time 4816520164 ps
CPU time 4.88 seconds
Started Jul 11 04:53:26 PM PDT 24
Finished Jul 11 04:53:39 PM PDT 24
Peak memory 201512 kb
Host smart-5e090499-d763-431b-8cd0-5c4d8a764b24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363360174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.1363360174
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.1545215383
Short name T156
Test name
Test status
Simulation time 4108244378 ps
CPU time 7.27 seconds
Started Jul 11 04:53:45 PM PDT 24
Finished Jul 11 04:54:01 PM PDT 24
Peak memory 201608 kb
Host smart-da2d9dff-66de-4fb1-bd99-3552ddd2d91f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545215383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.1545215383
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3925938868
Short name T502
Test name
Test status
Simulation time 2613105601 ps
CPU time 7.43 seconds
Started Jul 11 04:53:46 PM PDT 24
Finished Jul 11 04:54:02 PM PDT 24
Peak memory 201628 kb
Host smart-3cef60ae-4803-493d-8930-86a7b638d481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925938868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.3925938868
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.1505172523
Short name T725
Test name
Test status
Simulation time 2505432668 ps
CPU time 1.62 seconds
Started Jul 11 04:53:30 PM PDT 24
Finished Jul 11 04:53:40 PM PDT 24
Peak memory 201532 kb
Host smart-68c3decf-1c1a-4999-8161-79d427657c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505172523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.1505172523
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.1248308907
Short name T191
Test name
Test status
Simulation time 2084687083 ps
CPU time 5.28 seconds
Started Jul 11 04:53:26 PM PDT 24
Finished Jul 11 04:53:40 PM PDT 24
Peak memory 201484 kb
Host smart-1de1cac7-f277-449e-b72c-d40334914cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248308907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.1248308907
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.2849780138
Short name T552
Test name
Test status
Simulation time 2521814064 ps
CPU time 2.54 seconds
Started Jul 11 04:53:26 PM PDT 24
Finished Jul 11 04:53:38 PM PDT 24
Peak memory 201628 kb
Host smart-e25a76e9-e216-48ba-9f7d-92158814ddc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849780138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.2849780138
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.2614126744
Short name T458
Test name
Test status
Simulation time 2188195059 ps
CPU time 0.87 seconds
Started Jul 11 04:53:27 PM PDT 24
Finished Jul 11 04:53:36 PM PDT 24
Peak memory 201460 kb
Host smart-76834836-a366-4ad9-afd5-2c552f714761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614126744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.2614126744
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2833553247
Short name T183
Test name
Test status
Simulation time 39511394808 ps
CPU time 48.52 seconds
Started Jul 11 04:53:27 PM PDT 24
Finished Jul 11 04:54:24 PM PDT 24
Peak memory 202292 kb
Host smart-5f5a4709-2cce-40b8-a8a7-b8f1af520783
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833553247 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.2833553247
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3725460215
Short name T583
Test name
Test status
Simulation time 6279405780 ps
CPU time 8.37 seconds
Started Jul 11 04:53:27 PM PDT 24
Finished Jul 11 04:53:44 PM PDT 24
Peak memory 201620 kb
Host smart-30d92568-bd42-46e4-b68a-32372a23876f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725460215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.3725460215
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.773699415
Short name T198
Test name
Test status
Simulation time 2014045427 ps
CPU time 6.03 seconds
Started Jul 11 04:53:30 PM PDT 24
Finished Jul 11 04:53:45 PM PDT 24
Peak memory 201520 kb
Host smart-a62dde34-2661-4d09-befc-f321e4e5eb50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773699415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_tes
t.773699415
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.677030608
Short name T649
Test name
Test status
Simulation time 3211529218 ps
CPU time 3.54 seconds
Started Jul 11 04:53:28 PM PDT 24
Finished Jul 11 04:53:41 PM PDT 24
Peak memory 201660 kb
Host smart-5cf9dfc3-58ca-4422-a96e-3c8357a685fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677030608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.677030608
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.836953674
Short name T350
Test name
Test status
Simulation time 3940641822 ps
CPU time 3 seconds
Started Jul 11 04:53:32 PM PDT 24
Finished Jul 11 04:53:43 PM PDT 24
Peak memory 201536 kb
Host smart-0f13ebfa-a7c9-423f-9544-97acd177efcd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836953674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_ec_pwr_on_rst.836953674
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.951659076
Short name T36
Test name
Test status
Simulation time 4048620257 ps
CPU time 10.94 seconds
Started Jul 11 04:53:28 PM PDT 24
Finished Jul 11 04:53:48 PM PDT 24
Peak memory 201616 kb
Host smart-6676e54c-6e54-4b17-905b-51650a0b5b1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951659076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctr
l_edge_detect.951659076
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.2867386441
Short name T215
Test name
Test status
Simulation time 2616595645 ps
CPU time 3.93 seconds
Started Jul 11 04:53:31 PM PDT 24
Finished Jul 11 04:53:43 PM PDT 24
Peak memory 201540 kb
Host smart-27216712-8a0c-4edc-9c9d-7d7357551687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867386441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.2867386441
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.662507171
Short name T781
Test name
Test status
Simulation time 2453389695 ps
CPU time 7.81 seconds
Started Jul 11 04:53:33 PM PDT 24
Finished Jul 11 04:53:51 PM PDT 24
Peak memory 201560 kb
Host smart-8a697d80-db58-42a8-94a0-f52730e7a4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662507171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.662507171
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.670248060
Short name T594
Test name
Test status
Simulation time 2186926300 ps
CPU time 1.52 seconds
Started Jul 11 04:53:28 PM PDT 24
Finished Jul 11 04:53:39 PM PDT 24
Peak memory 201624 kb
Host smart-2cb2e7b9-372c-41b2-b15e-6ec2c042a93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670248060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.670248060
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.2283851089
Short name T751
Test name
Test status
Simulation time 2512666206 ps
CPU time 7.66 seconds
Started Jul 11 04:53:32 PM PDT 24
Finished Jul 11 04:53:48 PM PDT 24
Peak memory 201564 kb
Host smart-40694ca0-ecbc-4c61-b41e-1e017dab4c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283851089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.2283851089
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.2452808131
Short name T625
Test name
Test status
Simulation time 2126658032 ps
CPU time 2.2 seconds
Started Jul 11 04:53:28 PM PDT 24
Finished Jul 11 04:53:39 PM PDT 24
Peak memory 201500 kb
Host smart-c3b63b5f-4644-4519-a4ef-1260340ba698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452808131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.2452808131
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.3403081782
Short name T783
Test name
Test status
Simulation time 180320626436 ps
CPU time 499.57 seconds
Started Jul 11 04:53:41 PM PDT 24
Finished Jul 11 05:02:10 PM PDT 24
Peak memory 201896 kb
Host smart-4478202d-a7b8-4b7a-9c8f-7811bcbb54ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403081782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.3403081782
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.1529220096
Short name T93
Test name
Test status
Simulation time 81234403458 ps
CPU time 52.17 seconds
Started Jul 11 04:53:27 PM PDT 24
Finished Jul 11 04:54:27 PM PDT 24
Peak memory 214924 kb
Host smart-a9844193-a559-411b-9032-5b89e4458260
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529220096 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.1529220096
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.925108651
Short name T726
Test name
Test status
Simulation time 5798324577 ps
CPU time 1.28 seconds
Started Jul 11 04:53:32 PM PDT 24
Finished Jul 11 04:53:43 PM PDT 24
Peak memory 201628 kb
Host smart-38fa265c-fae1-4bcd-8ea2-af0848f405bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925108651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_ultra_low_pwr.925108651
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.4292081003
Short name T499
Test name
Test status
Simulation time 2012266005 ps
CPU time 5.31 seconds
Started Jul 11 04:53:32 PM PDT 24
Finished Jul 11 04:53:46 PM PDT 24
Peak memory 201600 kb
Host smart-48460912-30be-4ff5-a2d3-f2053b9df569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292081003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.4292081003
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2248718932
Short name T290
Test name
Test status
Simulation time 3665764537 ps
CPU time 2.21 seconds
Started Jul 11 04:53:34 PM PDT 24
Finished Jul 11 04:53:45 PM PDT 24
Peak memory 201700 kb
Host smart-8fb5282e-a9ee-4436-abea-55c467162c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248718932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.2
248718932
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3374548822
Short name T381
Test name
Test status
Simulation time 98209335914 ps
CPU time 255.27 seconds
Started Jul 11 04:53:47 PM PDT 24
Finished Jul 11 04:58:11 PM PDT 24
Peak memory 201840 kb
Host smart-13db2898-94ef-4608-bb44-50204a608697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374548822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.3374548822
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.3491309540
Short name T246
Test name
Test status
Simulation time 3043117326 ps
CPU time 1.11 seconds
Started Jul 11 04:53:32 PM PDT 24
Finished Jul 11 04:53:43 PM PDT 24
Peak memory 201584 kb
Host smart-64ea620e-818d-46a0-8d2f-3b9a9d4dd489
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491309540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ec_pwr_on_rst.3491309540
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.2665053638
Short name T152
Test name
Test status
Simulation time 4478081453 ps
CPU time 1.24 seconds
Started Jul 11 04:53:38 PM PDT 24
Finished Jul 11 04:53:48 PM PDT 24
Peak memory 201596 kb
Host smart-c4430cff-7c93-4144-a349-e98a6f6eeec1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665053638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.2665053638
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.1117321942
Short name T195
Test name
Test status
Simulation time 2645216809 ps
CPU time 1.58 seconds
Started Jul 11 04:53:39 PM PDT 24
Finished Jul 11 04:53:50 PM PDT 24
Peak memory 201532 kb
Host smart-30cef24c-fec7-46e1-8d42-e49cd463651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117321942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.1117321942
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.3856673746
Short name T674
Test name
Test status
Simulation time 2454260305 ps
CPU time 8.02 seconds
Started Jul 11 04:53:35 PM PDT 24
Finished Jul 11 04:53:52 PM PDT 24
Peak memory 201588 kb
Host smart-b3d023c2-cdd4-48f6-8890-1e9b6e90e96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856673746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.3856673746
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.2160443117
Short name T162
Test name
Test status
Simulation time 2090601118 ps
CPU time 5.64 seconds
Started Jul 11 04:53:38 PM PDT 24
Finished Jul 11 04:53:54 PM PDT 24
Peak memory 201488 kb
Host smart-974ae2be-1c28-4d92-bd21-bd8ddb3b2e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160443117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.2160443117
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.2385263566
Short name T437
Test name
Test status
Simulation time 2540614625 ps
CPU time 1.92 seconds
Started Jul 11 04:53:33 PM PDT 24
Finished Jul 11 04:53:45 PM PDT 24
Peak memory 201860 kb
Host smart-38dd8a98-f89d-4495-aa98-6dead146b6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385263566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.2385263566
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.2962006737
Short name T687
Test name
Test status
Simulation time 2112168194 ps
CPU time 5.72 seconds
Started Jul 11 04:53:33 PM PDT 24
Finished Jul 11 04:53:48 PM PDT 24
Peak memory 201568 kb
Host smart-8a9bbd42-58ab-4b2a-af32-9ecde037ee8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962006737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.2962006737
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.2010980547
Short name T245
Test name
Test status
Simulation time 9568923756 ps
CPU time 3.16 seconds
Started Jul 11 04:53:47 PM PDT 24
Finished Jul 11 04:53:59 PM PDT 24
Peak memory 201596 kb
Host smart-266150a5-acc9-4ce4-aa93-662035068c8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010980547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.2010980547
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1183016406
Short name T125
Test name
Test status
Simulation time 5401046699 ps
CPU time 4.34 seconds
Started Jul 11 04:53:44 PM PDT 24
Finished Jul 11 04:53:57 PM PDT 24
Peak memory 201644 kb
Host smart-c6a6ae1b-c460-4ca1-8fb7-79177e19c233
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183016406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.1183016406
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.3219207214
Short name T480
Test name
Test status
Simulation time 2016526251 ps
CPU time 2.99 seconds
Started Jul 11 04:53:32 PM PDT 24
Finished Jul 11 04:53:44 PM PDT 24
Peak memory 201548 kb
Host smart-ad28f3a5-84db-4e8c-8973-f4b9d32b9c45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219207214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.3219207214
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.4218601809
Short name T584
Test name
Test status
Simulation time 3958886674 ps
CPU time 2.08 seconds
Started Jul 11 04:53:33 PM PDT 24
Finished Jul 11 04:53:45 PM PDT 24
Peak memory 201924 kb
Host smart-dcf230d4-f357-411f-b998-4f5d4405b98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218601809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.4
218601809
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.1560833737
Short name T573
Test name
Test status
Simulation time 158718485156 ps
CPU time 105.52 seconds
Started Jul 11 04:53:38 PM PDT 24
Finished Jul 11 04:55:34 PM PDT 24
Peak memory 201812 kb
Host smart-51f3a7a7-77b4-4b0e-9e96-eb9567be8b16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560833737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.1560833737
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.2630266566
Short name T553
Test name
Test status
Simulation time 26605160987 ps
CPU time 17.55 seconds
Started Jul 11 04:53:36 PM PDT 24
Finished Jul 11 04:54:03 PM PDT 24
Peak memory 201912 kb
Host smart-26fc271f-237a-405d-b383-0a952071a7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630266566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_w
ith_pre_cond.2630266566
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.2079047212
Short name T264
Test name
Test status
Simulation time 3712437908 ps
CPU time 8.12 seconds
Started Jul 11 04:53:45 PM PDT 24
Finished Jul 11 04:54:02 PM PDT 24
Peak memory 201612 kb
Host smart-81f8d32e-77ae-4095-bf43-6c454b10b166
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079047212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.2079047212
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.320413245
Short name T171
Test name
Test status
Simulation time 2752822865 ps
CPU time 2.13 seconds
Started Jul 11 04:53:41 PM PDT 24
Finished Jul 11 04:53:53 PM PDT 24
Peak memory 201532 kb
Host smart-09f5fb17-1824-48dc-a0ab-eceb1e1fc735
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320413245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctr
l_edge_detect.320413245
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.1224728851
Short name T728
Test name
Test status
Simulation time 2616496637 ps
CPU time 4.19 seconds
Started Jul 11 04:53:41 PM PDT 24
Finished Jul 11 04:53:55 PM PDT 24
Peak memory 201572 kb
Host smart-cfa40ca1-4b69-46f9-bc7c-119cb7b68fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224728851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.1224728851
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.1472121169
Short name T771
Test name
Test status
Simulation time 2480066457 ps
CPU time 1.84 seconds
Started Jul 11 04:53:38 PM PDT 24
Finished Jul 11 04:53:50 PM PDT 24
Peak memory 201536 kb
Host smart-8c1d4a4d-0907-47fe-923f-9bb29eeaa6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472121169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.1472121169
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.1817465242
Short name T609
Test name
Test status
Simulation time 2242006498 ps
CPU time 1.33 seconds
Started Jul 11 04:53:33 PM PDT 24
Finished Jul 11 04:53:43 PM PDT 24
Peak memory 201532 kb
Host smart-202ffcbc-51c7-4364-9336-844085d59a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817465242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.1817465242
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.2791890404
Short name T646
Test name
Test status
Simulation time 2513798611 ps
CPU time 6.87 seconds
Started Jul 11 04:53:45 PM PDT 24
Finished Jul 11 04:54:00 PM PDT 24
Peak memory 201640 kb
Host smart-fc157001-1e8f-4640-8aa1-4bbb335c58ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791890404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.2791890404
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.1668294047
Short name T495
Test name
Test status
Simulation time 2113958243 ps
CPU time 6.14 seconds
Started Jul 11 04:53:32 PM PDT 24
Finished Jul 11 04:53:47 PM PDT 24
Peak memory 201516 kb
Host smart-9b2f5e26-6946-4b77-b9f9-58d6164ae827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668294047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.1668294047
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.1265605807
Short name T469
Test name
Test status
Simulation time 6370075430 ps
CPU time 16.6 seconds
Started Jul 11 04:53:33 PM PDT 24
Finished Jul 11 04:53:59 PM PDT 24
Peak memory 201500 kb
Host smart-b51249de-582a-4c75-92ec-c189f7021982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265605807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.1265605807
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2264947872
Short name T766
Test name
Test status
Simulation time 1497241857143 ps
CPU time 101.16 seconds
Started Jul 11 04:53:37 PM PDT 24
Finished Jul 11 04:55:27 PM PDT 24
Peak memory 201604 kb
Host smart-0da623bb-f6a1-43ce-a5d0-ea43054055bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264947872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ultra_low_pwr.2264947872
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.3708797840
Short name T421
Test name
Test status
Simulation time 2021670133 ps
CPU time 3.27 seconds
Started Jul 11 04:53:50 PM PDT 24
Finished Jul 11 04:54:01 PM PDT 24
Peak memory 201624 kb
Host smart-97090a43-4048-4c22-ba80-949963faf759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708797840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.3708797840
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2460461234
Short name T524
Test name
Test status
Simulation time 3944941348 ps
CPU time 10.55 seconds
Started Jul 11 04:53:46 PM PDT 24
Finished Jul 11 04:54:05 PM PDT 24
Peak memory 201704 kb
Host smart-f1ff010b-415f-42cf-ae36-52b5f468fcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460461234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.2
460461234
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.437536945
Short name T351
Test name
Test status
Simulation time 212524016269 ps
CPU time 218.76 seconds
Started Jul 11 04:53:40 PM PDT 24
Finished Jul 11 04:57:28 PM PDT 24
Peak memory 201876 kb
Host smart-1153c522-c10a-4877-9fdc-d15db0cea077
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437536945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_combo_detect.437536945
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.609243470
Short name T496
Test name
Test status
Simulation time 4150122836 ps
CPU time 2.99 seconds
Started Jul 11 04:53:41 PM PDT 24
Finished Jul 11 04:53:53 PM PDT 24
Peak memory 201544 kb
Host smart-a5c5b185-603a-4d01-88b9-9be22f6421b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609243470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_ec_pwr_on_rst.609243470
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3732185511
Short name T491
Test name
Test status
Simulation time 2608984973 ps
CPU time 7.14 seconds
Started Jul 11 04:53:32 PM PDT 24
Finished Jul 11 04:53:49 PM PDT 24
Peak memory 201560 kb
Host smart-cedb92b2-5b8e-4fef-8109-2ec25e991997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732185511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.3732185511
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.1099405088
Short name T221
Test name
Test status
Simulation time 2482906803 ps
CPU time 2.1 seconds
Started Jul 11 04:56:49 PM PDT 24
Finished Jul 11 04:56:59 PM PDT 24
Peak memory 201504 kb
Host smart-8461603b-5a38-46de-a29e-2f5fedddc8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099405088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.1099405088
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.2669865035
Short name T118
Test name
Test status
Simulation time 2120536556 ps
CPU time 1.39 seconds
Started Jul 11 04:53:34 PM PDT 24
Finished Jul 11 04:53:44 PM PDT 24
Peak memory 201412 kb
Host smart-aaf736a6-bf05-4509-bf86-fa65294a1ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669865035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.2669865035
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.399619703
Short name T571
Test name
Test status
Simulation time 2532266681 ps
CPU time 2.09 seconds
Started Jul 11 04:53:34 PM PDT 24
Finished Jul 11 04:53:46 PM PDT 24
Peak memory 201532 kb
Host smart-3ffc692c-bd91-4624-b854-fb4d7f2452ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399619703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.399619703
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.8861058
Short name T214
Test name
Test status
Simulation time 2107451135 ps
CPU time 5.51 seconds
Started Jul 11 04:53:33 PM PDT 24
Finished Jul 11 04:53:48 PM PDT 24
Peak memory 201540 kb
Host smart-799d73ac-1594-4b5a-b432-97c4ed395ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8861058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.8861058
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.1600546797
Short name T574
Test name
Test status
Simulation time 15460036585 ps
CPU time 8.41 seconds
Started Jul 11 04:53:39 PM PDT 24
Finished Jul 11 04:53:57 PM PDT 24
Peak memory 201860 kb
Host smart-9deee73b-48cb-4034-a8af-9f12a254425f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600546797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.1600546797
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.76723955
Short name T231
Test name
Test status
Simulation time 45981582130 ps
CPU time 114.75 seconds
Started Jul 11 04:53:41 PM PDT 24
Finished Jul 11 04:55:46 PM PDT 24
Peak memory 212472 kb
Host smart-7f1cbafe-804a-4016-a095-bbc1c77c5faf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76723955 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.76723955
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.930644581
Short name T464
Test name
Test status
Simulation time 10596534327 ps
CPU time 1.53 seconds
Started Jul 11 04:53:39 PM PDT 24
Finished Jul 11 04:53:50 PM PDT 24
Peak memory 201896 kb
Host smart-25a59584-24a4-4c98-88bd-d789a41c1544
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930644581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_ultra_low_pwr.930644581
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.2762472925
Short name T689
Test name
Test status
Simulation time 2016358137 ps
CPU time 3.08 seconds
Started Jul 11 04:53:45 PM PDT 24
Finished Jul 11 04:53:56 PM PDT 24
Peak memory 201632 kb
Host smart-4e8324c6-a3a7-40d1-be85-3aff6976210d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762472925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_te
st.2762472925
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2757551960
Short name T762
Test name
Test status
Simulation time 3407289595 ps
CPU time 5.21 seconds
Started Jul 11 04:53:38 PM PDT 24
Finished Jul 11 04:53:53 PM PDT 24
Peak memory 201656 kb
Host smart-fd8ee8d2-d075-4879-a7e8-1e2dad4aa608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757551960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.2
757551960
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.4001650697
Short name T706
Test name
Test status
Simulation time 101577091463 ps
CPU time 58 seconds
Started Jul 11 04:53:39 PM PDT 24
Finished Jul 11 04:54:47 PM PDT 24
Peak memory 201744 kb
Host smart-d98256c3-3c22-4879-af97-504f07d0f99c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001650697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.4001650697
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2081172150
Short name T641
Test name
Test status
Simulation time 26332518770 ps
CPU time 65.16 seconds
Started Jul 11 04:53:38 PM PDT 24
Finished Jul 11 04:54:51 PM PDT 24
Peak memory 201896 kb
Host smart-9e89cc05-8309-4cc2-bbec-2faf7b67f37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081172150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.2081172150
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2791358653
Short name T549
Test name
Test status
Simulation time 2657007727 ps
CPU time 0.93 seconds
Started Jul 11 04:53:41 PM PDT 24
Finished Jul 11 04:53:51 PM PDT 24
Peak memory 201612 kb
Host smart-8793f99f-05d1-4c6a-99a5-490d24942dc9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791358653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.2791358653
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.2945815497
Short name T208
Test name
Test status
Simulation time 2896263295 ps
CPU time 1.97 seconds
Started Jul 11 04:53:48 PM PDT 24
Finished Jul 11 04:53:58 PM PDT 24
Peak memory 201560 kb
Host smart-df740896-66c4-4144-9f50-3eaf161ecf08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945815497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.2945815497
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.3737687346
Short name T205
Test name
Test status
Simulation time 2610406491 ps
CPU time 7.43 seconds
Started Jul 11 04:53:48 PM PDT 24
Finished Jul 11 04:54:03 PM PDT 24
Peak memory 201620 kb
Host smart-91dc1a68-9b2e-467c-af37-7d58bde609a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737687346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.3737687346
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.451659503
Short name T516
Test name
Test status
Simulation time 2463600570 ps
CPU time 8.35 seconds
Started Jul 11 04:53:41 PM PDT 24
Finished Jul 11 04:53:59 PM PDT 24
Peak memory 201528 kb
Host smart-4f124810-3b70-4ec6-bc25-744e45d1c9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451659503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.451659503
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.3556188690
Short name T347
Test name
Test status
Simulation time 2184410193 ps
CPU time 2.17 seconds
Started Jul 11 04:53:38 PM PDT 24
Finished Jul 11 04:53:50 PM PDT 24
Peak memory 201480 kb
Host smart-528df764-15e9-4fef-b2bc-caa80b458dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556188690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.3556188690
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.491763679
Short name T70
Test name
Test status
Simulation time 2515611463 ps
CPU time 3.95 seconds
Started Jul 11 04:53:48 PM PDT 24
Finished Jul 11 04:54:00 PM PDT 24
Peak memory 201620 kb
Host smart-13ccfc66-09fe-48c2-b529-8d651bd864eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491763679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.491763679
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.1377355293
Short name T715
Test name
Test status
Simulation time 2110454900 ps
CPU time 5.65 seconds
Started Jul 11 04:53:39 PM PDT 24
Finished Jul 11 04:53:54 PM PDT 24
Peak memory 201504 kb
Host smart-f5273e3c-ab50-4257-8799-d10b879c8f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377355293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.1377355293
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.3819000590
Short name T615
Test name
Test status
Simulation time 38579293068 ps
CPU time 96.54 seconds
Started Jul 11 04:53:38 PM PDT 24
Finished Jul 11 04:55:25 PM PDT 24
Peak memory 218332 kb
Host smart-500ca649-ca8f-4326-b1eb-a229f13918e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819000590 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.3819000590
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.651881702
Short name T730
Test name
Test status
Simulation time 300332795824 ps
CPU time 15.05 seconds
Started Jul 11 04:53:36 PM PDT 24
Finished Jul 11 04:54:00 PM PDT 24
Peak memory 201624 kb
Host smart-15fc7202-e416-49c8-a162-5aa72ecca097
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651881702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_ultra_low_pwr.651881702
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.3561174459
Short name T604
Test name
Test status
Simulation time 2012355641 ps
CPU time 5.83 seconds
Started Jul 11 04:53:47 PM PDT 24
Finished Jul 11 04:54:01 PM PDT 24
Peak memory 201620 kb
Host smart-d5bd0ac9-1572-4d22-98fa-ee99b1a95c85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561174459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.3561174459
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.257922844
Short name T45
Test name
Test status
Simulation time 10172971214 ps
CPU time 27.26 seconds
Started Jul 11 04:53:44 PM PDT 24
Finished Jul 11 04:54:20 PM PDT 24
Peak memory 201592 kb
Host smart-18a39eda-bf2d-4d8f-b931-bc07f9ece01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257922844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.257922844
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.3796726755
Short name T712
Test name
Test status
Simulation time 89878300106 ps
CPU time 60.42 seconds
Started Jul 11 04:53:44 PM PDT 24
Finished Jul 11 04:54:53 PM PDT 24
Peak memory 202080 kb
Host smart-3b0a6456-8c20-4664-9aea-992896eb3435
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796726755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.3796726755
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.1513439935
Short name T113
Test name
Test status
Simulation time 3670338823 ps
CPU time 2.19 seconds
Started Jul 11 04:53:47 PM PDT 24
Finished Jul 11 04:53:58 PM PDT 24
Peak memory 201600 kb
Host smart-25867007-74c7-4fdd-932b-53be260bac59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513439935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.1513439935
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.4182754102
Short name T207
Test name
Test status
Simulation time 4092399110 ps
CPU time 4.78 seconds
Started Jul 11 04:53:42 PM PDT 24
Finished Jul 11 04:53:56 PM PDT 24
Peak memory 201608 kb
Host smart-182fd621-326c-4536-ab32-da989853c768
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182754102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.4182754102
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2775797030
Short name T543
Test name
Test status
Simulation time 2608969858 ps
CPU time 6.81 seconds
Started Jul 11 04:53:44 PM PDT 24
Finished Jul 11 04:53:59 PM PDT 24
Peak memory 201564 kb
Host smart-685d39d1-4823-4f40-a262-81666f342848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775797030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.2775797030
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.89206216
Short name T664
Test name
Test status
Simulation time 2506059293 ps
CPU time 2.25 seconds
Started Jul 11 04:53:37 PM PDT 24
Finished Jul 11 04:53:48 PM PDT 24
Peak memory 201532 kb
Host smart-2323bfda-4413-4df0-861a-f4be9e6db295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89206216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.89206216
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.2526853874
Short name T632
Test name
Test status
Simulation time 2027092531 ps
CPU time 5.65 seconds
Started Jul 11 04:53:46 PM PDT 24
Finished Jul 11 04:54:00 PM PDT 24
Peak memory 201432 kb
Host smart-e3822708-ac05-45e2-8f21-44d7c554bd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526853874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.2526853874
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.956169835
Short name T498
Test name
Test status
Simulation time 2536041132 ps
CPU time 2.28 seconds
Started Jul 11 04:53:47 PM PDT 24
Finished Jul 11 04:53:58 PM PDT 24
Peak memory 201556 kb
Host smart-186ab488-f9e7-439c-9c82-f5f716905c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956169835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.956169835
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.4233434902
Short name T432
Test name
Test status
Simulation time 2111563870 ps
CPU time 5.86 seconds
Started Jul 11 04:53:42 PM PDT 24
Finished Jul 11 04:53:57 PM PDT 24
Peak memory 201548 kb
Host smart-2071f515-b115-4438-b1b6-bfce38feef80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233434902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.4233434902
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.3069673010
Short name T451
Test name
Test status
Simulation time 15284511719 ps
CPU time 9.91 seconds
Started Jul 11 04:53:43 PM PDT 24
Finished Jul 11 04:54:02 PM PDT 24
Peak memory 201568 kb
Host smart-d3328c37-08a9-48f2-a1de-2cac7ce989f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069673010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s
tress_all.3069673010
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1612663085
Short name T232
Test name
Test status
Simulation time 84761893053 ps
CPU time 109.05 seconds
Started Jul 11 04:53:44 PM PDT 24
Finished Jul 11 04:55:42 PM PDT 24
Peak memory 210240 kb
Host smart-d2f94cc5-c413-425f-a06e-62a2af1de8a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612663085 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.1612663085
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2816565414
Short name T467
Test name
Test status
Simulation time 3773866431 ps
CPU time 2.38 seconds
Started Jul 11 04:53:44 PM PDT 24
Finished Jul 11 04:53:55 PM PDT 24
Peak memory 201604 kb
Host smart-10e4ca94-b1c3-451b-805b-b9902491acb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816565414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ultra_low_pwr.2816565414
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.3159896571
Short name T517
Test name
Test status
Simulation time 2019511424 ps
CPU time 2.98 seconds
Started Jul 11 04:53:44 PM PDT 24
Finished Jul 11 04:53:56 PM PDT 24
Peak memory 201532 kb
Host smart-e0c849cd-ab99-4c75-8dd0-b0b64ebc00bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159896571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.3159896571
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.2830703192
Short name T226
Test name
Test status
Simulation time 3629485148 ps
CPU time 1.83 seconds
Started Jul 11 04:53:45 PM PDT 24
Finished Jul 11 04:53:55 PM PDT 24
Peak memory 201700 kb
Host smart-974ce12d-602a-4ca2-876e-2582140a2dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830703192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.2
830703192
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.317288340
Short name T714
Test name
Test status
Simulation time 86469956637 ps
CPU time 230.77 seconds
Started Jul 11 04:53:50 PM PDT 24
Finished Jul 11 04:57:48 PM PDT 24
Peak memory 201848 kb
Host smart-2596a010-c82a-43c1-8b9d-f6fac859335c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317288340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_wi
th_pre_cond.317288340
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.2276554159
Short name T597
Test name
Test status
Simulation time 3057469157 ps
CPU time 2.69 seconds
Started Jul 11 04:53:44 PM PDT 24
Finished Jul 11 04:53:55 PM PDT 24
Peak memory 201512 kb
Host smart-281a777a-ff39-4f03-9af9-b5ab2a85b4af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276554159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ec_pwr_on_rst.2276554159
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.2512451105
Short name T150
Test name
Test status
Simulation time 3863849897 ps
CPU time 2.18 seconds
Started Jul 11 04:53:47 PM PDT 24
Finished Jul 11 04:53:58 PM PDT 24
Peak memory 201616 kb
Host smart-3614cbef-5db4-49e3-9e46-29a047696c2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512451105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.2512451105
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.2702439905
Short name T732
Test name
Test status
Simulation time 2701503066 ps
CPU time 1.16 seconds
Started Jul 11 04:53:52 PM PDT 24
Finished Jul 11 04:54:01 PM PDT 24
Peak memory 201632 kb
Host smart-a53d6424-18a1-4036-91ad-9794e21dd966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702439905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.2702439905
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.4276334850
Short name T647
Test name
Test status
Simulation time 2458368200 ps
CPU time 6.91 seconds
Started Jul 11 04:53:44 PM PDT 24
Finished Jul 11 04:54:00 PM PDT 24
Peak memory 201612 kb
Host smart-65303a9b-0cca-4c62-8d5e-729bd597ccc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276334850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.4276334850
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.622623829
Short name T417
Test name
Test status
Simulation time 2166458712 ps
CPU time 1.98 seconds
Started Jul 11 04:53:45 PM PDT 24
Finished Jul 11 04:53:55 PM PDT 24
Peak memory 201536 kb
Host smart-b5c86e55-fcc0-43bb-8449-6b8cdcb9f5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622623829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.622623829
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.2554877912
Short name T650
Test name
Test status
Simulation time 2529689234 ps
CPU time 2.37 seconds
Started Jul 11 04:53:53 PM PDT 24
Finished Jul 11 04:54:03 PM PDT 24
Peak memory 201636 kb
Host smart-fb7e462d-22b7-4ebe-a9dc-baae9fcd2e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554877912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.2554877912
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.619831821
Short name T562
Test name
Test status
Simulation time 2136591551 ps
CPU time 1.78 seconds
Started Jul 11 04:53:50 PM PDT 24
Finished Jul 11 04:53:59 PM PDT 24
Peak memory 201440 kb
Host smart-563a9238-af7f-4c2f-98c4-b361725b9914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619831821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.619831821
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.959895080
Short name T772
Test name
Test status
Simulation time 12611638202 ps
CPU time 28.61 seconds
Started Jul 11 04:53:46 PM PDT 24
Finished Jul 11 04:54:23 PM PDT 24
Peak memory 201508 kb
Host smart-38a7f855-29dd-49dc-b812-603f31deaf2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959895080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_st
ress_all.959895080
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.1325925580
Short name T340
Test name
Test status
Simulation time 46974398147 ps
CPU time 30.21 seconds
Started Jul 11 04:53:43 PM PDT 24
Finished Jul 11 04:54:22 PM PDT 24
Peak memory 210264 kb
Host smart-94996c34-9b41-4a25-8f5c-381f12f9deac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325925580 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.1325925580
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2971321501
Short name T761
Test name
Test status
Simulation time 536374411035 ps
CPU time 25.72 seconds
Started Jul 11 04:53:46 PM PDT 24
Finished Jul 11 04:54:19 PM PDT 24
Peak memory 201624 kb
Host smart-82c780ee-88bb-4124-bee4-d8525a68bfe9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971321501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.2971321501
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.2805067286
Short name T129
Test name
Test status
Simulation time 2015332951 ps
CPU time 4.71 seconds
Started Jul 11 04:52:53 PM PDT 24
Finished Jul 11 04:53:04 PM PDT 24
Peak memory 201632 kb
Host smart-5bae861a-719f-48b5-baee-1d2ede743cc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805067286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.2805067286
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.2148354058
Short name T671
Test name
Test status
Simulation time 3234921153 ps
CPU time 2.58 seconds
Started Jul 11 04:52:54 PM PDT 24
Finished Jul 11 04:53:02 PM PDT 24
Peak memory 201676 kb
Host smart-4396f3ed-078d-47f0-8bbf-ad67e21dd92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148354058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.2148354058
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.4004350843
Short name T121
Test name
Test status
Simulation time 148421625575 ps
CPU time 406.22 seconds
Started Jul 11 04:52:53 PM PDT 24
Finished Jul 11 04:59:46 PM PDT 24
Peak memory 201880 kb
Host smart-fd63e85c-b692-4684-96c9-f4bd948a71f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004350843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.4004350843
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.1449367437
Short name T618
Test name
Test status
Simulation time 2416772129 ps
CPU time 7.38 seconds
Started Jul 11 04:52:50 PM PDT 24
Finished Jul 11 04:53:04 PM PDT 24
Peak memory 201560 kb
Host smart-510a00b6-996b-4817-84bd-6c65bc36a281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449367437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.1449367437
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1391799956
Short name T10
Test name
Test status
Simulation time 2521694037 ps
CPU time 1.97 seconds
Started Jul 11 04:52:56 PM PDT 24
Finished Jul 11 04:53:04 PM PDT 24
Peak memory 201608 kb
Host smart-6c546ba0-df47-4f20-b108-5ac61c7e24a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391799956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1391799956
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2275821435
Short name T580
Test name
Test status
Simulation time 90266113025 ps
CPU time 223.93 seconds
Started Jul 11 04:52:56 PM PDT 24
Finished Jul 11 04:56:46 PM PDT 24
Peak memory 201920 kb
Host smart-c5b35f5d-2d7a-4926-b647-8a5b6606e02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275821435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.2275821435
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.4027817432
Short name T455
Test name
Test status
Simulation time 4099175648 ps
CPU time 6.46 seconds
Started Jul 11 04:52:54 PM PDT 24
Finished Jul 11 04:53:06 PM PDT 24
Peak memory 201856 kb
Host smart-0b1da88a-d412-44e3-9174-77c37a817a30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027817432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.4027817432
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.1793060595
Short name T209
Test name
Test status
Simulation time 3249197201 ps
CPU time 2.21 seconds
Started Jul 11 04:52:50 PM PDT 24
Finished Jul 11 04:52:58 PM PDT 24
Peak memory 201588 kb
Host smart-0bc643b4-f3bd-4990-a3d7-574b52ac2ff0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793060595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.1793060595
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2711664747
Short name T770
Test name
Test status
Simulation time 2610247202 ps
CPU time 7.48 seconds
Started Jul 11 04:52:53 PM PDT 24
Finished Jul 11 04:53:06 PM PDT 24
Peak memory 200924 kb
Host smart-fd1c5917-988c-44dc-bc98-f825142ca673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711664747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.2711664747
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.1564727279
Short name T777
Test name
Test status
Simulation time 2474288172 ps
CPU time 7.27 seconds
Started Jul 11 04:52:55 PM PDT 24
Finished Jul 11 04:53:08 PM PDT 24
Peak memory 201540 kb
Host smart-35851c8f-9fe1-454f-9e09-a4f4a69c5859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564727279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.1564727279
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.4104545204
Short name T623
Test name
Test status
Simulation time 2119220562 ps
CPU time 1.7 seconds
Started Jul 11 04:52:54 PM PDT 24
Finished Jul 11 04:53:02 PM PDT 24
Peak memory 201508 kb
Host smart-8a794f51-11ff-46fb-ba3d-aedad9d697c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104545204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.4104545204
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.790715617
Short name T784
Test name
Test status
Simulation time 2509889839 ps
CPU time 7.36 seconds
Started Jul 11 04:52:52 PM PDT 24
Finished Jul 11 04:53:06 PM PDT 24
Peak memory 201636 kb
Host smart-fe11c51c-3ae9-4abe-85ae-d8c137466a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790715617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.790715617
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.750859602
Short name T479
Test name
Test status
Simulation time 2119632261 ps
CPU time 3.35 seconds
Started Jul 11 04:52:51 PM PDT 24
Finished Jul 11 04:53:01 PM PDT 24
Peak memory 201484 kb
Host smart-c683ca0a-ded5-4b02-a2da-280c8dcd3b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750859602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.750859602
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.999534407
Short name T241
Test name
Test status
Simulation time 13636873194 ps
CPU time 34.01 seconds
Started Jul 11 04:52:53 PM PDT 24
Finished Jul 11 04:53:34 PM PDT 24
Peak memory 201860 kb
Host smart-feb89eca-6022-4afd-8beb-7cd487f33c8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999534407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_str
ess_all.999534407
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.1714713829
Short name T142
Test name
Test status
Simulation time 6534738399 ps
CPU time 2.62 seconds
Started Jul 11 04:52:52 PM PDT 24
Finished Jul 11 04:53:01 PM PDT 24
Peak memory 201608 kb
Host smart-32e673af-b2e3-4f5e-9dc5-a3cae4114619
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714713829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.1714713829
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.2580534692
Short name T222
Test name
Test status
Simulation time 2037243584 ps
CPU time 1.9 seconds
Started Jul 11 04:53:53 PM PDT 24
Finished Jul 11 04:54:02 PM PDT 24
Peak memory 201636 kb
Host smart-960ee627-e587-460f-b6f6-5ee7403f430f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580534692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.2580534692
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.3448069605
Short name T488
Test name
Test status
Simulation time 3838125723 ps
CPU time 2.59 seconds
Started Jul 11 04:53:47 PM PDT 24
Finished Jul 11 04:53:58 PM PDT 24
Peak memory 201648 kb
Host smart-d4053010-de0a-44cd-a1d7-27ca9e69f542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448069605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.3
448069605
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.1183090895
Short name T268
Test name
Test status
Simulation time 43113123223 ps
CPU time 58.71 seconds
Started Jul 11 04:53:50 PM PDT 24
Finished Jul 11 04:54:56 PM PDT 24
Peak memory 201860 kb
Host smart-7700e8d5-7717-44e7-ace0-a467bec826dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183090895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.1183090895
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.836579050
Short name T434
Test name
Test status
Simulation time 2897556201 ps
CPU time 2.69 seconds
Started Jul 11 04:53:44 PM PDT 24
Finished Jul 11 04:53:55 PM PDT 24
Peak memory 201604 kb
Host smart-2df46c60-399f-4e34-beba-13e1be780fb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836579050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_ec_pwr_on_rst.836579050
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1685455136
Short name T352
Test name
Test status
Simulation time 2635908031 ps
CPU time 2.55 seconds
Started Jul 11 04:53:53 PM PDT 24
Finished Jul 11 04:54:03 PM PDT 24
Peak memory 201636 kb
Host smart-dafe6fc0-f9b0-4092-8f09-70a94d173e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685455136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.1685455136
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.3621770817
Short name T447
Test name
Test status
Simulation time 2478355827 ps
CPU time 7.42 seconds
Started Jul 11 04:53:44 PM PDT 24
Finished Jul 11 04:54:00 PM PDT 24
Peak memory 201628 kb
Host smart-517e3c5f-f846-47f8-9b68-368d52bdc9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621770817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.3621770817
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.190835307
Short name T620
Test name
Test status
Simulation time 2050503205 ps
CPU time 5.86 seconds
Started Jul 11 04:53:48 PM PDT 24
Finished Jul 11 04:54:02 PM PDT 24
Peak memory 201440 kb
Host smart-824e20f0-20c1-4b8c-b3f0-00cf8878c977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190835307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.190835307
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.3262411501
Short name T550
Test name
Test status
Simulation time 2527371977 ps
CPU time 2.28 seconds
Started Jul 11 04:53:47 PM PDT 24
Finished Jul 11 04:53:57 PM PDT 24
Peak memory 201536 kb
Host smart-58519c91-0af9-45ef-b805-69dfe1d86d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262411501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.3262411501
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.1285345244
Short name T50
Test name
Test status
Simulation time 2122143868 ps
CPU time 2.1 seconds
Started Jul 11 04:53:48 PM PDT 24
Finished Jul 11 04:53:58 PM PDT 24
Peak memory 201488 kb
Host smart-c27052f9-edfb-45b5-afe9-b18f6109fd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285345244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.1285345244
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.1256354846
Short name T154
Test name
Test status
Simulation time 12376022746 ps
CPU time 8.6 seconds
Started Jul 11 04:53:51 PM PDT 24
Finished Jul 11 04:54:07 PM PDT 24
Peak memory 201604 kb
Host smart-14048388-92f0-44f4-9e8d-ff5ddfdae37c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256354846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.1256354846
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.83613539
Short name T94
Test name
Test status
Simulation time 5572026353 ps
CPU time 3.95 seconds
Started Jul 11 04:53:45 PM PDT 24
Finished Jul 11 04:53:57 PM PDT 24
Peak memory 201616 kb
Host smart-fc89acaf-250c-4466-b267-7531a5109379
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83613539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_ultra_low_pwr.83613539
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.2061519806
Short name T413
Test name
Test status
Simulation time 2101263274 ps
CPU time 1.14 seconds
Started Jul 11 04:53:54 PM PDT 24
Finished Jul 11 04:54:04 PM PDT 24
Peak memory 201580 kb
Host smart-96a2c9fd-ccae-4e8b-bcf7-a4dc2fbdc5b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061519806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.2061519806
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3304225310
Short name T750
Test name
Test status
Simulation time 294969692833 ps
CPU time 809.15 seconds
Started Jul 11 04:53:51 PM PDT 24
Finished Jul 11 05:07:27 PM PDT 24
Peak memory 201624 kb
Host smart-c0553e59-89ad-4c26-b46e-2800325d28ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304225310 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.3
304225310
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.1658686154
Short name T8
Test name
Test status
Simulation time 163947954313 ps
CPU time 86.93 seconds
Started Jul 11 04:53:54 PM PDT 24
Finished Jul 11 04:55:30 PM PDT 24
Peak memory 201852 kb
Host smart-e8ad6de5-6300-4ad0-9183-d63ac402208f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658686154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.1658686154
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.2096149046
Short name T243
Test name
Test status
Simulation time 91405117161 ps
CPU time 248.96 seconds
Started Jul 11 04:53:58 PM PDT 24
Finished Jul 11 04:58:17 PM PDT 24
Peak memory 201864 kb
Host smart-ddd99f86-55eb-431a-a01b-5b0d6aede284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096149046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.2096149046
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3793463220
Short name T575
Test name
Test status
Simulation time 5177185870 ps
CPU time 6.15 seconds
Started Jul 11 04:53:56 PM PDT 24
Finished Jul 11 04:54:11 PM PDT 24
Peak memory 201604 kb
Host smart-422b2e76-110e-4084-b9fc-2354fa3431d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793463220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.3793463220
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.2720952195
Short name T713
Test name
Test status
Simulation time 3545106260 ps
CPU time 2.91 seconds
Started Jul 11 04:53:57 PM PDT 24
Finished Jul 11 04:54:08 PM PDT 24
Peak memory 201512 kb
Host smart-0f02440d-aaa8-4980-b35a-fcc07ab68a85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720952195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.2720952195
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.727751603
Short name T602
Test name
Test status
Simulation time 2614731382 ps
CPU time 7.41 seconds
Started Jul 11 04:53:52 PM PDT 24
Finished Jul 11 04:54:07 PM PDT 24
Peak memory 201552 kb
Host smart-97d3538a-a9f4-41bf-b482-e7005f7bbb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727751603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.727751603
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.200794433
Short name T26
Test name
Test status
Simulation time 2452385963 ps
CPU time 6.34 seconds
Started Jul 11 04:53:52 PM PDT 24
Finished Jul 11 04:54:06 PM PDT 24
Peak memory 201628 kb
Host smart-6ee858ea-22d4-4d22-b7cb-745d950063d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200794433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.200794433
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.971488197
Short name T422
Test name
Test status
Simulation time 2086254386 ps
CPU time 5.8 seconds
Started Jul 11 04:53:54 PM PDT 24
Finished Jul 11 04:54:08 PM PDT 24
Peak memory 201520 kb
Host smart-9e28834b-ff71-40ac-993d-330ba4c11e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971488197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.971488197
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.3496142487
Short name T481
Test name
Test status
Simulation time 2511687694 ps
CPU time 6.99 seconds
Started Jul 11 04:53:55 PM PDT 24
Finished Jul 11 04:54:10 PM PDT 24
Peak memory 201544 kb
Host smart-07d03b41-caaf-404f-8217-b2814850b31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496142487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.3496142487
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.439162697
Short name T608
Test name
Test status
Simulation time 2116269026 ps
CPU time 3.31 seconds
Started Jul 11 04:53:59 PM PDT 24
Finished Jul 11 04:54:12 PM PDT 24
Peak memory 201500 kb
Host smart-8d9a01c9-a245-48ed-a061-7625d6fd8006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439162697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.439162697
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.95722915
Short name T393
Test name
Test status
Simulation time 170311712822 ps
CPU time 111.6 seconds
Started Jul 11 04:53:56 PM PDT 24
Finished Jul 11 04:55:56 PM PDT 24
Peak memory 201728 kb
Host smart-621ec49e-9db8-4fad-8551-722a1c5a8883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95722915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_str
ess_all.95722915
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.58901747
Short name T591
Test name
Test status
Simulation time 4630485980 ps
CPU time 5.83 seconds
Started Jul 11 04:53:57 PM PDT 24
Finished Jul 11 04:54:11 PM PDT 24
Peak memory 201636 kb
Host smart-7e4d46ee-7817-497f-b226-53e9da604fe1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58901747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_ultra_low_pwr.58901747
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.4181788000
Short name T186
Test name
Test status
Simulation time 2036182375 ps
CPU time 2.02 seconds
Started Jul 11 04:53:55 PM PDT 24
Finished Jul 11 04:54:05 PM PDT 24
Peak memory 201872 kb
Host smart-420305b6-f376-4766-b07f-ff02aef67071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181788000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te
st.4181788000
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.1072620773
Short name T716
Test name
Test status
Simulation time 3108730351 ps
CPU time 4.33 seconds
Started Jul 11 04:53:55 PM PDT 24
Finished Jul 11 04:54:08 PM PDT 24
Peak memory 201596 kb
Host smart-dc5f2238-4409-4256-bdd0-a314a6abf572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072620773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.1
072620773
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.3674160464
Short name T2
Test name
Test status
Simulation time 169503155607 ps
CPU time 81.98 seconds
Started Jul 11 04:53:58 PM PDT 24
Finished Jul 11 04:55:30 PM PDT 24
Peak memory 201828 kb
Host smart-3eb4bf01-35a4-4a59-96c8-ed5b8e8be5d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674160464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.3674160464
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.4118311462
Short name T100
Test name
Test status
Simulation time 27340394694 ps
CPU time 36.88 seconds
Started Jul 11 04:53:54 PM PDT 24
Finished Jul 11 04:54:39 PM PDT 24
Peak memory 201800 kb
Host smart-bde3b76b-91d0-407d-8e78-360e931ef7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118311462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_w
ith_pre_cond.4118311462
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.3150471072
Short name T654
Test name
Test status
Simulation time 2760229530 ps
CPU time 4.2 seconds
Started Jul 11 04:53:54 PM PDT 24
Finished Jul 11 04:54:07 PM PDT 24
Peak memory 201604 kb
Host smart-1e31c9c9-cb19-4cfb-8951-e9c02709c766
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150471072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.3150471072
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.593445417
Short name T173
Test name
Test status
Simulation time 5160202793 ps
CPU time 3.17 seconds
Started Jul 11 04:53:57 PM PDT 24
Finished Jul 11 04:54:08 PM PDT 24
Peak memory 201620 kb
Host smart-63bbcaab-c6f3-48f1-916d-a65279ad8ab1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593445417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctr
l_edge_detect.593445417
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3666268669
Short name T640
Test name
Test status
Simulation time 2642313447 ps
CPU time 1.66 seconds
Started Jul 11 04:53:52 PM PDT 24
Finished Jul 11 04:54:02 PM PDT 24
Peak memory 201560 kb
Host smart-f4ecb362-54be-4623-86c2-ddedb5540131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666268669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3666268669
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.225713260
Short name T61
Test name
Test status
Simulation time 2489658269 ps
CPU time 6.81 seconds
Started Jul 11 04:53:56 PM PDT 24
Finished Jul 11 04:54:11 PM PDT 24
Peak memory 201540 kb
Host smart-60de0dba-09af-4979-9f60-ebd2fe06c2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225713260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.225713260
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.492577604
Short name T536
Test name
Test status
Simulation time 2273665556 ps
CPU time 0.98 seconds
Started Jul 11 04:53:53 PM PDT 24
Finished Jul 11 04:54:02 PM PDT 24
Peak memory 201532 kb
Host smart-1e221b73-7b71-42cb-a847-ac30c7a43fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492577604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.492577604
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.1292195640
Short name T768
Test name
Test status
Simulation time 2524832246 ps
CPU time 2.42 seconds
Started Jul 11 04:53:57 PM PDT 24
Finished Jul 11 04:54:08 PM PDT 24
Peak memory 201640 kb
Host smart-6331f0f9-2b21-4c17-99f4-048a2ffaf415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292195640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.1292195640
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.278565215
Short name T62
Test name
Test status
Simulation time 2113856844 ps
CPU time 5.58 seconds
Started Jul 11 04:53:52 PM PDT 24
Finished Jul 11 04:54:06 PM PDT 24
Peak memory 201492 kb
Host smart-498d3c3b-792b-4ab2-989e-8780a724b1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278565215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.278565215
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.1915469619
Short name T266
Test name
Test status
Simulation time 33150133083 ps
CPU time 20.44 seconds
Started Jul 11 04:53:50 PM PDT 24
Finished Jul 11 04:54:18 PM PDT 24
Peak memory 201744 kb
Host smart-2327d01a-ec63-455d-be9b-3150d12c09fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915469619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s
tress_all.1915469619
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1965376042
Short name T238
Test name
Test status
Simulation time 33062962598 ps
CPU time 11.67 seconds
Started Jul 11 04:53:52 PM PDT 24
Finished Jul 11 04:54:11 PM PDT 24
Peak memory 210324 kb
Host smart-906df23a-ff97-4cc3-8027-c62ad95b6fa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965376042 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.1965376042
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.2144452906
Short name T720
Test name
Test status
Simulation time 2459552920685 ps
CPU time 76.34 seconds
Started Jul 11 04:53:54 PM PDT 24
Finished Jul 11 04:55:19 PM PDT 24
Peak memory 201516 kb
Host smart-b7440373-8b11-4cb5-97c4-632839d3c502
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144452906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.2144452906
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.3210471079
Short name T528
Test name
Test status
Simulation time 2020661892 ps
CPU time 3.22 seconds
Started Jul 11 04:53:58 PM PDT 24
Finished Jul 11 04:54:10 PM PDT 24
Peak memory 201584 kb
Host smart-4d7d9127-dc82-4f43-aa54-9b19a8f4de7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210471079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.3210471079
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.71945862
Short name T589
Test name
Test status
Simulation time 3667745483 ps
CPU time 3.05 seconds
Started Jul 11 04:53:58 PM PDT 24
Finished Jul 11 04:54:11 PM PDT 24
Peak memory 201648 kb
Host smart-505cbca0-5b16-4c77-b07c-b1ebe28c0493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71945862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.71945862
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.4021159917
Short name T225
Test name
Test status
Simulation time 116205049145 ps
CPU time 146.66 seconds
Started Jul 11 04:53:54 PM PDT 24
Finished Jul 11 04:56:29 PM PDT 24
Peak memory 201880 kb
Host smart-4962c4bb-b703-49c8-a36a-96d96a991634
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021159917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.4021159917
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.919515658
Short name T86
Test name
Test status
Simulation time 79205642206 ps
CPU time 14.31 seconds
Started Jul 11 04:53:58 PM PDT 24
Finished Jul 11 04:54:22 PM PDT 24
Peak memory 201780 kb
Host smart-6aa517b6-b3bf-4bdc-8a56-513c743c2a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919515658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_wi
th_pre_cond.919515658
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1192906774
Short name T442
Test name
Test status
Simulation time 3960964544 ps
CPU time 10.62 seconds
Started Jul 11 04:53:55 PM PDT 24
Finished Jul 11 04:54:14 PM PDT 24
Peak memory 201516 kb
Host smart-7d763119-f924-41b6-8d94-a30039e0bea3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192906774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.1192906774
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.3281525144
Short name T492
Test name
Test status
Simulation time 2413091437 ps
CPU time 7.11 seconds
Started Jul 11 04:53:55 PM PDT 24
Finished Jul 11 04:54:10 PM PDT 24
Peak memory 201536 kb
Host smart-26787ef0-189a-4a85-8c02-51004933df3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281525144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.3281525144
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.624358355
Short name T572
Test name
Test status
Simulation time 2614236376 ps
CPU time 3.99 seconds
Started Jul 11 04:54:06 PM PDT 24
Finished Jul 11 04:54:19 PM PDT 24
Peak memory 201632 kb
Host smart-fc9e9d42-c7bd-43ba-a6f0-beaff001c23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624358355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.624358355
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.3708583733
Short name T172
Test name
Test status
Simulation time 2501158547 ps
CPU time 1.65 seconds
Started Jul 11 04:53:55 PM PDT 24
Finished Jul 11 04:54:05 PM PDT 24
Peak memory 201540 kb
Host smart-c4769599-c3bb-4717-bdd4-2273c2a39d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708583733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.3708583733
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3463052482
Short name T17
Test name
Test status
Simulation time 2244736252 ps
CPU time 2.22 seconds
Started Jul 11 04:53:57 PM PDT 24
Finished Jul 11 04:54:08 PM PDT 24
Peak memory 201564 kb
Host smart-caef2b0e-5a09-4bfb-a0ff-6a3823333211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463052482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.3463052482
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.2189198887
Short name T202
Test name
Test status
Simulation time 2510615455 ps
CPU time 7.26 seconds
Started Jul 11 04:53:58 PM PDT 24
Finished Jul 11 04:54:14 PM PDT 24
Peak memory 201616 kb
Host smart-923f7b6e-f699-48ae-8c9a-015e43209280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189198887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.2189198887
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.3085314185
Short name T445
Test name
Test status
Simulation time 2125788451 ps
CPU time 1.89 seconds
Started Jul 11 04:53:56 PM PDT 24
Finished Jul 11 04:54:07 PM PDT 24
Peak memory 201368 kb
Host smart-f2928650-02ca-41f8-a5c6-d151ae4bc1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085314185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.3085314185
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.2205386555
Short name T763
Test name
Test status
Simulation time 14903586821 ps
CPU time 9.72 seconds
Started Jul 11 04:53:59 PM PDT 24
Finished Jul 11 04:54:19 PM PDT 24
Peak memory 201688 kb
Host smart-9fd17600-4417-48bc-b5a7-e8016f3fab29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205386555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.2205386555
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.172467599
Short name T190
Test name
Test status
Simulation time 4118146587 ps
CPU time 6.29 seconds
Started Jul 11 04:54:03 PM PDT 24
Finished Jul 11 04:54:18 PM PDT 24
Peak memory 201616 kb
Host smart-dc93a675-5670-491c-95d2-979b0ed4ffdb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172467599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_ultra_low_pwr.172467599
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.3472080781
Short name T586
Test name
Test status
Simulation time 2118773951 ps
CPU time 1.14 seconds
Started Jul 11 04:53:57 PM PDT 24
Finished Jul 11 04:54:07 PM PDT 24
Peak memory 201500 kb
Host smart-4ec589ac-0ce8-4e5b-8455-26565e9b4a1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472080781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_te
st.3472080781
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2061897066
Short name T743
Test name
Test status
Simulation time 3594428271 ps
CPU time 2.85 seconds
Started Jul 11 04:53:56 PM PDT 24
Finished Jul 11 04:54:07 PM PDT 24
Peak memory 201696 kb
Host smart-99cd2f75-15c0-46a9-b551-015abb978aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061897066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.2
061897066
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.3755805218
Short name T398
Test name
Test status
Simulation time 111870794274 ps
CPU time 57.52 seconds
Started Jul 11 04:53:58 PM PDT 24
Finished Jul 11 04:55:05 PM PDT 24
Peak memory 201836 kb
Host smart-f1ef40b5-a286-4526-86b5-ad0e6b55f934
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755805218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.3755805218
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.958722249
Short name T521
Test name
Test status
Simulation time 2744057044 ps
CPU time 2.51 seconds
Started Jul 11 04:54:05 PM PDT 24
Finished Jul 11 04:54:16 PM PDT 24
Peak memory 201604 kb
Host smart-0abfa8b6-0b01-4f7a-994e-4bb8543eef13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958722249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_ec_pwr_on_rst.958722249
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.1046957271
Short name T181
Test name
Test status
Simulation time 2692099126 ps
CPU time 6.42 seconds
Started Jul 11 04:53:57 PM PDT 24
Finished Jul 11 04:54:13 PM PDT 24
Peak memory 201536 kb
Host smart-e70be5e8-94f0-4566-82b8-0a720ac81276
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046957271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.1046957271
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.2007200453
Short name T533
Test name
Test status
Simulation time 2612278411 ps
CPU time 7.22 seconds
Started Jul 11 04:53:57 PM PDT 24
Finished Jul 11 04:54:14 PM PDT 24
Peak memory 201592 kb
Host smart-c332402e-eebf-4b1a-b88a-ed8e8594f079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007200453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.2007200453
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.945047599
Short name T759
Test name
Test status
Simulation time 2487983814 ps
CPU time 3.69 seconds
Started Jul 11 04:53:56 PM PDT 24
Finished Jul 11 04:54:08 PM PDT 24
Peak memory 201640 kb
Host smart-3a804687-e431-425f-a492-32fb07254da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945047599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.945047599
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.4216726765
Short name T656
Test name
Test status
Simulation time 2325875388 ps
CPU time 1.23 seconds
Started Jul 11 04:53:56 PM PDT 24
Finished Jul 11 04:54:05 PM PDT 24
Peak memory 201468 kb
Host smart-5ae40584-bac6-4194-bd53-3ae0a03c15cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216726765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.4216726765
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.2958641072
Short name T755
Test name
Test status
Simulation time 2527204919 ps
CPU time 3.41 seconds
Started Jul 11 04:53:57 PM PDT 24
Finished Jul 11 04:54:09 PM PDT 24
Peak memory 201636 kb
Host smart-b289d8a1-c060-4e4c-bc2a-24a4713841ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958641072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.2958641072
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.1848293023
Short name T13
Test name
Test status
Simulation time 2110893872 ps
CPU time 6.05 seconds
Started Jul 11 04:53:58 PM PDT 24
Finished Jul 11 04:54:14 PM PDT 24
Peak memory 201516 kb
Host smart-678afc37-d78f-4130-9d70-c5c3efcd0ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848293023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.1848293023
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.3787174899
Short name T745
Test name
Test status
Simulation time 16124142858 ps
CPU time 10.17 seconds
Started Jul 11 04:53:58 PM PDT 24
Finished Jul 11 04:54:18 PM PDT 24
Peak memory 201560 kb
Host smart-68d99bce-70ce-4d86-b889-cbbe7626c306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787174899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.3787174899
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2072126973
Short name T660
Test name
Test status
Simulation time 6236617494 ps
CPU time 2.49 seconds
Started Jul 11 04:54:06 PM PDT 24
Finished Jul 11 04:54:17 PM PDT 24
Peak memory 201640 kb
Host smart-33f87800-1991-4f03-92a5-307997298dd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072126973 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ultra_low_pwr.2072126973
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.3073732946
Short name T548
Test name
Test status
Simulation time 2058949912 ps
CPU time 1.35 seconds
Started Jul 11 04:53:59 PM PDT 24
Finished Jul 11 04:54:10 PM PDT 24
Peak memory 201632 kb
Host smart-2f06c2e7-9d1a-4ea7-a212-85425754ae48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073732946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.3073732946
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2062297777
Short name T740
Test name
Test status
Simulation time 3410709732 ps
CPU time 5.16 seconds
Started Jul 11 04:54:06 PM PDT 24
Finished Jul 11 04:54:20 PM PDT 24
Peak memory 201608 kb
Host smart-60bf3fb1-327b-4188-8f60-b543b85fad42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062297777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.2
062297777
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.1771921174
Short name T782
Test name
Test status
Simulation time 192846400502 ps
CPU time 513.25 seconds
Started Jul 11 04:54:02 PM PDT 24
Finished Jul 11 05:02:45 PM PDT 24
Peak memory 201760 kb
Host smart-dff7ccf4-21fe-4bed-955d-d824f7e1d51e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771921174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_combo_detect.1771921174
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.3847803817
Short name T633
Test name
Test status
Simulation time 2685579247 ps
CPU time 2.19 seconds
Started Jul 11 04:53:59 PM PDT 24
Finished Jul 11 04:54:11 PM PDT 24
Peak memory 201544 kb
Host smart-6d7975b7-8eb5-44ff-815f-4cafe4880ce5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847803817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ec_pwr_on_rst.3847803817
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.1027006238
Short name T72
Test name
Test status
Simulation time 2911542356 ps
CPU time 2.5 seconds
Started Jul 11 04:53:59 PM PDT 24
Finished Jul 11 04:54:11 PM PDT 24
Peak memory 201592 kb
Host smart-1c9c070a-0d1e-463c-a4b5-089539a5b67b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027006238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.1027006238
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.3739505027
Short name T742
Test name
Test status
Simulation time 2676412153 ps
CPU time 1.41 seconds
Started Jul 11 04:53:57 PM PDT 24
Finished Jul 11 04:54:07 PM PDT 24
Peak memory 201532 kb
Host smart-f01ecdc3-200b-460e-9f3b-041bf29f511f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739505027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.3739505027
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.1349291241
Short name T738
Test name
Test status
Simulation time 2485155478 ps
CPU time 3.81 seconds
Started Jul 11 04:54:02 PM PDT 24
Finished Jul 11 04:54:15 PM PDT 24
Peak memory 201636 kb
Host smart-b1c60e92-2783-4838-9348-c614b6670619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349291241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.1349291241
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.2109330172
Short name T117
Test name
Test status
Simulation time 2066449108 ps
CPU time 5.93 seconds
Started Jul 11 04:53:58 PM PDT 24
Finished Jul 11 04:54:14 PM PDT 24
Peak memory 201424 kb
Host smart-19416276-891d-4b2a-a711-adf04673ce41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109330172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.2109330172
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.2785262194
Short name T563
Test name
Test status
Simulation time 2514133771 ps
CPU time 7.19 seconds
Started Jul 11 04:53:57 PM PDT 24
Finished Jul 11 04:54:14 PM PDT 24
Peak memory 201616 kb
Host smart-d2589863-10f8-406d-9b96-6551eb34be05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785262194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.2785262194
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.3317391813
Short name T443
Test name
Test status
Simulation time 2115123146 ps
CPU time 3.19 seconds
Started Jul 11 04:53:58 PM PDT 24
Finished Jul 11 04:54:11 PM PDT 24
Peak memory 201468 kb
Host smart-51a32c80-12ad-43df-b1d3-e8694a788203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317391813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.3317391813
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.2486682907
Short name T330
Test name
Test status
Simulation time 92676454573 ps
CPU time 239.82 seconds
Started Jul 11 04:53:59 PM PDT 24
Finished Jul 11 04:58:09 PM PDT 24
Peak memory 201792 kb
Host smart-09e7114a-e9f2-4986-b1b5-3dae8fafb656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486682907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.2486682907
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.2740105781
Short name T275
Test name
Test status
Simulation time 102777227684 ps
CPU time 66.33 seconds
Started Jul 11 04:54:01 PM PDT 24
Finished Jul 11 04:55:17 PM PDT 24
Peak memory 210272 kb
Host smart-c6593dad-e793-4aca-b97f-abae37dbd84f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740105781 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.2740105781
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.3218696433
Short name T356
Test name
Test status
Simulation time 2041740987 ps
CPU time 2.06 seconds
Started Jul 11 04:53:58 PM PDT 24
Finished Jul 11 04:54:09 PM PDT 24
Peak memory 201600 kb
Host smart-558517b0-3f8b-4c4c-9d5b-133e5bc32a8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218696433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.3218696433
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.1366910950
Short name T624
Test name
Test status
Simulation time 3220817863 ps
CPU time 2.84 seconds
Started Jul 11 04:54:05 PM PDT 24
Finished Jul 11 04:54:16 PM PDT 24
Peak memory 201700 kb
Host smart-2b2e8b61-e633-4113-bd7d-4d5554cc95e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366910950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.1
366910950
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.420241660
Short name T267
Test name
Test status
Simulation time 86265471613 ps
CPU time 153.79 seconds
Started Jul 11 04:54:01 PM PDT 24
Finished Jul 11 04:56:44 PM PDT 24
Peak memory 201896 kb
Host smart-86468dd1-1683-48c0-a9ae-497cd0d2c081
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420241660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_combo_detect.420241660
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2795332750
Short name T386
Test name
Test status
Simulation time 54183063352 ps
CPU time 15.97 seconds
Started Jul 11 04:53:57 PM PDT 24
Finished Jul 11 04:54:22 PM PDT 24
Peak memory 201836 kb
Host smart-10dfae18-6163-4ae8-b1ce-768c15dc1311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795332750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_w
ith_pre_cond.2795332750
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.3464206397
Short name T704
Test name
Test status
Simulation time 2814143166 ps
CPU time 1.29 seconds
Started Jul 11 04:54:02 PM PDT 24
Finished Jul 11 04:54:13 PM PDT 24
Peak memory 201500 kb
Host smart-5ff8049e-0e0d-457c-947f-45673b3625cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464206397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ec_pwr_on_rst.3464206397
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.60919033
Short name T748
Test name
Test status
Simulation time 3134188608 ps
CPU time 6.78 seconds
Started Jul 11 04:54:05 PM PDT 24
Finished Jul 11 04:54:20 PM PDT 24
Peak memory 201608 kb
Host smart-f468bde0-da35-4572-be0a-bfbd4a166b5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60919033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl
_edge_detect.60919033
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.4275028059
Short name T472
Test name
Test status
Simulation time 2668195336 ps
CPU time 1.29 seconds
Started Jul 11 04:54:01 PM PDT 24
Finished Jul 11 04:54:12 PM PDT 24
Peak memory 201560 kb
Host smart-9911b7c6-3cac-4f9c-b114-688b5a3d7cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275028059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.4275028059
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.534917955
Short name T754
Test name
Test status
Simulation time 2478441093 ps
CPU time 2.48 seconds
Started Jul 11 04:54:06 PM PDT 24
Finished Jul 11 04:54:17 PM PDT 24
Peak memory 201508 kb
Host smart-74efb213-079a-4550-821a-e951897a8dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534917955 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.534917955
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.3772771959
Short name T723
Test name
Test status
Simulation time 2207045011 ps
CPU time 1.92 seconds
Started Jul 11 04:54:01 PM PDT 24
Finished Jul 11 04:54:12 PM PDT 24
Peak memory 201636 kb
Host smart-141f9930-e857-450b-93b4-e14541431259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772771959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.3772771959
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.1304327709
Short name T544
Test name
Test status
Simulation time 2510579304 ps
CPU time 7.37 seconds
Started Jul 11 04:53:58 PM PDT 24
Finished Jul 11 04:54:15 PM PDT 24
Peak memory 201596 kb
Host smart-d926e3e4-48ca-4d10-a951-ffa53bde928a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304327709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.1304327709
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.3254581133
Short name T470
Test name
Test status
Simulation time 2134243411 ps
CPU time 1.88 seconds
Started Jul 11 04:54:05 PM PDT 24
Finished Jul 11 04:54:16 PM PDT 24
Peak memory 201424 kb
Host smart-32eecfad-9595-44e1-8675-24b2f384a8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254581133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.3254581133
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.3011442507
Short name T336
Test name
Test status
Simulation time 10231088965 ps
CPU time 25.61 seconds
Started Jul 11 04:54:06 PM PDT 24
Finished Jul 11 04:54:40 PM PDT 24
Peak memory 201592 kb
Host smart-ba0430e5-3127-4f30-80c0-bb8fb7ab90b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011442507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.3011442507
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.4165436442
Short name T240
Test name
Test status
Simulation time 17418887841 ps
CPU time 44.29 seconds
Started Jul 11 04:54:02 PM PDT 24
Finished Jul 11 04:54:55 PM PDT 24
Peak memory 201676 kb
Host smart-151cca2f-ac2f-4b73-8253-5d4a35e3cb29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165436442 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.4165436442
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.1999414949
Short name T648
Test name
Test status
Simulation time 2014080540 ps
CPU time 5.49 seconds
Started Jul 11 04:54:13 PM PDT 24
Finished Jul 11 04:54:26 PM PDT 24
Peak memory 201544 kb
Host smart-0a67e09a-9207-4e86-86c8-d57a03bcf043
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999414949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.1999414949
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2106985079
Short name T774
Test name
Test status
Simulation time 3505400841 ps
CPU time 2.97 seconds
Started Jul 11 04:54:02 PM PDT 24
Finished Jul 11 04:54:15 PM PDT 24
Peak memory 201696 kb
Host smart-c8e08d56-6974-4d3a-a7f6-0acdd4698385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106985079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.2
106985079
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.1631838745
Short name T685
Test name
Test status
Simulation time 98733532048 ps
CPU time 226.55 seconds
Started Jul 11 04:54:08 PM PDT 24
Finished Jul 11 04:58:04 PM PDT 24
Peak memory 201768 kb
Host smart-93d90d6c-84dd-42ec-a8ca-fc648bd311c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631838745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.1631838745
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2046331911
Short name T605
Test name
Test status
Simulation time 78024404822 ps
CPU time 108.05 seconds
Started Jul 11 04:54:06 PM PDT 24
Finished Jul 11 04:56:02 PM PDT 24
Peak memory 201844 kb
Host smart-c3796874-54e8-4280-87fa-7dd458d48d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046331911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_w
ith_pre_cond.2046331911
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.423760354
Short name T49
Test name
Test status
Simulation time 3144381066 ps
CPU time 1.28 seconds
Started Jul 11 04:53:58 PM PDT 24
Finished Jul 11 04:54:08 PM PDT 24
Peak memory 201856 kb
Host smart-f74c7957-6045-41c2-bce6-3951ecc1f82e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423760354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_ec_pwr_on_rst.423760354
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.1464323988
Short name T185
Test name
Test status
Simulation time 4202744752 ps
CPU time 3.37 seconds
Started Jul 11 04:54:07 PM PDT 24
Finished Jul 11 04:54:20 PM PDT 24
Peak memory 201640 kb
Host smart-cf3d669b-6441-4cbc-bbca-2203a5d7d14e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464323988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.1464323988
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.803333667
Short name T551
Test name
Test status
Simulation time 2630329138 ps
CPU time 2.02 seconds
Started Jul 11 04:54:03 PM PDT 24
Finished Jul 11 04:54:14 PM PDT 24
Peak memory 201640 kb
Host smart-4280e819-5019-463b-afa4-51f0041d9aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803333667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.803333667
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.3086207931
Short name T333
Test name
Test status
Simulation time 2450087265 ps
CPU time 6.71 seconds
Started Jul 11 04:54:09 PM PDT 24
Finished Jul 11 04:54:24 PM PDT 24
Peak memory 201528 kb
Host smart-73484250-50c7-4cb8-a614-89d6756a6b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086207931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.3086207931
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.1003867756
Short name T429
Test name
Test status
Simulation time 2029992560 ps
CPU time 3.79 seconds
Started Jul 11 04:54:09 PM PDT 24
Finished Jul 11 04:54:21 PM PDT 24
Peak memory 201400 kb
Host smart-1d612ab4-5781-4774-a085-e36eee32f272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003867756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.1003867756
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.3157330116
Short name T468
Test name
Test status
Simulation time 2508730921 ps
CPU time 7.5 seconds
Started Jul 11 04:53:57 PM PDT 24
Finished Jul 11 04:54:13 PM PDT 24
Peak memory 201644 kb
Host smart-743cfc4e-a824-4420-9707-b7b99a7fb8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157330116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.3157330116
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.1549331272
Short name T119
Test name
Test status
Simulation time 2108877787 ps
CPU time 6.09 seconds
Started Jul 11 04:53:57 PM PDT 24
Finished Jul 11 04:54:12 PM PDT 24
Peak memory 201468 kb
Host smart-b5e97682-0f76-457d-a765-a937495bf78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549331272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.1549331272
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.408614245
Short name T418
Test name
Test status
Simulation time 7831286124 ps
CPU time 10.25 seconds
Started Jul 11 04:54:06 PM PDT 24
Finished Jul 11 04:54:25 PM PDT 24
Peak memory 201528 kb
Host smart-4b4ade0c-7745-4d8a-93ff-96cc5474242a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408614245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_st
ress_all.408614245
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.992686893
Short name T144
Test name
Test status
Simulation time 1339076878231 ps
CPU time 57.9 seconds
Started Jul 11 04:54:06 PM PDT 24
Finished Jul 11 04:55:12 PM PDT 24
Peak memory 201512 kb
Host smart-7ead9f5f-8dff-49cd-8d4b-f0550e4b2565
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992686893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_ultra_low_pwr.992686893
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.2758835806
Short name T598
Test name
Test status
Simulation time 2044674695 ps
CPU time 1.93 seconds
Started Jul 11 04:54:05 PM PDT 24
Finished Jul 11 04:54:15 PM PDT 24
Peak memory 201584 kb
Host smart-d101af94-f1a3-4086-9993-7f74ccbcfce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758835806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.2758835806
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3429944243
Short name T48
Test name
Test status
Simulation time 264702267670 ps
CPU time 48.87 seconds
Started Jul 11 04:54:07 PM PDT 24
Finished Jul 11 04:55:04 PM PDT 24
Peak memory 201700 kb
Host smart-290b876d-658d-4416-a7b7-08698ab0293b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429944243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.3
429944243
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.2156595556
Short name T676
Test name
Test status
Simulation time 183915876127 ps
CPU time 57.55 seconds
Started Jul 11 04:54:07 PM PDT 24
Finished Jul 11 04:55:13 PM PDT 24
Peak memory 201880 kb
Host smart-5e064627-cf7d-4bf4-a6f0-6737de338cc4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156595556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.2156595556
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.3435098089
Short name T570
Test name
Test status
Simulation time 3125742251 ps
CPU time 2.67 seconds
Started Jul 11 04:54:04 PM PDT 24
Finished Jul 11 04:54:15 PM PDT 24
Peak memory 201604 kb
Host smart-e0f021ff-6660-46c5-8b95-d4751c9b98b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435098089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ec_pwr_on_rst.3435098089
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.24101229
Short name T568
Test name
Test status
Simulation time 2939297455 ps
CPU time 7.74 seconds
Started Jul 11 04:54:06 PM PDT 24
Finished Jul 11 04:54:22 PM PDT 24
Peak memory 201500 kb
Host smart-a67cdeac-eafc-45bd-9b88-f0021982f787
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24101229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl
_edge_detect.24101229
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2541043774
Short name T355
Test name
Test status
Simulation time 2625965707 ps
CPU time 2.46 seconds
Started Jul 11 04:54:06 PM PDT 24
Finished Jul 11 04:54:17 PM PDT 24
Peak memory 201640 kb
Host smart-a1bac8af-4b4b-4354-a4ae-1ee113a07a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541043774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.2541043774
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.3413013173
Short name T613
Test name
Test status
Simulation time 2488800929 ps
CPU time 2.37 seconds
Started Jul 11 04:54:06 PM PDT 24
Finished Jul 11 04:54:17 PM PDT 24
Peak memory 201612 kb
Host smart-25d62af4-4c75-4877-ae7a-70a535e492d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413013173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.3413013173
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.1774869039
Short name T731
Test name
Test status
Simulation time 2129738695 ps
CPU time 3.24 seconds
Started Jul 11 04:54:03 PM PDT 24
Finished Jul 11 04:54:15 PM PDT 24
Peak memory 201760 kb
Host smart-9cc3b23e-3910-40d3-8ad7-354301fc98bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774869039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.1774869039
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.1387448408
Short name T663
Test name
Test status
Simulation time 2569910399 ps
CPU time 1.21 seconds
Started Jul 11 04:54:13 PM PDT 24
Finished Jul 11 04:54:22 PM PDT 24
Peak memory 201560 kb
Host smart-9bafa097-f8d7-453f-852f-bf0b4b6847d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387448408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.1387448408
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.763716078
Short name T131
Test name
Test status
Simulation time 2185431387 ps
CPU time 1.05 seconds
Started Jul 11 04:54:08 PM PDT 24
Finished Jul 11 04:54:18 PM PDT 24
Peak memory 201532 kb
Host smart-525baca3-ed0a-431c-bb44-1cd6e70dc53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763716078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.763716078
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.278144628
Short name T545
Test name
Test status
Simulation time 15900533953 ps
CPU time 11.6 seconds
Started Jul 11 04:54:04 PM PDT 24
Finished Jul 11 04:54:24 PM PDT 24
Peak memory 201612 kb
Host smart-b9257c25-2ba4-4085-88b5-07979e26ef95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278144628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_st
ress_all.278144628
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.1677098103
Short name T328
Test name
Test status
Simulation time 40759557953 ps
CPU time 109.02 seconds
Started Jul 11 04:54:04 PM PDT 24
Finished Jul 11 04:56:02 PM PDT 24
Peak memory 210100 kb
Host smart-a8ef04d5-0393-4352-bcd9-a477f706154c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677098103 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.1677098103
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.558796552
Short name T78
Test name
Test status
Simulation time 7732961484 ps
CPU time 2.16 seconds
Started Jul 11 04:54:12 PM PDT 24
Finished Jul 11 04:54:22 PM PDT 24
Peak memory 201268 kb
Host smart-8b304972-d3c2-4cf4-8b3f-2b93d6ddfe92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558796552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ultra_low_pwr.558796552
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.3931656914
Short name T695
Test name
Test status
Simulation time 2033507340 ps
CPU time 1.87 seconds
Started Jul 11 04:54:13 PM PDT 24
Finished Jul 11 04:54:23 PM PDT 24
Peak memory 201516 kb
Host smart-d310cec1-a0c2-4bbf-941d-727ff33cf5b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931656914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.3931656914
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.2839497258
Short name T114
Test name
Test status
Simulation time 3673898707 ps
CPU time 3.97 seconds
Started Jul 11 04:54:12 PM PDT 24
Finished Jul 11 04:54:24 PM PDT 24
Peak memory 201268 kb
Host smart-dc0c62c3-79e3-42c6-8908-c0ab1fd86074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839497258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.2
839497258
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.1840762308
Short name T109
Test name
Test status
Simulation time 26913131637 ps
CPU time 17.93 seconds
Started Jul 11 04:54:06 PM PDT 24
Finished Jul 11 04:54:33 PM PDT 24
Peak memory 201828 kb
Host smart-9c22cf20-4137-4792-86c4-7b82b79ab508
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840762308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.1840762308
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2721055683
Short name T581
Test name
Test status
Simulation time 57831598422 ps
CPU time 149.24 seconds
Started Jul 11 04:54:09 PM PDT 24
Finished Jul 11 04:56:46 PM PDT 24
Peak memory 201844 kb
Host smart-5a54dcb4-5415-4ce3-834a-42c1209a8ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721055683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.2721055683
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.2808004070
Short name T735
Test name
Test status
Simulation time 3220270955 ps
CPU time 8.65 seconds
Started Jul 11 05:03:18 PM PDT 24
Finished Jul 11 05:03:27 PM PDT 24
Peak memory 201608 kb
Host smart-772193c1-0909-4527-b7d7-a2d1a0219004
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808004070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.2808004070
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.4180631876
Short name T756
Test name
Test status
Simulation time 2816965057 ps
CPU time 2.41 seconds
Started Jul 11 04:54:04 PM PDT 24
Finished Jul 11 04:54:15 PM PDT 24
Peak memory 201508 kb
Host smart-352a12fa-9eae-4d7f-a392-2f89a90564af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180631876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct
rl_edge_detect.4180631876
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1851420095
Short name T579
Test name
Test status
Simulation time 2614298961 ps
CPU time 7.05 seconds
Started Jul 11 04:54:07 PM PDT 24
Finished Jul 11 04:54:23 PM PDT 24
Peak memory 201620 kb
Host smart-8ce9154f-53fc-4115-9039-9f67e9d8c562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851420095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.1851420095
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.1574648186
Short name T466
Test name
Test status
Simulation time 2519948797 ps
CPU time 1.7 seconds
Started Jul 11 04:54:06 PM PDT 24
Finished Jul 11 04:54:16 PM PDT 24
Peak memory 201536 kb
Host smart-e8e247ef-2043-4a58-b2c4-3761539f74cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574648186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.1574648186
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.2103971217
Short name T532
Test name
Test status
Simulation time 2278092633 ps
CPU time 2.02 seconds
Started Jul 11 04:54:10 PM PDT 24
Finished Jul 11 04:54:20 PM PDT 24
Peak memory 201568 kb
Host smart-cc6a59ab-3b47-4627-8447-237e4cc1ee65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103971217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.2103971217
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1779235342
Short name T621
Test name
Test status
Simulation time 2540292311 ps
CPU time 1.96 seconds
Started Jul 11 04:54:07 PM PDT 24
Finished Jul 11 04:54:17 PM PDT 24
Peak memory 201536 kb
Host smart-2f1a53bc-e7b5-4f07-b6f5-0f68c6ab6f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779235342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.1779235342
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.1029218019
Short name T614
Test name
Test status
Simulation time 2120654175 ps
CPU time 2.04 seconds
Started Jul 11 04:54:05 PM PDT 24
Finished Jul 11 04:54:15 PM PDT 24
Peak memory 201436 kb
Host smart-a7f4a7c5-e0f8-4064-a915-3dd208bebe9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029218019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.1029218019
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.1348778086
Short name T123
Test name
Test status
Simulation time 16981590691 ps
CPU time 4.46 seconds
Started Jul 11 04:54:11 PM PDT 24
Finished Jul 11 04:54:23 PM PDT 24
Peak memory 201600 kb
Host smart-f0bbced6-8ee5-4677-99cc-39331a40ff9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348778086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.1348778086
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.1300961375
Short name T453
Test name
Test status
Simulation time 2023116505 ps
CPU time 3.16 seconds
Started Jul 11 04:52:50 PM PDT 24
Finished Jul 11 04:53:00 PM PDT 24
Peak memory 201556 kb
Host smart-7c803614-7b97-4221-ae21-db52c49c8d17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300961375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.1300961375
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.3488651211
Short name T679
Test name
Test status
Simulation time 3357947477 ps
CPU time 8.86 seconds
Started Jul 11 04:52:56 PM PDT 24
Finished Jul 11 04:53:11 PM PDT 24
Peak memory 201696 kb
Host smart-62e371cf-e78e-4d32-bbc5-9d4446797f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488651211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.3488651211
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.3879899056
Short name T374
Test name
Test status
Simulation time 113740518668 ps
CPU time 281.82 seconds
Started Jul 11 04:53:03 PM PDT 24
Finished Jul 11 04:57:50 PM PDT 24
Peak memory 201880 kb
Host smart-961dd7af-4655-439d-90ee-6aeca7dc5d62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879899056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_combo_detect.3879899056
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.3722401370
Short name T192
Test name
Test status
Simulation time 2221994146 ps
CPU time 3.34 seconds
Started Jul 11 04:52:57 PM PDT 24
Finished Jul 11 04:53:06 PM PDT 24
Peak memory 201636 kb
Host smart-e77e70e6-e8d3-41c5-9e37-c85fc99b8374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722401370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.3722401370
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2592887160
Short name T765
Test name
Test status
Simulation time 2530101790 ps
CPU time 2.33 seconds
Started Jul 11 04:52:57 PM PDT 24
Finished Jul 11 04:53:05 PM PDT 24
Peak memory 201608 kb
Host smart-91943c50-de33-4350-9695-61d471630080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592887160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2592887160
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.585425602
Short name T51
Test name
Test status
Simulation time 4167396000 ps
CPU time 11.71 seconds
Started Jul 11 04:52:52 PM PDT 24
Finished Jul 11 04:53:09 PM PDT 24
Peak memory 201608 kb
Host smart-b73b2f39-1936-4962-869f-f9fdb91f5e87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585425602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_ec_pwr_on_rst.585425602
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.1781390835
Short name T567
Test name
Test status
Simulation time 2709682278 ps
CPU time 1.75 seconds
Started Jul 11 04:52:54 PM PDT 24
Finished Jul 11 04:53:02 PM PDT 24
Peak memory 201596 kb
Host smart-45e992c8-8896-4506-8197-b12d634216be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781390835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.1781390835
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.3557518479
Short name T587
Test name
Test status
Simulation time 2636407479 ps
CPU time 2.51 seconds
Started Jul 11 04:52:52 PM PDT 24
Finished Jul 11 04:53:00 PM PDT 24
Peak memory 201864 kb
Host smart-e29db22d-326c-4e65-9c3a-032f7996e38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557518479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.3557518479
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.540295645
Short name T542
Test name
Test status
Simulation time 2466086797 ps
CPU time 4.34 seconds
Started Jul 11 04:52:53 PM PDT 24
Finished Jul 11 04:53:04 PM PDT 24
Peak memory 201628 kb
Host smart-14ddfe68-96f4-4a8b-83f1-e2629cd0afc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540295645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.540295645
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.2933778867
Short name T511
Test name
Test status
Simulation time 2163710341 ps
CPU time 3.39 seconds
Started Jul 11 04:52:51 PM PDT 24
Finished Jul 11 04:53:01 PM PDT 24
Peak memory 201524 kb
Host smart-8a297141-49f8-4adc-a6b2-01e5a30c2294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933778867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.2933778867
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.3664335832
Short name T335
Test name
Test status
Simulation time 2514436388 ps
CPU time 7.15 seconds
Started Jul 11 04:52:54 PM PDT 24
Finished Jul 11 04:53:08 PM PDT 24
Peak memory 201544 kb
Host smart-36ef6b1c-aa39-4cc8-8634-ea5ed760aab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664335832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.3664335832
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.2512758847
Short name T293
Test name
Test status
Simulation time 42026426168 ps
CPU time 55.73 seconds
Started Jul 11 04:52:54 PM PDT 24
Finished Jul 11 04:53:56 PM PDT 24
Peak memory 221124 kb
Host smart-24804935-b514-447f-afa2-ef8f8a520271
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512758847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.2512758847
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.3232296151
Short name T747
Test name
Test status
Simulation time 2110552542 ps
CPU time 5.98 seconds
Started Jul 11 04:52:53 PM PDT 24
Finished Jul 11 04:53:05 PM PDT 24
Peak memory 200764 kb
Host smart-66e2aa35-1922-4bd7-9c60-6912803ec705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232296151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.3232296151
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.3737377137
Short name T588
Test name
Test status
Simulation time 15425596166 ps
CPU time 4.11 seconds
Started Jul 11 04:52:55 PM PDT 24
Finished Jul 11 04:53:06 PM PDT 24
Peak memory 201616 kb
Host smart-65399616-fb9f-4df2-8328-82c61a5ce111
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737377137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.3737377137
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2611622727
Short name T325
Test name
Test status
Simulation time 45672828904 ps
CPU time 82.45 seconds
Started Jul 11 04:53:01 PM PDT 24
Finished Jul 11 04:54:29 PM PDT 24
Peak memory 210228 kb
Host smart-a870e9ce-c0ff-49a8-9e99-228613244d99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611622727 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.2611622727
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.2788484659
Short name T578
Test name
Test status
Simulation time 6324355533 ps
CPU time 1.14 seconds
Started Jul 11 04:52:49 PM PDT 24
Finished Jul 11 04:52:57 PM PDT 24
Peak memory 201648 kb
Host smart-5c72e56e-5737-4686-9503-9303de111392
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788484659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ultra_low_pwr.2788484659
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.1714011772
Short name T538
Test name
Test status
Simulation time 2013160909 ps
CPU time 6.03 seconds
Started Jul 11 04:54:12 PM PDT 24
Finished Jul 11 04:54:26 PM PDT 24
Peak memory 201628 kb
Host smart-29eb0076-5ffa-4bca-92e6-d9bfa232c868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714011772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_te
st.1714011772
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1094937186
Short name T269
Test name
Test status
Simulation time 3327193024 ps
CPU time 8.93 seconds
Started Jul 11 04:54:17 PM PDT 24
Finished Jul 11 04:54:34 PM PDT 24
Peak memory 201680 kb
Host smart-0770dc8c-aa42-4fa9-9fbd-3aa5dcbc78ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094937186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.1
094937186
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.1278162202
Short name T284
Test name
Test status
Simulation time 99057888471 ps
CPU time 63.8 seconds
Started Jul 11 04:54:10 PM PDT 24
Finished Jul 11 04:55:22 PM PDT 24
Peak memory 201732 kb
Host smart-3188f4b0-dfde-44a3-8269-a3075be862ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278162202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.1278162202
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.3525638857
Short name T76
Test name
Test status
Simulation time 21578763657 ps
CPU time 59.56 seconds
Started Jul 11 04:54:11 PM PDT 24
Finished Jul 11 04:55:18 PM PDT 24
Peak memory 201712 kb
Host smart-f61c6ab4-b610-469e-8a78-b74eab3f300c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525638857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.3525638857
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.257398003
Short name T616
Test name
Test status
Simulation time 3293352857 ps
CPU time 2.6 seconds
Started Jul 11 04:54:12 PM PDT 24
Finished Jul 11 04:54:23 PM PDT 24
Peak memory 201616 kb
Host smart-6a2733e4-b423-4d42-9662-c8956e120c97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257398003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_ec_pwr_on_rst.257398003
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.2052033261
Short name T692
Test name
Test status
Simulation time 2958852230 ps
CPU time 1.02 seconds
Started Jul 11 04:54:10 PM PDT 24
Finished Jul 11 04:54:19 PM PDT 24
Peak memory 201488 kb
Host smart-9a15817e-472e-46ae-b779-d3d9b533fe9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052033261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_edge_detect.2052033261
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3909421495
Short name T416
Test name
Test status
Simulation time 2611701923 ps
CPU time 3.76 seconds
Started Jul 11 04:54:11 PM PDT 24
Finished Jul 11 04:54:23 PM PDT 24
Peak memory 201616 kb
Host smart-76c4bc89-8795-4954-9dcb-0db330f909f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909421495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.3909421495
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2422408617
Short name T65
Test name
Test status
Simulation time 2486057227 ps
CPU time 7.45 seconds
Started Jul 11 04:54:21 PM PDT 24
Finished Jul 11 04:54:38 PM PDT 24
Peak memory 201628 kb
Host smart-b8967b04-142e-4884-aca2-80d0b6955a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422408617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.2422408617
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.98020938
Short name T456
Test name
Test status
Simulation time 2116629070 ps
CPU time 5.9 seconds
Started Jul 11 04:54:15 PM PDT 24
Finished Jul 11 04:54:29 PM PDT 24
Peak memory 201508 kb
Host smart-ac850dce-752c-47ca-9e94-f83dcded04af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98020938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.98020938
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.4040358097
Short name T433
Test name
Test status
Simulation time 2520818416 ps
CPU time 2.43 seconds
Started Jul 11 04:54:12 PM PDT 24
Finished Jul 11 04:54:22 PM PDT 24
Peak memory 201532 kb
Host smart-b4402fb3-e562-42e0-b6e6-76ab316df910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040358097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.4040358097
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.649971321
Short name T709
Test name
Test status
Simulation time 2147475936 ps
CPU time 1.63 seconds
Started Jul 11 04:54:12 PM PDT 24
Finished Jul 11 04:54:21 PM PDT 24
Peak memory 201400 kb
Host smart-28ba3ac7-0db4-4b35-947f-f58bacdd8b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649971321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.649971321
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.955756898
Short name T265
Test name
Test status
Simulation time 38681367291 ps
CPU time 35.8 seconds
Started Jul 11 04:54:11 PM PDT 24
Finished Jul 11 04:54:55 PM PDT 24
Peak memory 201704 kb
Host smart-30357c32-c868-4f30-9a0e-7ffe3f49daee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955756898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_st
ress_all.955756898
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1877216790
Short name T327
Test name
Test status
Simulation time 18281604404 ps
CPU time 46.63 seconds
Started Jul 11 04:54:15 PM PDT 24
Finished Jul 11 04:55:10 PM PDT 24
Peak memory 201768 kb
Host smart-6b3a5220-ba00-43c5-b3a8-8d0cee4d22d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877216790 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.1877216790
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.1099768352
Short name T764
Test name
Test status
Simulation time 72329874085 ps
CPU time 2.58 seconds
Started Jul 11 04:54:11 PM PDT 24
Finished Jul 11 04:54:22 PM PDT 24
Peak memory 201616 kb
Host smart-d9f32856-8e3f-4c49-b67a-6a87ef6f2983
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099768352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ultra_low_pwr.1099768352
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.4006352799
Short name T448
Test name
Test status
Simulation time 2030860796 ps
CPU time 2.02 seconds
Started Jul 11 04:54:14 PM PDT 24
Finished Jul 11 04:54:24 PM PDT 24
Peak memory 201524 kb
Host smart-1fe0d434-6f31-49d1-8a49-4ceecdca941e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006352799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.4006352799
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.175979106
Short name T569
Test name
Test status
Simulation time 3408099343 ps
CPU time 5.25 seconds
Started Jul 11 04:54:15 PM PDT 24
Finished Jul 11 04:54:28 PM PDT 24
Peak memory 201732 kb
Host smart-433a725b-f3f0-437c-953b-6b08e9df98d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175979106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.175979106
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.2236930800
Short name T271
Test name
Test status
Simulation time 124933876292 ps
CPU time 340.97 seconds
Started Jul 11 04:54:14 PM PDT 24
Finished Jul 11 05:00:03 PM PDT 24
Peak memory 201856 kb
Host smart-1a0275c7-f2bf-4a46-9f4c-c86b3120cd5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236930800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.2236930800
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2864131040
Short name T531
Test name
Test status
Simulation time 59455059558 ps
CPU time 40.34 seconds
Started Jul 11 04:54:14 PM PDT 24
Finished Jul 11 04:55:02 PM PDT 24
Peak memory 201852 kb
Host smart-9d0acab5-5cfb-4f16-a0c3-7ab7cb544767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864131040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.2864131040
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.3326169046
Short name T345
Test name
Test status
Simulation time 3105883375 ps
CPU time 8.37 seconds
Started Jul 11 04:54:11 PM PDT 24
Finished Jul 11 04:54:27 PM PDT 24
Peak memory 201448 kb
Host smart-70bad6b7-b586-46bd-9d62-75c37321824d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326169046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ec_pwr_on_rst.3326169046
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2706460748
Short name T132
Test name
Test status
Simulation time 2624057454 ps
CPU time 2.38 seconds
Started Jul 11 04:54:15 PM PDT 24
Finished Jul 11 04:54:25 PM PDT 24
Peak memory 201628 kb
Host smart-08aa9181-1b71-4d61-b072-0ac6ed5c71b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706460748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.2706460748
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.639543610
Short name T722
Test name
Test status
Simulation time 2524283646 ps
CPU time 1.44 seconds
Started Jul 11 04:54:13 PM PDT 24
Finished Jul 11 04:54:23 PM PDT 24
Peak memory 201592 kb
Host smart-23bd946b-a8b7-4dc8-8622-9062dc115092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639543610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.639543610
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.4158209913
Short name T412
Test name
Test status
Simulation time 2259158222 ps
CPU time 2.03 seconds
Started Jul 11 04:54:10 PM PDT 24
Finished Jul 11 04:54:20 PM PDT 24
Peak memory 201440 kb
Host smart-4ff2ebd7-385a-44fc-9809-b639c2263c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158209913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.4158209913
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.4162903107
Short name T749
Test name
Test status
Simulation time 2566662176 ps
CPU time 1.14 seconds
Started Jul 11 04:54:13 PM PDT 24
Finished Jul 11 04:54:23 PM PDT 24
Peak memory 201616 kb
Host smart-6d6ae5ff-2b13-4484-9476-7bac2c903d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162903107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.4162903107
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.1749538712
Short name T318
Test name
Test status
Simulation time 2121497054 ps
CPU time 3.3 seconds
Started Jul 11 04:54:14 PM PDT 24
Finished Jul 11 04:54:25 PM PDT 24
Peak memory 201444 kb
Host smart-3dafede1-1e5c-4308-af35-279b05df0d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749538712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.1749538712
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1265279434
Short name T122
Test name
Test status
Simulation time 34861467272 ps
CPU time 34.08 seconds
Started Jul 11 04:54:09 PM PDT 24
Finished Jul 11 04:54:51 PM PDT 24
Peak memory 210284 kb
Host smart-a83f80e6-67a7-49f7-ba96-70d9481eed98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265279434 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.1265279434
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.904743056
Short name T135
Test name
Test status
Simulation time 5986789700 ps
CPU time 7.14 seconds
Started Jul 11 04:54:14 PM PDT 24
Finished Jul 11 04:54:29 PM PDT 24
Peak memory 201608 kb
Host smart-e18dd64e-a111-43d5-ab9f-0a42fc7aa659
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904743056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_ultra_low_pwr.904743056
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.2754826487
Short name T465
Test name
Test status
Simulation time 2014917662 ps
CPU time 5.26 seconds
Started Jul 11 04:54:21 PM PDT 24
Finished Jul 11 04:54:34 PM PDT 24
Peak memory 201624 kb
Host smart-d289711c-b541-4d9f-90e0-00c681b1a1c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754826487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.2754826487
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.962464611
Short name T539
Test name
Test status
Simulation time 3468069470 ps
CPU time 9.76 seconds
Started Jul 11 04:54:17 PM PDT 24
Finished Jul 11 04:54:35 PM PDT 24
Peak memory 201604 kb
Host smart-f99a9f5f-a8c1-49d5-b8d1-bf9929003dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962464611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.962464611
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2739929160
Short name T530
Test name
Test status
Simulation time 91525563537 ps
CPU time 242.31 seconds
Started Jul 11 04:54:18 PM PDT 24
Finished Jul 11 04:58:29 PM PDT 24
Peak memory 201860 kb
Host smart-2829985e-b322-487a-812e-898a521ab4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739929160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.2739929160
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.2741080115
Short name T410
Test name
Test status
Simulation time 5580634155 ps
CPU time 15.36 seconds
Started Jul 11 04:54:23 PM PDT 24
Finished Jul 11 04:54:47 PM PDT 24
Peak memory 201612 kb
Host smart-185c691b-683a-473c-bd30-f55fb1bf8c13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741080115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ec_pwr_on_rst.2741080115
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.1216322832
Short name T420
Test name
Test status
Simulation time 2727507209 ps
CPU time 6.84 seconds
Started Jul 11 04:54:19 PM PDT 24
Finished Jul 11 04:54:35 PM PDT 24
Peak memory 201532 kb
Host smart-480fbb8b-dbfc-4ba2-90d3-e3b51bd06ccc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216322832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_edge_detect.1216322832
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.1329675581
Short name T167
Test name
Test status
Simulation time 2633034572 ps
CPU time 2.42 seconds
Started Jul 11 04:54:16 PM PDT 24
Finished Jul 11 04:54:26 PM PDT 24
Peak memory 201616 kb
Host smart-6764bd5e-570e-4710-aa4b-06b11b71bc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329675581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.1329675581
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.1478100170
Short name T475
Test name
Test status
Simulation time 2487449452 ps
CPU time 2.22 seconds
Started Jul 11 04:54:18 PM PDT 24
Finished Jul 11 04:54:29 PM PDT 24
Peak memory 201628 kb
Host smart-0c1518cc-413d-4f37-8197-55bcad1845a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478100170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.1478100170
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.2061486116
Short name T159
Test name
Test status
Simulation time 2220312277 ps
CPU time 3.52 seconds
Started Jul 11 04:54:18 PM PDT 24
Finished Jul 11 04:54:30 PM PDT 24
Peak memory 201532 kb
Host smart-d29b8cef-cdf6-417b-a4a3-5b8f9cfe02e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061486116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.2061486116
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.1278617862
Short name T337
Test name
Test status
Simulation time 2523246748 ps
CPU time 3.67 seconds
Started Jul 11 04:54:23 PM PDT 24
Finished Jul 11 04:54:36 PM PDT 24
Peak memory 201632 kb
Host smart-61b800a1-9787-4cf4-96f6-e3290f88f0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278617862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.1278617862
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.971375362
Short name T523
Test name
Test status
Simulation time 2115095380 ps
CPU time 5.43 seconds
Started Jul 11 04:54:17 PM PDT 24
Finished Jul 11 04:54:31 PM PDT 24
Peak memory 201464 kb
Host smart-428016b5-60b0-4075-9f17-e4498c2781f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971375362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.971375362
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.2784164725
Short name T149
Test name
Test status
Simulation time 12533302768 ps
CPU time 15.02 seconds
Started Jul 11 04:54:18 PM PDT 24
Finished Jul 11 04:54:42 PM PDT 24
Peak memory 201612 kb
Host smart-56fd6209-b25e-4623-bdfc-629f74bfdd92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784164725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.2784164725
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2834745944
Short name T179
Test name
Test status
Simulation time 49141659319 ps
CPU time 113.09 seconds
Started Jul 11 04:54:23 PM PDT 24
Finished Jul 11 04:56:26 PM PDT 24
Peak memory 210268 kb
Host smart-9ff5baf9-a02d-447d-a227-8c16dbe45c6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834745944 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.2834745944
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1534871738
Short name T487
Test name
Test status
Simulation time 4741658140 ps
CPU time 2.05 seconds
Started Jul 11 04:54:18 PM PDT 24
Finished Jul 11 04:54:29 PM PDT 24
Peak memory 201576 kb
Host smart-47cc1610-c08a-4f1b-b93f-b5e9d8ee13b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534871738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.1534871738
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.3970729175
Short name T596
Test name
Test status
Simulation time 2033115815 ps
CPU time 2.11 seconds
Started Jul 11 04:54:24 PM PDT 24
Finished Jul 11 04:54:35 PM PDT 24
Peak memory 201632 kb
Host smart-3f10d36f-e435-4ec3-a7a2-3be6293759b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970729175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.3970729175
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2893468638
Short name T669
Test name
Test status
Simulation time 3478903896 ps
CPU time 2.81 seconds
Started Jul 11 04:54:23 PM PDT 24
Finished Jul 11 04:54:35 PM PDT 24
Peak memory 201732 kb
Host smart-1cca98bd-4e7e-42ee-8fe3-567b121afff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893468638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.2
893468638
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.1120877637
Short name T372
Test name
Test status
Simulation time 53850485864 ps
CPU time 35.67 seconds
Started Jul 11 04:54:19 PM PDT 24
Finished Jul 11 04:55:03 PM PDT 24
Peak memory 201792 kb
Host smart-b476b0f5-9441-44f1-9203-99d78fc625bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120877637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.1120877637
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2290927694
Short name T383
Test name
Test status
Simulation time 61310216217 ps
CPU time 37.67 seconds
Started Jul 11 04:54:17 PM PDT 24
Finished Jul 11 04:55:03 PM PDT 24
Peak memory 201836 kb
Host smart-01e2dcff-7633-4cfd-83fa-46a6d91f34f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290927694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_w
ith_pre_cond.2290927694
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2702936649
Short name T655
Test name
Test status
Simulation time 4677989138 ps
CPU time 13.6 seconds
Started Jul 11 04:54:20 PM PDT 24
Finished Jul 11 04:54:42 PM PDT 24
Peak memory 201456 kb
Host smart-affd0c50-1e53-4407-9eec-aea99cc06611
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702936649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.2702936649
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.3942006195
Short name T767
Test name
Test status
Simulation time 3161655942 ps
CPU time 2.19 seconds
Started Jul 11 04:54:17 PM PDT 24
Finished Jul 11 04:54:28 PM PDT 24
Peak memory 201588 kb
Host smart-eb55e19a-4250-4076-975f-6aabaf83c8ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942006195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.3942006195
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1541258613
Short name T662
Test name
Test status
Simulation time 2612377173 ps
CPU time 4.06 seconds
Started Jul 11 04:54:23 PM PDT 24
Finished Jul 11 04:54:37 PM PDT 24
Peak memory 201640 kb
Host smart-f4304afd-7f94-4a46-bbb9-35de7fb6b30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541258613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.1541258613
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.4095073540
Short name T682
Test name
Test status
Simulation time 2539331187 ps
CPU time 1.33 seconds
Started Jul 11 04:54:20 PM PDT 24
Finished Jul 11 04:54:30 PM PDT 24
Peak memory 201520 kb
Host smart-8f13dfa0-dcc0-44a8-8175-564df42b078a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095073540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.4095073540
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.2646772365
Short name T556
Test name
Test status
Simulation time 2071968293 ps
CPU time 1.91 seconds
Started Jul 11 04:54:18 PM PDT 24
Finished Jul 11 04:54:28 PM PDT 24
Peak memory 201572 kb
Host smart-17c0fcb9-36f7-488b-994e-9fb2782e5524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646772365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.2646772365
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1020947363
Short name T343
Test name
Test status
Simulation time 2532745558 ps
CPU time 2.21 seconds
Started Jul 11 04:54:23 PM PDT 24
Finished Jul 11 04:54:35 PM PDT 24
Peak memory 201640 kb
Host smart-b2d27d05-4cc1-4bb0-8216-f4335ceaebf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020947363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.1020947363
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.3825861493
Short name T537
Test name
Test status
Simulation time 2134734430 ps
CPU time 1.85 seconds
Started Jul 11 04:54:15 PM PDT 24
Finished Jul 11 04:54:25 PM PDT 24
Peak memory 201460 kb
Host smart-0a46602d-3b77-4ba1-80c0-25e7763e5f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825861493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.3825861493
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.344751360
Short name T773
Test name
Test status
Simulation time 4676023490 ps
CPU time 6.47 seconds
Started Jul 11 04:54:14 PM PDT 24
Finished Jul 11 04:54:29 PM PDT 24
Peak memory 201644 kb
Host smart-addc9c7b-4e09-47b6-add8-a8d42c386f93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344751360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_ultra_low_pwr.344751360
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.1243696031
Short name T354
Test name
Test status
Simulation time 2035614763 ps
CPU time 1.86 seconds
Started Jul 11 04:54:20 PM PDT 24
Finished Jul 11 04:54:30 PM PDT 24
Peak memory 201520 kb
Host smart-5a1df967-fd65-47b3-b19f-62b0b5eca8a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243696031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.1243696031
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3898657085
Short name T547
Test name
Test status
Simulation time 197087276892 ps
CPU time 132.93 seconds
Started Jul 11 04:54:15 PM PDT 24
Finished Jul 11 04:56:36 PM PDT 24
Peak memory 201724 kb
Host smart-cbfe0f4a-5c98-4f7a-ad7b-8b9d27983b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898657085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.3
898657085
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2784935618
Short name T611
Test name
Test status
Simulation time 141459170347 ps
CPU time 364.32 seconds
Started Jul 11 04:54:20 PM PDT 24
Finished Jul 11 05:00:33 PM PDT 24
Peak memory 201812 kb
Host smart-baef229f-0050-418d-9085-cc533af82855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784935618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.2784935618
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3982651540
Short name T619
Test name
Test status
Simulation time 54747678795 ps
CPU time 143.84 seconds
Started Jul 11 04:54:17 PM PDT 24
Finished Jul 11 04:56:50 PM PDT 24
Peak memory 201616 kb
Host smart-f0ca33c9-d154-4437-9641-3950d310cab2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982651540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.3982651540
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.3027235718
Short name T9
Test name
Test status
Simulation time 5021863066 ps
CPU time 13.99 seconds
Started Jul 11 04:54:23 PM PDT 24
Finished Jul 11 04:54:46 PM PDT 24
Peak memory 201520 kb
Host smart-3004b70e-281e-471b-a221-d2339a10448e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027235718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.3027235718
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.587861908
Short name T652
Test name
Test status
Simulation time 2613579596 ps
CPU time 7.04 seconds
Started Jul 11 04:54:17 PM PDT 24
Finished Jul 11 04:54:32 PM PDT 24
Peak memory 201532 kb
Host smart-b686d2a1-601e-470a-9ab6-79b55b5d4cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587861908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.587861908
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1680880730
Short name T165
Test name
Test status
Simulation time 2476290795 ps
CPU time 2.02 seconds
Started Jul 11 04:54:20 PM PDT 24
Finished Jul 11 04:54:31 PM PDT 24
Peak memory 201488 kb
Host smart-ffa8060b-c6a0-469d-84b7-29fe2f976813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680880730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.1680880730
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.1032501219
Short name T786
Test name
Test status
Simulation time 2074702548 ps
CPU time 5.83 seconds
Started Jul 11 04:54:18 PM PDT 24
Finished Jul 11 04:54:32 PM PDT 24
Peak memory 201532 kb
Host smart-38198715-9375-4fd2-ad55-c71832bbf681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032501219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.1032501219
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3896007363
Short name T320
Test name
Test status
Simulation time 2530354485 ps
CPU time 2.36 seconds
Started Jul 11 04:54:19 PM PDT 24
Finished Jul 11 04:54:30 PM PDT 24
Peak memory 201540 kb
Host smart-57cf2c10-15e9-4bb8-8556-7c1d992dbe1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896007363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.3896007363
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.2035383479
Short name T263
Test name
Test status
Simulation time 2119230506 ps
CPU time 3.39 seconds
Started Jul 11 04:54:23 PM PDT 24
Finished Jul 11 04:54:35 PM PDT 24
Peak memory 201500 kb
Host smart-b736c31f-1d87-4b72-b230-65df0e2e717f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035383479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.2035383479
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.2876674402
Short name T227
Test name
Test status
Simulation time 15676896298 ps
CPU time 21.78 seconds
Started Jul 11 04:54:24 PM PDT 24
Finished Jul 11 04:54:55 PM PDT 24
Peak memory 201812 kb
Host smart-9f9f0aca-9c28-4cf8-b8d9-63b86cd61734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876674402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.2876674402
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3759197323
Short name T79
Test name
Test status
Simulation time 38257447012 ps
CPU time 73.74 seconds
Started Jul 11 04:54:24 PM PDT 24
Finished Jul 11 04:55:47 PM PDT 24
Peak memory 218452 kb
Host smart-766a790d-9303-4343-8ba1-4edfd8601e4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759197323 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.3759197323
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3483530392
Short name T250
Test name
Test status
Simulation time 5588484744 ps
CPU time 4.04 seconds
Started Jul 11 04:54:16 PM PDT 24
Finished Jul 11 04:54:28 PM PDT 24
Peak memory 201876 kb
Host smart-f8129abe-c834-4a15-acfd-9766cc653d96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483530392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.3483530392
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.82339294
Short name T228
Test name
Test status
Simulation time 2012509602 ps
CPU time 5.7 seconds
Started Jul 11 04:54:25 PM PDT 24
Finished Jul 11 04:54:40 PM PDT 24
Peak memory 201608 kb
Host smart-0889536b-5645-41b9-a5a9-e055f154473e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82339294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_test
.82339294
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.4174474923
Short name T678
Test name
Test status
Simulation time 3232380685 ps
CPU time 8.81 seconds
Started Jul 11 04:54:24 PM PDT 24
Finished Jul 11 04:54:42 PM PDT 24
Peak memory 201728 kb
Host smart-e07fa499-eaad-400c-93a6-2affc7b432d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174474923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.4
174474923
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.2892278662
Short name T600
Test name
Test status
Simulation time 100395863810 ps
CPU time 272.93 seconds
Started Jul 11 04:54:23 PM PDT 24
Finished Jul 11 04:59:05 PM PDT 24
Peak memory 201732 kb
Host smart-14f8ec97-49d4-4217-9364-cf4dcc1c33ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892278662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.2892278662
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.4115527847
Short name T43
Test name
Test status
Simulation time 26082425694 ps
CPU time 72.99 seconds
Started Jul 11 04:54:19 PM PDT 24
Finished Jul 11 04:55:41 PM PDT 24
Peak memory 201900 kb
Host smart-2d4f594c-50fa-4e7f-8c35-9750894eb988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115527847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.4115527847
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3505883129
Short name T667
Test name
Test status
Simulation time 4131558461 ps
CPU time 10.7 seconds
Started Jul 11 04:54:25 PM PDT 24
Finished Jul 11 04:54:44 PM PDT 24
Peak memory 201592 kb
Host smart-33394b17-aa69-4d71-8aed-a109a3c934e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505883129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.3505883129
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.3819946322
Short name T116
Test name
Test status
Simulation time 5342769394 ps
CPU time 4.68 seconds
Started Jul 11 04:54:28 PM PDT 24
Finished Jul 11 04:54:42 PM PDT 24
Peak memory 201504 kb
Host smart-e84b0b82-330c-4839-b5ca-fcb4260e6c8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819946322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.3819946322
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3555490272
Short name T525
Test name
Test status
Simulation time 2613526081 ps
CPU time 7.36 seconds
Started Jul 11 04:54:26 PM PDT 24
Finished Jul 11 04:54:42 PM PDT 24
Peak memory 200960 kb
Host smart-4cb0fc0d-4961-4b2e-95ac-06f599c3e319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555490272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.3555490272
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3115554643
Short name T626
Test name
Test status
Simulation time 2498000708 ps
CPU time 2.19 seconds
Started Jul 11 04:54:23 PM PDT 24
Finished Jul 11 04:54:34 PM PDT 24
Peak memory 201632 kb
Host smart-a07d8632-e429-4eb2-a64a-e5fdf40e2e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115554643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.3115554643
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2110405344
Short name T321
Test name
Test status
Simulation time 2144184934 ps
CPU time 5.7 seconds
Started Jul 11 04:54:24 PM PDT 24
Finished Jul 11 04:54:39 PM PDT 24
Peak memory 201508 kb
Host smart-6e1ab485-800f-4eea-bb01-11c733410aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110405344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.2110405344
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.4162342751
Short name T164
Test name
Test status
Simulation time 2509273416 ps
CPU time 6.93 seconds
Started Jul 11 04:54:22 PM PDT 24
Finished Jul 11 04:54:37 PM PDT 24
Peak memory 201628 kb
Host smart-9fb1b867-6bdc-4a56-98bf-01df16f41712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162342751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.4162342751
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.2741013009
Short name T423
Test name
Test status
Simulation time 2110219341 ps
CPU time 6.24 seconds
Started Jul 11 04:54:20 PM PDT 24
Finished Jul 11 04:54:34 PM PDT 24
Peak memory 201492 kb
Host smart-40450d76-8ef7-4e76-b57c-d18493c1c05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741013009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.2741013009
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.1018399840
Short name T506
Test name
Test status
Simulation time 8755048381 ps
CPU time 7.26 seconds
Started Jul 11 04:54:21 PM PDT 24
Finished Jul 11 04:54:37 PM PDT 24
Peak memory 201640 kb
Host smart-68c9bdc6-6c60-48c1-8020-bdcbbf608412
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018399840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ultra_low_pwr.1018399840
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.3482115841
Short name T508
Test name
Test status
Simulation time 2051038108 ps
CPU time 1.46 seconds
Started Jul 11 04:54:23 PM PDT 24
Finished Jul 11 04:54:34 PM PDT 24
Peak memory 201500 kb
Host smart-29d6be78-355d-4c8d-b4e8-cb2ad04678db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482115841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.3482115841
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.841500042
Short name T694
Test name
Test status
Simulation time 3765530669 ps
CPU time 2.87 seconds
Started Jul 11 04:54:24 PM PDT 24
Finished Jul 11 04:54:36 PM PDT 24
Peak memory 201624 kb
Host smart-ca43ce9c-3ec4-46df-ab36-e1c71d168f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841500042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.841500042
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.2371675896
Short name T288
Test name
Test status
Simulation time 86263762841 ps
CPU time 213.41 seconds
Started Jul 11 04:54:22 PM PDT 24
Finished Jul 11 04:58:05 PM PDT 24
Peak memory 201808 kb
Host smart-09d39360-ea35-4019-811a-39260b54a458
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371675896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.2371675896
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.4256883358
Short name T348
Test name
Test status
Simulation time 49475309060 ps
CPU time 122.41 seconds
Started Jul 11 04:54:28 PM PDT 24
Finished Jul 11 04:56:39 PM PDT 24
Peak memory 201824 kb
Host smart-59424fef-4c2f-4693-a67f-22a76eede3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256883358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.4256883358
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2180926780
Short name T248
Test name
Test status
Simulation time 4277825819 ps
CPU time 11.27 seconds
Started Jul 11 04:54:23 PM PDT 24
Finished Jul 11 04:54:43 PM PDT 24
Peak memory 201532 kb
Host smart-aeba3df3-0b6a-4ba6-a22b-edd458457d63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180926780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ec_pwr_on_rst.2180926780
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.3138015131
Short name T700
Test name
Test status
Simulation time 2343604156 ps
CPU time 2.04 seconds
Started Jul 11 04:54:22 PM PDT 24
Finished Jul 11 04:54:33 PM PDT 24
Peak memory 201572 kb
Host smart-da1d4db6-8fa2-4c76-b6a5-08ebf8c8c5ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138015131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.3138015131
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1941362474
Short name T555
Test name
Test status
Simulation time 2614172997 ps
CPU time 4.31 seconds
Started Jul 11 04:54:23 PM PDT 24
Finished Jul 11 04:54:37 PM PDT 24
Peak memory 201640 kb
Host smart-f327a760-b226-48dc-ac3e-6e439f706281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941362474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.1941362474
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3750146512
Short name T514
Test name
Test status
Simulation time 2456229944 ps
CPU time 7.31 seconds
Started Jul 11 04:54:23 PM PDT 24
Finished Jul 11 04:54:39 PM PDT 24
Peak memory 201636 kb
Host smart-0657ab40-be8b-46b1-81ba-96fd61ce8ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750146512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.3750146512
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1423010459
Short name T593
Test name
Test status
Simulation time 2258048683 ps
CPU time 2.04 seconds
Started Jul 11 04:54:24 PM PDT 24
Finished Jul 11 04:54:35 PM PDT 24
Peak memory 201484 kb
Host smart-c1e480c3-b7a1-469a-9318-cc879cf72030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423010459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.1423010459
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.3082248119
Short name T201
Test name
Test status
Simulation time 2507418300 ps
CPU time 7.34 seconds
Started Jul 11 04:54:22 PM PDT 24
Finished Jul 11 04:54:38 PM PDT 24
Peak memory 201632 kb
Host smart-c21d9162-f46d-4d23-b6b9-753795b1cc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082248119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.3082248119
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.2276482730
Short name T634
Test name
Test status
Simulation time 2110879916 ps
CPU time 5.88 seconds
Started Jul 11 04:54:21 PM PDT 24
Finished Jul 11 04:54:36 PM PDT 24
Peak memory 201544 kb
Host smart-b8c3e05f-0613-40e1-b7e5-3665e6526887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276482730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.2276482730
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.1759428962
Short name T394
Test name
Test status
Simulation time 109985441910 ps
CPU time 260.92 seconds
Started Jul 11 04:54:21 PM PDT 24
Finished Jul 11 04:58:51 PM PDT 24
Peak memory 201900 kb
Host smart-e16192a6-12cf-4440-99e7-8a9f916ec79a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759428962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s
tress_all.1759428962
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2543403724
Short name T145
Test name
Test status
Simulation time 73005889545 ps
CPU time 41.57 seconds
Started Jul 11 04:54:23 PM PDT 24
Finished Jul 11 04:55:13 PM PDT 24
Peak memory 218320 kb
Host smart-25713baa-5e94-4d29-ad67-88da6d5fa545
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543403724 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.2543403724
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.2557377195
Short name T566
Test name
Test status
Simulation time 7297376357 ps
CPU time 7.71 seconds
Started Jul 11 04:54:23 PM PDT 24
Finished Jul 11 04:54:40 PM PDT 24
Peak memory 201508 kb
Host smart-855c07f9-c8ad-41e1-a446-3fed5dc36bb1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557377195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ultra_low_pwr.2557377195
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.1674540690
Short name T518
Test name
Test status
Simulation time 2021166229 ps
CPU time 2.38 seconds
Started Jul 11 04:54:27 PM PDT 24
Finished Jul 11 04:54:38 PM PDT 24
Peak memory 201544 kb
Host smart-b1cf0646-17f4-45ea-ac2a-5d3186ded96e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674540690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.1674540690
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3990878760
Short name T254
Test name
Test status
Simulation time 3948430961 ps
CPU time 3.13 seconds
Started Jul 11 04:54:29 PM PDT 24
Finished Jul 11 04:54:41 PM PDT 24
Peak memory 201660 kb
Host smart-475f548f-2bb8-433f-a9e0-a27fa6bcba6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990878760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.3
990878760
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.1584638174
Short name T736
Test name
Test status
Simulation time 143041333561 ps
CPU time 94.35 seconds
Started Jul 11 04:54:26 PM PDT 24
Finished Jul 11 04:56:10 PM PDT 24
Peak memory 201852 kb
Host smart-0fbeb7e7-52e8-486f-a431-20dd32c4fd6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584638174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.1584638174
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3781943982
Short name T485
Test name
Test status
Simulation time 2580347941 ps
CPU time 3.71 seconds
Started Jul 11 04:54:26 PM PDT 24
Finished Jul 11 04:54:38 PM PDT 24
Peak memory 201608 kb
Host smart-4adcefde-a6ee-4679-8bde-8c4b107e0ba3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781943982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.3781943982
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.646292672
Short name T176
Test name
Test status
Simulation time 4127851249 ps
CPU time 3.37 seconds
Started Jul 11 04:54:25 PM PDT 24
Finished Jul 11 04:54:37 PM PDT 24
Peak memory 201544 kb
Host smart-0dcb442e-fae8-4841-9b46-d9e156a7aeea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646292672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctr
l_edge_detect.646292672
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.563704266
Short name T188
Test name
Test status
Simulation time 2630677962 ps
CPU time 2.38 seconds
Started Jul 11 04:54:26 PM PDT 24
Finished Jul 11 04:54:37 PM PDT 24
Peak memory 201632 kb
Host smart-b4fedd65-af57-4e90-976f-36d521b5e168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563704266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.563704266
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2277013235
Short name T665
Test name
Test status
Simulation time 2489933010 ps
CPU time 2.48 seconds
Started Jul 11 04:54:22 PM PDT 24
Finished Jul 11 04:54:33 PM PDT 24
Peak memory 201624 kb
Host smart-2c30bfe9-b4f2-4c20-a296-d00f231aa125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277013235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.2277013235
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3040400682
Short name T450
Test name
Test status
Simulation time 2083986122 ps
CPU time 5.91 seconds
Started Jul 11 04:54:28 PM PDT 24
Finished Jul 11 04:54:43 PM PDT 24
Peak memory 201412 kb
Host smart-9fe58ded-be71-465a-9add-d2ca991b2d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040400682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.3040400682
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1475065720
Short name T459
Test name
Test status
Simulation time 2534459132 ps
CPU time 1.96 seconds
Started Jul 11 04:54:27 PM PDT 24
Finished Jul 11 04:54:38 PM PDT 24
Peak memory 201616 kb
Host smart-68c4b216-023a-4aee-bf13-56551584f7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475065720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.1475065720
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.2109112699
Short name T462
Test name
Test status
Simulation time 2112958390 ps
CPU time 5.45 seconds
Started Jul 11 04:54:28 PM PDT 24
Finished Jul 11 04:54:42 PM PDT 24
Peak memory 201568 kb
Host smart-57a312a8-e8bf-4964-9fb9-0ef1adcb6b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109112699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.2109112699
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.779978560
Short name T326
Test name
Test status
Simulation time 55953610286 ps
CPU time 27.94 seconds
Started Jul 11 04:54:32 PM PDT 24
Finished Jul 11 04:55:07 PM PDT 24
Peak memory 210160 kb
Host smart-a71ff180-4609-4108-97aa-df99bfb80eda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779978560 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.779978560
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1709402846
Short name T476
Test name
Test status
Simulation time 2520709980 ps
CPU time 1.06 seconds
Started Jul 11 04:54:27 PM PDT 24
Finished Jul 11 04:54:37 PM PDT 24
Peak memory 201620 kb
Host smart-a8f2645f-c966-4895-a819-d83a587cb41a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709402846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.1709402846
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.3572236084
Short name T177
Test name
Test status
Simulation time 2038167424 ps
CPU time 1.95 seconds
Started Jul 11 04:54:27 PM PDT 24
Finished Jul 11 04:54:37 PM PDT 24
Peak memory 201564 kb
Host smart-65df282b-4411-4a4c-be1a-6372de7f5096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572236084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.3572236084
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2045546001
Short name T194
Test name
Test status
Simulation time 3363098774 ps
CPU time 5.12 seconds
Started Jul 11 05:34:15 PM PDT 24
Finished Jul 11 05:34:33 PM PDT 24
Peak memory 201648 kb
Host smart-19558fe6-7973-49a3-9d16-1d4e87427f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045546001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.2
045546001
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.1701598447
Short name T661
Test name
Test status
Simulation time 114871568269 ps
CPU time 302.51 seconds
Started Jul 11 05:25:58 PM PDT 24
Finished Jul 11 05:31:05 PM PDT 24
Peak memory 201840 kb
Host smart-260213d1-65c8-4ef6-89d0-314e16599c11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701598447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_combo_detect.1701598447
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2437138208
Short name T101
Test name
Test status
Simulation time 25351775914 ps
CPU time 16.31 seconds
Started Jul 11 05:43:51 PM PDT 24
Finished Jul 11 05:44:09 PM PDT 24
Peak memory 201928 kb
Host smart-329f13d1-bf6f-4f4a-b526-5000578c7804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437138208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.2437138208
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3803355882
Short name T463
Test name
Test status
Simulation time 3624449592 ps
CPU time 10.28 seconds
Started Jul 11 05:12:24 PM PDT 24
Finished Jul 11 05:12:35 PM PDT 24
Peak memory 201504 kb
Host smart-c1ea2ca4-549d-4f22-a5c8-58e3374601c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803355882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.3803355882
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.1747775853
Short name T331
Test name
Test status
Simulation time 4014930563 ps
CPU time 1.69 seconds
Started Jul 11 05:20:58 PM PDT 24
Finished Jul 11 05:21:05 PM PDT 24
Peak memory 201536 kb
Host smart-946e1cd5-0468-4257-b67d-993253c14168
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747775853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.1747775853
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.286295231
Short name T439
Test name
Test status
Simulation time 2610236209 ps
CPU time 7.04 seconds
Started Jul 11 04:54:27 PM PDT 24
Finished Jul 11 04:54:43 PM PDT 24
Peak memory 201532 kb
Host smart-080f90ab-e6b4-4975-a2a3-624d4cf58aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286295231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.286295231
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.1467537963
Short name T529
Test name
Test status
Simulation time 2463034759 ps
CPU time 7.25 seconds
Started Jul 11 04:54:27 PM PDT 24
Finished Jul 11 04:54:43 PM PDT 24
Peak memory 201644 kb
Host smart-145ed09d-9470-4d8a-9089-56b1b8cbfed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467537963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.1467537963
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.4105842983
Short name T710
Test name
Test status
Simulation time 2262041400 ps
CPU time 6.19 seconds
Started Jul 11 04:54:26 PM PDT 24
Finished Jul 11 04:54:41 PM PDT 24
Peak memory 201604 kb
Host smart-99ad37ce-ae3b-4696-893c-4dd7eaab69a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105842983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.4105842983
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.2517115119
Short name T657
Test name
Test status
Simulation time 2509171467 ps
CPU time 7.28 seconds
Started Jul 11 04:54:27 PM PDT 24
Finished Jul 11 04:54:43 PM PDT 24
Peak memory 201532 kb
Host smart-c7d7d31c-3a8c-44a5-b8cb-603db460afca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517115119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.2517115119
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.3511668734
Short name T247
Test name
Test status
Simulation time 2195191005 ps
CPU time 0.97 seconds
Started Jul 11 04:54:27 PM PDT 24
Finished Jul 11 04:54:36 PM PDT 24
Peak memory 201580 kb
Host smart-912af1f1-07f5-4f94-9807-6ece7de0dd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511668734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.3511668734
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.1357973782
Short name T560
Test name
Test status
Simulation time 13227678291 ps
CPU time 6.67 seconds
Started Jul 11 05:47:21 PM PDT 24
Finished Jul 11 05:47:31 PM PDT 24
Peak memory 201692 kb
Host smart-d71bbcb6-2e89-4430-add1-0df4fa648e4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357973782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.1357973782
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2660067817
Short name T206
Test name
Test status
Simulation time 59667695999 ps
CPU time 111.85 seconds
Started Jul 11 05:15:47 PM PDT 24
Finished Jul 11 05:17:40 PM PDT 24
Peak memory 210208 kb
Host smart-96c2fa18-51d8-4d83-b36a-e318eb6ccaf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660067817 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.2660067817
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2066713767
Short name T143
Test name
Test status
Simulation time 6740674585 ps
CPU time 2.39 seconds
Started Jul 11 05:30:36 PM PDT 24
Finished Jul 11 05:30:40 PM PDT 24
Peak memory 201584 kb
Host smart-f5edd2a8-068d-4fd0-a5e3-d61b70e7fd7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066713767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.2066713767
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.1877089129
Short name T683
Test name
Test status
Simulation time 2029454068 ps
CPU time 1.99 seconds
Started Jul 11 04:54:31 PM PDT 24
Finished Jul 11 04:54:41 PM PDT 24
Peak memory 201524 kb
Host smart-24151b1d-8798-4def-8112-6e5e0655e561
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877089129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.1877089129
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.3591454726
Short name T607
Test name
Test status
Simulation time 3724515144 ps
CPU time 2.8 seconds
Started Jul 11 04:54:27 PM PDT 24
Finished Jul 11 04:54:39 PM PDT 24
Peak memory 201628 kb
Host smart-b488bc0f-006f-4c4c-a58d-18c332c53f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591454726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.3
591454726
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.2282611766
Short name T376
Test name
Test status
Simulation time 165284028192 ps
CPU time 106.82 seconds
Started Jul 11 04:58:22 PM PDT 24
Finished Jul 11 05:00:21 PM PDT 24
Peak memory 201724 kb
Host smart-4bec8ce3-8356-4dac-8bd2-ea61266f2a5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282611766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_combo_detect.2282611766
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3467464326
Short name T174
Test name
Test status
Simulation time 109966211273 ps
CPU time 75.17 seconds
Started Jul 11 04:54:26 PM PDT 24
Finished Jul 11 04:55:50 PM PDT 24
Peak memory 201836 kb
Host smart-656c24a0-99f9-4f0e-b1ff-42ec914aeefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467464326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.3467464326
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1969870311
Short name T460
Test name
Test status
Simulation time 2873523008 ps
CPU time 7.58 seconds
Started Jul 11 04:54:26 PM PDT 24
Finished Jul 11 04:54:43 PM PDT 24
Peak memory 201532 kb
Host smart-96579af3-de19-41ca-9e16-2604a4681a94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969870311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.1969870311
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.3891691199
Short name T249
Test name
Test status
Simulation time 3051650115 ps
CPU time 7.67 seconds
Started Jul 11 04:54:35 PM PDT 24
Finished Jul 11 04:54:50 PM PDT 24
Peak memory 201612 kb
Host smart-121dfa8b-30e7-4b9a-94f3-16929482f866
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891691199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.3891691199
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.33189460
Short name T519
Test name
Test status
Simulation time 2610405866 ps
CPU time 7.02 seconds
Started Jul 11 04:54:26 PM PDT 24
Finished Jul 11 04:54:42 PM PDT 24
Peak memory 201044 kb
Host smart-b135d733-59be-4a50-8739-25ebf9007f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33189460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.33189460
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.781480116
Short name T334
Test name
Test status
Simulation time 2449675784 ps
CPU time 2.29 seconds
Started Jul 11 04:54:27 PM PDT 24
Finished Jul 11 04:54:39 PM PDT 24
Peak memory 201612 kb
Host smart-28d9538c-59fa-4b15-8a09-a59f97c617cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781480116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.781480116
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1152791070
Short name T776
Test name
Test status
Simulation time 2121806446 ps
CPU time 5.64 seconds
Started Jul 11 05:12:21 PM PDT 24
Finished Jul 11 05:12:28 PM PDT 24
Peak memory 201568 kb
Host smart-b5294b80-2a5c-4a7f-8bcf-425752ebc488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152791070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.1152791070
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.244078810
Short name T436
Test name
Test status
Simulation time 2535016708 ps
CPU time 2 seconds
Started Jul 11 04:59:01 PM PDT 24
Finished Jul 11 04:59:05 PM PDT 24
Peak memory 201628 kb
Host smart-100b546e-49d6-46f4-9a83-f9ed70f10921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244078810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.244078810
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.2828813411
Short name T554
Test name
Test status
Simulation time 2122600333 ps
CPU time 2.04 seconds
Started Jul 11 05:24:25 PM PDT 24
Finished Jul 11 05:24:29 PM PDT 24
Peak memory 201516 kb
Host smart-a125f077-3f5f-4cf5-b0e6-58331802d91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828813411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.2828813411
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.630223747
Short name T408
Test name
Test status
Simulation time 488205207813 ps
CPU time 56.8 seconds
Started Jul 11 04:54:25 PM PDT 24
Finished Jul 11 04:55:31 PM PDT 24
Peak memory 201564 kb
Host smart-ef668650-5438-4883-84fa-57eddccad6a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630223747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_st
ress_all.630223747
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3513076670
Short name T127
Test name
Test status
Simulation time 6962967594 ps
CPU time 2.18 seconds
Started Jul 11 04:56:17 PM PDT 24
Finished Jul 11 04:56:31 PM PDT 24
Peak memory 201492 kb
Host smart-e8ef6211-9345-4a8b-bba8-dcc8ed9000ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513076670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.3513076670
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.1331778878
Short name T489
Test name
Test status
Simulation time 2029210885 ps
CPU time 1.8 seconds
Started Jul 11 04:52:59 PM PDT 24
Finished Jul 11 04:53:06 PM PDT 24
Peak memory 201636 kb
Host smart-5d201b99-d2ba-4c63-8d9a-209b6dda7ec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331778878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.1331778878
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.375578468
Short name T204
Test name
Test status
Simulation time 3158097549 ps
CPU time 8.59 seconds
Started Jul 11 04:52:59 PM PDT 24
Finished Jul 11 04:53:13 PM PDT 24
Peak memory 201652 kb
Host smart-cb0de226-89be-4acb-9b0b-61eb4883455a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375578468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.375578468
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.2895275671
Short name T279
Test name
Test status
Simulation time 135666377787 ps
CPU time 340.5 seconds
Started Jul 11 04:52:59 PM PDT 24
Finished Jul 11 04:58:45 PM PDT 24
Peak memory 201872 kb
Host smart-bbe526ed-8532-49a6-bfe2-83c1e1411b3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895275671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.2895275671
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.4021722968
Short name T390
Test name
Test status
Simulation time 58203349999 ps
CPU time 39.35 seconds
Started Jul 11 04:52:59 PM PDT 24
Finished Jul 11 04:53:44 PM PDT 24
Peak memory 201924 kb
Host smart-c6d34509-bcb5-4fee-b31d-c9c4cbc6bf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021722968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.4021722968
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3646521961
Short name T504
Test name
Test status
Simulation time 3563555261 ps
CPU time 4.35 seconds
Started Jul 11 04:52:54 PM PDT 24
Finished Jul 11 04:53:04 PM PDT 24
Peak memory 201540 kb
Host smart-09d01e9b-6b75-48e9-ad91-f82890e78ba6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646521961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.3646521961
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.829851399
Short name T112
Test name
Test status
Simulation time 3507681436 ps
CPU time 2.66 seconds
Started Jul 11 04:52:56 PM PDT 24
Finished Jul 11 04:53:05 PM PDT 24
Peak memory 201576 kb
Host smart-31033559-e0ff-475f-bc5b-87b1ff280d37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829851399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl
_edge_detect.829851399
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3103085311
Short name T693
Test name
Test status
Simulation time 2613186510 ps
CPU time 7.13 seconds
Started Jul 11 04:52:54 PM PDT 24
Finished Jul 11 04:53:08 PM PDT 24
Peak memory 201624 kb
Host smart-0a877c18-d87f-42c1-a72c-340ba778128d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103085311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.3103085311
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.2297146582
Short name T438
Test name
Test status
Simulation time 2464283185 ps
CPU time 7.49 seconds
Started Jul 11 04:52:52 PM PDT 24
Finished Jul 11 04:53:06 PM PDT 24
Peak memory 201528 kb
Host smart-44bd5231-274f-4ad3-b798-66348837086c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297146582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.2297146582
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.922249160
Short name T196
Test name
Test status
Simulation time 2225160481 ps
CPU time 6.69 seconds
Started Jul 11 04:52:51 PM PDT 24
Finished Jul 11 04:53:04 PM PDT 24
Peak memory 201640 kb
Host smart-934e7e5f-b554-43fd-8d67-0dff2615ae56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922249160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.922249160
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3109404011
Short name T444
Test name
Test status
Simulation time 2532502592 ps
CPU time 2.48 seconds
Started Jul 11 04:52:52 PM PDT 24
Finished Jul 11 04:53:01 PM PDT 24
Peak memory 201540 kb
Host smart-0e0d33a8-c43c-4a95-a44b-be36fe35a7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109404011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.3109404011
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.2648202929
Short name T15
Test name
Test status
Simulation time 2136816193 ps
CPU time 1.87 seconds
Started Jul 11 04:52:52 PM PDT 24
Finished Jul 11 04:53:01 PM PDT 24
Peak memory 201464 kb
Host smart-c3c3d2f7-d47a-47fa-aaca-5f5437f06cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648202929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.2648202929
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.2332576669
Short name T323
Test name
Test status
Simulation time 6266441588 ps
CPU time 4.54 seconds
Started Jul 11 04:52:58 PM PDT 24
Finished Jul 11 04:53:07 PM PDT 24
Peak memory 201588 kb
Host smart-a01ae5bd-8b64-4b49-b14f-103234b29c3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332576669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.2332576669
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1618402692
Short name T168
Test name
Test status
Simulation time 39670926248 ps
CPU time 21.86 seconds
Started Jul 11 04:52:57 PM PDT 24
Finished Jul 11 04:53:25 PM PDT 24
Peak memory 210212 kb
Host smart-2447df82-add8-4ae3-a3e4-dd71e92cc5d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618402692 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.1618402692
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3163880738
Short name T703
Test name
Test status
Simulation time 22590022764 ps
CPU time 30.5 seconds
Started Jul 11 04:54:31 PM PDT 24
Finished Jul 11 04:55:10 PM PDT 24
Peak memory 201928 kb
Host smart-933da72e-5ced-4a0d-9886-d57b4f3db7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163880738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.3163880738
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1187587659
Short name T512
Test name
Test status
Simulation time 63755883015 ps
CPU time 165.24 seconds
Started Jul 11 04:54:32 PM PDT 24
Finished Jul 11 04:57:25 PM PDT 24
Peak memory 201848 kb
Host smart-99ccd768-c62f-4d1a-8f2f-1f05f7dabe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187587659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.1187587659
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.447198893
Short name T557
Test name
Test status
Simulation time 71616062719 ps
CPU time 40.29 seconds
Started Jul 11 04:54:34 PM PDT 24
Finished Jul 11 04:55:22 PM PDT 24
Peak memory 201808 kb
Host smart-4e9c681f-2823-4041-bf0c-33c6c4bdb468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447198893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_wi
th_pre_cond.447198893
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.724462077
Short name T697
Test name
Test status
Simulation time 25084181044 ps
CPU time 32.01 seconds
Started Jul 11 04:54:36 PM PDT 24
Finished Jul 11 04:55:15 PM PDT 24
Peak memory 201896 kb
Host smart-be49793d-126c-44e7-b473-e470e8367d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724462077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_wi
th_pre_cond.724462077
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.914412755
Short name T758
Test name
Test status
Simulation time 78026958258 ps
CPU time 36.47 seconds
Started Jul 11 04:54:33 PM PDT 24
Finished Jul 11 04:55:17 PM PDT 24
Peak memory 201864 kb
Host smart-65a4f67b-2d55-4880-9a1d-27753f55aab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914412755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_wi
th_pre_cond.914412755
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2686267760
Short name T477
Test name
Test status
Simulation time 28607685708 ps
CPU time 12.8 seconds
Started Jul 11 04:54:33 PM PDT 24
Finished Jul 11 04:54:54 PM PDT 24
Peak memory 201888 kb
Host smart-0500b380-7635-450c-bcf2-351c59480918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686267760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w
ith_pre_cond.2686267760
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3168584699
Short name T401
Test name
Test status
Simulation time 130849391361 ps
CPU time 83.97 seconds
Started Jul 11 04:54:36 PM PDT 24
Finished Jul 11 04:56:07 PM PDT 24
Peak memory 201924 kb
Host smart-51660459-8643-4985-aa68-2312945438bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168584699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.3168584699
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2325563857
Short name T236
Test name
Test status
Simulation time 41552368490 ps
CPU time 7.8 seconds
Started Jul 11 04:54:35 PM PDT 24
Finished Jul 11 04:54:50 PM PDT 24
Peak memory 201904 kb
Host smart-cff79797-b640-4ea8-8d26-87c873af7f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325563857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_w
ith_pre_cond.2325563857
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.3280499279
Short name T81
Test name
Test status
Simulation time 2014638292 ps
CPU time 4.06 seconds
Started Jul 11 04:53:01 PM PDT 24
Finished Jul 11 04:53:10 PM PDT 24
Peak memory 201520 kb
Host smart-0141aee7-c9e3-4376-9972-793afb3290b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280499279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes
t.3280499279
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1330075923
Short name T659
Test name
Test status
Simulation time 3372789574 ps
CPU time 8.06 seconds
Started Jul 11 04:52:57 PM PDT 24
Finished Jul 11 04:53:10 PM PDT 24
Peak memory 201708 kb
Host smart-8ae97d72-fbf3-46c3-93b1-34700fbc23cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330075923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.1330075923
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.3130892710
Short name T253
Test name
Test status
Simulation time 147356982405 ps
CPU time 239.73 seconds
Started Jul 11 04:52:58 PM PDT 24
Finished Jul 11 04:57:04 PM PDT 24
Peak memory 201908 kb
Host smart-cfdf5228-155b-4fc6-b3ee-bb8a92f3b28b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130892710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.3130892710
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3299707291
Short name T680
Test name
Test status
Simulation time 63398665113 ps
CPU time 170.93 seconds
Started Jul 11 04:53:01 PM PDT 24
Finished Jul 11 04:55:57 PM PDT 24
Peak memory 201768 kb
Host smart-f4670071-2988-43eb-bc56-779fa8dc71e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299707291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wi
th_pre_cond.3299707291
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3817967122
Short name T565
Test name
Test status
Simulation time 3224202036 ps
CPU time 8.33 seconds
Started Jul 11 04:52:58 PM PDT 24
Finished Jul 11 04:53:12 PM PDT 24
Peak memory 201596 kb
Host smart-c1b9bce9-e9d0-45a3-b91b-65e1f8296b48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817967122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.3817967122
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.144050135
Short name T169
Test name
Test status
Simulation time 4375817914 ps
CPU time 9.72 seconds
Started Jul 11 04:52:59 PM PDT 24
Finished Jul 11 04:53:14 PM PDT 24
Peak memory 201616 kb
Host smart-de5b2e7e-9450-4493-b428-5d729030d4a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144050135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl
_edge_detect.144050135
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3605613117
Short name T564
Test name
Test status
Simulation time 2632044235 ps
CPU time 2.34 seconds
Started Jul 11 04:53:00 PM PDT 24
Finished Jul 11 04:53:07 PM PDT 24
Peak memory 201508 kb
Host smart-48a6ea70-be9b-4816-84d5-e0f19f603037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605613117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.3605613117
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.608467725
Short name T16
Test name
Test status
Simulation time 2524948823 ps
CPU time 1.9 seconds
Started Jul 11 04:52:58 PM PDT 24
Finished Jul 11 04:53:05 PM PDT 24
Peak memory 201588 kb
Host smart-9f5da7e0-dfa0-4c3a-9831-465d4de61835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608467725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.608467725
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.72458359
Short name T785
Test name
Test status
Simulation time 2121668882 ps
CPU time 5.37 seconds
Started Jul 11 04:53:09 PM PDT 24
Finished Jul 11 04:53:20 PM PDT 24
Peak memory 201476 kb
Host smart-2fa5b44d-13f0-4ce4-8d50-0921d234eadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72458359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.72458359
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3433590305
Short name T540
Test name
Test status
Simulation time 2520358979 ps
CPU time 3.99 seconds
Started Jul 11 04:52:57 PM PDT 24
Finished Jul 11 04:53:07 PM PDT 24
Peak memory 201540 kb
Host smart-575d0649-26ec-47f9-9704-ae8f637fc8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433590305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.3433590305
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.3476761420
Short name T645
Test name
Test status
Simulation time 2123479418 ps
CPU time 3 seconds
Started Jul 11 04:52:58 PM PDT 24
Finished Jul 11 04:53:07 PM PDT 24
Peak memory 201476 kb
Host smart-f63b8912-ea5c-44d3-8794-51cfc5b1899e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476761420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.3476761420
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.4262280278
Short name T353
Test name
Test status
Simulation time 24633041981 ps
CPU time 63.97 seconds
Started Jul 11 04:52:58 PM PDT 24
Finished Jul 11 04:54:07 PM PDT 24
Peak memory 210196 kb
Host smart-1ba68106-3c08-42c4-8806-cae583ecbc11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262280278 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.4262280278
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2225226409
Short name T338
Test name
Test status
Simulation time 4797997773 ps
CPU time 3.57 seconds
Started Jul 11 04:52:59 PM PDT 24
Finished Jul 11 04:53:08 PM PDT 24
Peak memory 201644 kb
Host smart-162e431a-2ebf-4c1f-bb7a-d7cccadbf59c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225226409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ultra_low_pwr.2225226409
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.2330987802
Short name T627
Test name
Test status
Simulation time 65787994842 ps
CPU time 41.88 seconds
Started Jul 11 04:54:32 PM PDT 24
Finished Jul 11 04:55:22 PM PDT 24
Peak memory 202156 kb
Host smart-77e945d4-520c-453a-98f5-6dfbb30f4e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330987802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_w
ith_pre_cond.2330987802
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.6181694
Short name T90
Test name
Test status
Simulation time 53972558827 ps
CPU time 134.33 seconds
Started Jul 11 04:54:38 PM PDT 24
Finished Jul 11 04:56:59 PM PDT 24
Peak memory 201904 kb
Host smart-3baa74db-edd1-42d4-848a-49accaef3bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6181694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_with
_pre_cond.6181694
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3962440592
Short name T98
Test name
Test status
Simulation time 77175061177 ps
CPU time 191.8 seconds
Started Jul 11 04:54:30 PM PDT 24
Finished Jul 11 04:57:50 PM PDT 24
Peak memory 201756 kb
Host smart-be531722-e966-47d0-82b6-a01f4a582f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962440592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.3962440592
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2557333125
Short name T75
Test name
Test status
Simulation time 55916106353 ps
CPU time 72.78 seconds
Started Jul 11 04:54:31 PM PDT 24
Finished Jul 11 04:55:52 PM PDT 24
Peak memory 201816 kb
Host smart-d0739405-6cf1-4a66-a296-d0f0d54b2bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557333125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.2557333125
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3568376994
Short name T402
Test name
Test status
Simulation time 229006629929 ps
CPU time 154.24 seconds
Started Jul 11 04:54:32 PM PDT 24
Finished Jul 11 04:57:14 PM PDT 24
Peak memory 201892 kb
Host smart-bfcd5a99-e1ef-494b-b3e4-ed1f6aec3475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568376994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.3568376994
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.2225047849
Short name T752
Test name
Test status
Simulation time 22333146488 ps
CPU time 55.91 seconds
Started Jul 11 04:54:33 PM PDT 24
Finished Jul 11 04:55:37 PM PDT 24
Peak memory 201888 kb
Host smart-9087aee3-32d9-483e-a2eb-b8d0c5d03eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225047849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_w
ith_pre_cond.2225047849
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.735843743
Short name T681
Test name
Test status
Simulation time 82576940068 ps
CPU time 206.02 seconds
Started Jul 11 04:54:33 PM PDT 24
Finished Jul 11 04:58:07 PM PDT 24
Peak memory 201868 kb
Host smart-30b8a8bf-0ca8-4357-bb13-21eedb0e1ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735843743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_wi
th_pre_cond.735843743
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2252844849
Short name T696
Test name
Test status
Simulation time 106259494972 ps
CPU time 286.64 seconds
Started Jul 11 04:54:34 PM PDT 24
Finished Jul 11 04:59:28 PM PDT 24
Peak memory 201912 kb
Host smart-560eadbd-9fc1-4ff8-9621-222b5d6fdc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252844849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.2252844849
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.436637030
Short name T382
Test name
Test status
Simulation time 70281568869 ps
CPU time 132.01 seconds
Started Jul 11 04:54:38 PM PDT 24
Finished Jul 11 04:56:56 PM PDT 24
Peak memory 201904 kb
Host smart-5c0a4d65-72b7-4ce5-8786-18aaabadc43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436637030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_wi
th_pre_cond.436637030
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.3546760085
Short name T435
Test name
Test status
Simulation time 2024190177 ps
CPU time 2 seconds
Started Jul 11 04:52:58 PM PDT 24
Finished Jul 11 04:53:05 PM PDT 24
Peak memory 201528 kb
Host smart-6bba732f-d1ee-4981-a140-cc56bbd13828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546760085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.3546760085
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.19590535
Short name T27
Test name
Test status
Simulation time 3337471876 ps
CPU time 5.11 seconds
Started Jul 11 04:53:08 PM PDT 24
Finished Jul 11 04:53:19 PM PDT 24
Peak memory 201596 kb
Host smart-6face36b-d8bd-4f62-b290-7940fec6cee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19590535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.19590535
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.560875709
Short name T104
Test name
Test status
Simulation time 24953983894 ps
CPU time 11.6 seconds
Started Jul 11 04:52:58 PM PDT 24
Finished Jul 11 04:53:15 PM PDT 24
Peak memory 201824 kb
Host smart-1d8097b3-b1cd-4e9e-9955-7b2f3aa5f43a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560875709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_combo_detect.560875709
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2242604701
Short name T12
Test name
Test status
Simulation time 35560510940 ps
CPU time 6.95 seconds
Started Jul 11 04:53:01 PM PDT 24
Finished Jul 11 04:53:12 PM PDT 24
Peak memory 201820 kb
Host smart-b7996247-4701-424a-a714-89319e1fcb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242604701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wi
th_pre_cond.2242604701
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1952178387
Short name T449
Test name
Test status
Simulation time 3272420444 ps
CPU time 2.87 seconds
Started Jul 11 04:52:58 PM PDT 24
Finished Jul 11 04:53:06 PM PDT 24
Peak memory 201508 kb
Host smart-c1b905fd-55a0-40bf-b178-13094e346e4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952178387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ec_pwr_on_rst.1952178387
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.2645878189
Short name T229
Test name
Test status
Simulation time 3036065839 ps
CPU time 2.24 seconds
Started Jul 11 04:52:56 PM PDT 24
Finished Jul 11 04:53:04 PM PDT 24
Peak memory 201516 kb
Host smart-26da1b68-288c-4c4f-a32b-27493f5d23fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645878189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.2645878189
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1563660193
Short name T497
Test name
Test status
Simulation time 2642529812 ps
CPU time 2.16 seconds
Started Jul 11 04:52:56 PM PDT 24
Finished Jul 11 04:53:04 PM PDT 24
Peak memory 201596 kb
Host smart-97ba70fa-ac91-4bb8-a26e-8d4fab6a751c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563660193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.1563660193
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.1211196086
Short name T672
Test name
Test status
Simulation time 2458389377 ps
CPU time 8.16 seconds
Started Jul 11 04:52:56 PM PDT 24
Finished Jul 11 04:53:10 PM PDT 24
Peak memory 201636 kb
Host smart-c9ce95c3-2e5e-47b2-87ac-5fc1102c6ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211196086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.1211196086
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2220717515
Short name T474
Test name
Test status
Simulation time 2167939775 ps
CPU time 2 seconds
Started Jul 11 04:52:57 PM PDT 24
Finished Jul 11 04:53:05 PM PDT 24
Peak memory 201536 kb
Host smart-7385a500-2318-4415-9327-e4f57736eb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220717515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.2220717515
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.1439361000
Short name T628
Test name
Test status
Simulation time 2538132082 ps
CPU time 2.31 seconds
Started Jul 11 04:52:59 PM PDT 24
Finished Jul 11 04:53:07 PM PDT 24
Peak memory 201556 kb
Host smart-9aaedb9e-8294-48f8-971a-68c29383abf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439361000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.1439361000
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.2690789193
Short name T493
Test name
Test status
Simulation time 2129405607 ps
CPU time 2 seconds
Started Jul 11 04:53:04 PM PDT 24
Finished Jul 11 04:53:11 PM PDT 24
Peak memory 201500 kb
Host smart-5d7138f5-5869-46e6-b7c7-8702238134ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690789193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.2690789193
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.1583664119
Short name T210
Test name
Test status
Simulation time 205839181622 ps
CPU time 125.35 seconds
Started Jul 11 04:53:02 PM PDT 24
Finished Jul 11 04:55:12 PM PDT 24
Peak memory 201840 kb
Host smart-4eb34f36-2a96-48e5-b4d2-a516f4047ce3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583664119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.1583664119
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2166009310
Short name T108
Test name
Test status
Simulation time 71603955763 ps
CPU time 188.44 seconds
Started Jul 11 04:52:58 PM PDT 24
Finished Jul 11 04:56:12 PM PDT 24
Peak memory 210452 kb
Host smart-99d365b3-df54-458e-9510-abf93d800bcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166009310 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.2166009310
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3846467566
Short name T138
Test name
Test status
Simulation time 12000103579 ps
CPU time 8.38 seconds
Started Jul 11 04:52:58 PM PDT 24
Finished Jul 11 04:53:12 PM PDT 24
Peak memory 201596 kb
Host smart-82eb33e2-6ac4-4df0-ab2a-f2ccc1ab3b2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846467566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ultra_low_pwr.3846467566
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2168300349
Short name T260
Test name
Test status
Simulation time 52151990972 ps
CPU time 11.68 seconds
Started Jul 11 04:54:30 PM PDT 24
Finished Jul 11 04:54:50 PM PDT 24
Peak memory 201880 kb
Host smart-31aa13ad-00ac-4e06-9532-4e44c9a99b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168300349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.2168300349
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1006984765
Short name T718
Test name
Test status
Simulation time 25107224409 ps
CPU time 15.58 seconds
Started Jul 11 04:54:30 PM PDT 24
Finished Jul 11 04:54:54 PM PDT 24
Peak memory 201828 kb
Host smart-2f681bf3-8908-443b-94ea-aa96023cfe44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006984765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.1006984765
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.382641458
Short name T688
Test name
Test status
Simulation time 113189093863 ps
CPU time 49.91 seconds
Started Jul 11 04:54:33 PM PDT 24
Finished Jul 11 04:55:31 PM PDT 24
Peak memory 201888 kb
Host smart-a5dd212d-d8dc-4285-aee2-926cc9b23ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382641458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_wi
th_pre_cond.382641458
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1364432820
Short name T702
Test name
Test status
Simulation time 30352978623 ps
CPU time 19.28 seconds
Started Jul 11 04:54:31 PM PDT 24
Finished Jul 11 04:54:59 PM PDT 24
Peak memory 201900 kb
Host smart-109e7b86-7860-4d93-bc63-2a3a8d3717ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364432820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.1364432820
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3289531917
Short name T41
Test name
Test status
Simulation time 76675436786 ps
CPU time 51.79 seconds
Started Jul 11 04:54:33 PM PDT 24
Finished Jul 11 04:55:33 PM PDT 24
Peak memory 201828 kb
Host smart-fb5398e3-73d0-4db0-a81e-19070dc5cc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289531917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.3289531917
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.3142333801
Short name T88
Test name
Test status
Simulation time 79473272113 ps
CPU time 54.17 seconds
Started Jul 11 04:54:36 PM PDT 24
Finished Jul 11 04:55:37 PM PDT 24
Peak memory 201872 kb
Host smart-cd067176-411a-4e36-a0d5-b766c09e9839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142333801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.3142333801
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1218986006
Short name T673
Test name
Test status
Simulation time 140449362006 ps
CPU time 32.87 seconds
Started Jul 11 04:54:38 PM PDT 24
Finished Jul 11 04:55:17 PM PDT 24
Peak memory 201908 kb
Host smart-07c1c5e6-ed78-4147-91c5-c36a39a1c05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218986006 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_w
ith_pre_cond.1218986006
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.890589843
Short name T282
Test name
Test status
Simulation time 50983422130 ps
CPU time 64.36 seconds
Started Jul 11 04:54:30 PM PDT 24
Finished Jul 11 04:55:43 PM PDT 24
Peak memory 201816 kb
Host smart-c120bf39-7158-417c-a083-912cea22b439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890589843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_wi
th_pre_cond.890589843
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.1346954068
Short name T200
Test name
Test status
Simulation time 2017683651 ps
CPU time 2.63 seconds
Started Jul 11 04:53:07 PM PDT 24
Finished Jul 11 04:53:16 PM PDT 24
Peak memory 201628 kb
Host smart-fc84e29c-bf9a-48de-875d-fcd8c321f891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346954068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.1346954068
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1357250518
Short name T111
Test name
Test status
Simulation time 3268668942 ps
CPU time 3.5 seconds
Started Jul 11 04:53:10 PM PDT 24
Finished Jul 11 04:53:21 PM PDT 24
Peak memory 201620 kb
Host smart-ac74a2f7-24ec-4fa6-ba9d-21fb9af0d376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357250518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.1357250518
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.1738176676
Short name T276
Test name
Test status
Simulation time 155370342179 ps
CPU time 412.02 seconds
Started Jul 11 04:53:08 PM PDT 24
Finished Jul 11 05:00:06 PM PDT 24
Peak memory 201712 kb
Host smart-2aeb3fd4-a445-4669-8fd6-7614e6e8a9ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738176676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.1738176676
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2707448099
Short name T582
Test name
Test status
Simulation time 2924442817 ps
CPU time 4.54 seconds
Started Jul 11 04:53:10 PM PDT 24
Finished Jul 11 04:53:21 PM PDT 24
Peak memory 201484 kb
Host smart-3726f402-3cbf-4b85-82f3-10820c192e6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707448099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.2707448099
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.2932534975
Short name T216
Test name
Test status
Simulation time 3973315882 ps
CPU time 9.52 seconds
Started Jul 11 04:53:06 PM PDT 24
Finished Jul 11 04:53:20 PM PDT 24
Peak memory 201612 kb
Host smart-7a8279fd-a654-4dc9-bd8e-b2da9e1a5224
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932534975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.2932534975
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1940191984
Short name T744
Test name
Test status
Simulation time 2629522922 ps
CPU time 2.44 seconds
Started Jul 11 04:53:03 PM PDT 24
Finished Jul 11 04:53:11 PM PDT 24
Peak memory 201636 kb
Host smart-af32a715-5fcd-4b1e-9e36-6e6d02691e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940191984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.1940191984
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2969922607
Short name T25
Test name
Test status
Simulation time 2471712557 ps
CPU time 2.2 seconds
Started Jul 11 04:53:10 PM PDT 24
Finished Jul 11 04:53:19 PM PDT 24
Peak memory 201512 kb
Host smart-262461ad-f258-440b-95cf-b18888dae523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969922607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.2969922607
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.768769377
Short name T734
Test name
Test status
Simulation time 2064353326 ps
CPU time 1.62 seconds
Started Jul 11 04:53:07 PM PDT 24
Finished Jul 11 04:53:15 PM PDT 24
Peak memory 201416 kb
Host smart-211aea96-8280-46b0-968a-c2671a14ea1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768769377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.768769377
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2047006340
Short name T684
Test name
Test status
Simulation time 2544182210 ps
CPU time 1.52 seconds
Started Jul 11 04:53:04 PM PDT 24
Finished Jul 11 04:53:10 PM PDT 24
Peak memory 201616 kb
Host smart-087cbd59-683e-4113-a9d0-6689034b07d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047006340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.2047006340
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.893871929
Short name T561
Test name
Test status
Simulation time 2127948084 ps
CPU time 2.04 seconds
Started Jul 11 04:53:06 PM PDT 24
Finished Jul 11 04:53:14 PM PDT 24
Peak memory 201812 kb
Host smart-c696641d-5992-4d0d-8e82-534429360203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893871929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.893871929
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.1530033141
Short name T486
Test name
Test status
Simulation time 9549317140 ps
CPU time 3.23 seconds
Started Jul 11 04:53:01 PM PDT 24
Finished Jul 11 04:53:09 PM PDT 24
Peak memory 201504 kb
Host smart-48e68922-290d-4795-9c8e-77449756db5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530033141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.1530033141
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3099196334
Short name T124
Test name
Test status
Simulation time 69349532679 ps
CPU time 87.81 seconds
Started Jul 11 04:53:03 PM PDT 24
Finished Jul 11 04:54:36 PM PDT 24
Peak memory 218300 kb
Host smart-a3de9525-60fe-4dee-bfd1-18c14b748afa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099196334 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.3099196334
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3910519886
Short name T137
Test name
Test status
Simulation time 4527042457 ps
CPU time 2.24 seconds
Started Jul 11 04:53:04 PM PDT 24
Finished Jul 11 04:53:11 PM PDT 24
Peak memory 201596 kb
Host smart-8b8d5fb3-429d-4ff7-84f3-34f7bce73905
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910519886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.3910519886
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2635794441
Short name T503
Test name
Test status
Simulation time 43576636052 ps
CPU time 24.86 seconds
Started Jul 11 04:54:39 PM PDT 24
Finished Jul 11 04:55:10 PM PDT 24
Peak memory 201820 kb
Host smart-f91df0a2-c8a4-44b8-94a4-b6ad81473754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635794441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_w
ith_pre_cond.2635794441
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1363257368
Short name T389
Test name
Test status
Simulation time 125194477979 ps
CPU time 163.74 seconds
Started Jul 11 04:54:39 PM PDT 24
Finished Jul 11 04:57:29 PM PDT 24
Peak memory 201856 kb
Host smart-b7fb02de-0d73-49f9-8ed9-6acc95760ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363257368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w
ith_pre_cond.1363257368
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.590529932
Short name T385
Test name
Test status
Simulation time 58337848422 ps
CPU time 20.68 seconds
Started Jul 11 04:54:45 PM PDT 24
Finished Jul 11 04:55:08 PM PDT 24
Peak memory 201852 kb
Host smart-308bf36f-e39a-42cd-964d-ee6182c4d115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590529932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_wi
th_pre_cond.590529932
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2299413439
Short name T384
Test name
Test status
Simulation time 81002003859 ps
CPU time 213.34 seconds
Started Jul 11 04:54:39 PM PDT 24
Finished Jul 11 04:58:18 PM PDT 24
Peak memory 201780 kb
Host smart-b92812be-8fdf-4911-9841-c6056190fad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299413439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_w
ith_pre_cond.2299413439
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.3192755508
Short name T717
Test name
Test status
Simulation time 27080192608 ps
CPU time 65.3 seconds
Started Jul 11 04:54:37 PM PDT 24
Finished Jul 11 04:55:49 PM PDT 24
Peak memory 201804 kb
Host smart-00804f10-8aeb-45b5-b7a2-b57423d8ec6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192755508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_w
ith_pre_cond.3192755508
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.2929153172
Short name T391
Test name
Test status
Simulation time 148341721523 ps
CPU time 348.12 seconds
Started Jul 11 04:54:49 PM PDT 24
Finished Jul 11 05:00:39 PM PDT 24
Peak memory 201852 kb
Host smart-ea79b931-2e6a-4eaa-8f35-1bc9d0b5aa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929153172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.2929153172
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1260105993
Short name T644
Test name
Test status
Simulation time 66978249020 ps
CPU time 179.59 seconds
Started Jul 11 04:54:39 PM PDT 24
Finished Jul 11 04:57:44 PM PDT 24
Peak memory 202084 kb
Host smart-506b92c7-ba54-4c7d-8a79-45fb384927eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260105993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.1260105993
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3327142395
Short name T400
Test name
Test status
Simulation time 72334564461 ps
CPU time 90.57 seconds
Started Jul 11 04:54:35 PM PDT 24
Finished Jul 11 04:56:13 PM PDT 24
Peak memory 201808 kb
Host smart-474ed853-9bde-4206-b236-dd663481ae08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327142395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.3327142395
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.4086248507
Short name T428
Test name
Test status
Simulation time 2043927558 ps
CPU time 1.46 seconds
Started Jul 11 04:53:04 PM PDT 24
Finished Jul 11 04:53:10 PM PDT 24
Peak memory 201580 kb
Host smart-e6644ef8-58ab-4966-b245-baa7dfdf8d76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086248507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.4086248507
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1186887048
Short name T189
Test name
Test status
Simulation time 3132400553 ps
CPU time 8.51 seconds
Started Jul 11 04:53:03 PM PDT 24
Finished Jul 11 04:53:17 PM PDT 24
Peak memory 201600 kb
Host smart-15c6eaac-ef67-44fa-b007-4e45c1db67df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186887048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.1186887048
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.106305591
Short name T273
Test name
Test status
Simulation time 94726075504 ps
CPU time 119.9 seconds
Started Jul 11 04:53:05 PM PDT 24
Finished Jul 11 04:55:10 PM PDT 24
Peak memory 201816 kb
Host smart-7513297a-0244-468c-98bb-c3ea77b1e89e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106305591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_combo_detect.106305591
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1402417277
Short name T388
Test name
Test status
Simulation time 100293984097 ps
CPU time 245.49 seconds
Started Jul 11 04:53:02 PM PDT 24
Finished Jul 11 04:57:13 PM PDT 24
Peak memory 201728 kb
Host smart-465864cc-6e69-4b4c-8b8c-5f78d7cb3e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402417277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.1402417277
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2565575572
Short name T711
Test name
Test status
Simulation time 4577901451 ps
CPU time 11.44 seconds
Started Jul 11 04:53:06 PM PDT 24
Finished Jul 11 04:53:23 PM PDT 24
Peak memory 201536 kb
Host smart-51463492-8509-44ec-b242-322f9d557e66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565575572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.2565575572
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.787251168
Short name T757
Test name
Test status
Simulation time 3673895827 ps
CPU time 1.03 seconds
Started Jul 11 04:53:10 PM PDT 24
Finished Jul 11 04:53:18 PM PDT 24
Peak memory 201500 kb
Host smart-8d6a7b32-0ac2-4777-9820-5ae99e7a8c05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787251168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl
_edge_detect.787251168
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1631324963
Short name T478
Test name
Test status
Simulation time 2634751529 ps
CPU time 2.44 seconds
Started Jul 11 04:53:05 PM PDT 24
Finished Jul 11 04:53:13 PM PDT 24
Peak memory 201504 kb
Host smart-f67b91fd-c2d1-425b-939b-1eaae82e219b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631324963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.1631324963
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1491944153
Short name T643
Test name
Test status
Simulation time 2479289599 ps
CPU time 7.05 seconds
Started Jul 11 04:53:02 PM PDT 24
Finished Jul 11 04:53:15 PM PDT 24
Peak memory 201620 kb
Host smart-16967294-0de3-4f1f-8c32-7fd6f2958fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491944153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.1491944153
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1481723160
Short name T590
Test name
Test status
Simulation time 2195624491 ps
CPU time 3.6 seconds
Started Jul 11 04:53:01 PM PDT 24
Finished Jul 11 04:53:10 PM PDT 24
Peak memory 201564 kb
Host smart-38916641-44a3-4ed1-96c6-5c516664cf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481723160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.1481723160
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2969752114
Short name T4
Test name
Test status
Simulation time 2519630129 ps
CPU time 3.96 seconds
Started Jul 11 04:53:10 PM PDT 24
Finished Jul 11 04:53:21 PM PDT 24
Peak memory 201480 kb
Host smart-41607df8-ee1f-41e3-bb0e-d03a272f3ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969752114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.2969752114
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.60829885
Short name T161
Test name
Test status
Simulation time 2115004851 ps
CPU time 3.33 seconds
Started Jul 11 04:53:10 PM PDT 24
Finished Jul 11 04:53:21 PM PDT 24
Peak memory 201564 kb
Host smart-b49646ab-ba88-4f79-8d8e-77a63b1e1754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60829885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.60829885
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.2782933149
Short name T707
Test name
Test status
Simulation time 61042497235 ps
CPU time 159.45 seconds
Started Jul 11 04:53:11 PM PDT 24
Finished Jul 11 04:55:57 PM PDT 24
Peak memory 201740 kb
Host smart-7da1a7b6-d154-47c4-98a9-5919da7689c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782933149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.2782933149
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2087404011
Short name T349
Test name
Test status
Simulation time 749650556800 ps
CPU time 108.69 seconds
Started Jul 11 04:53:04 PM PDT 24
Finished Jul 11 04:54:58 PM PDT 24
Peak memory 214884 kb
Host smart-04bcee39-e294-4510-9755-eed1fc7251f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087404011 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.2087404011
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2478292274
Short name T494
Test name
Test status
Simulation time 30427061168 ps
CPU time 6.54 seconds
Started Jul 11 04:54:45 PM PDT 24
Finished Jul 11 04:54:54 PM PDT 24
Peak memory 201888 kb
Host smart-92889aa4-4e76-482a-bb70-0bcfc32e563c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478292274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.2478292274
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.153117299
Short name T610
Test name
Test status
Simulation time 69350207286 ps
CPU time 64.99 seconds
Started Jul 11 04:54:39 PM PDT 24
Finished Jul 11 04:55:50 PM PDT 24
Peak memory 202172 kb
Host smart-091f5888-43fd-4669-8a08-69a8c7cef0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153117299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_wi
th_pre_cond.153117299
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.187749927
Short name T392
Test name
Test status
Simulation time 107762037958 ps
CPU time 72 seconds
Started Jul 11 04:54:45 PM PDT 24
Finished Jul 11 04:55:59 PM PDT 24
Peak memory 201916 kb
Host smart-ac2480df-4b6c-4a15-a84c-238fd3a582fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187749927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_wi
th_pre_cond.187749927
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.831962225
Short name T705
Test name
Test status
Simulation time 26577220930 ps
CPU time 72.56 seconds
Started Jul 11 04:54:40 PM PDT 24
Finished Jul 11 04:55:59 PM PDT 24
Peak memory 201828 kb
Host smart-0008c06a-f4fd-469c-b2a2-7797345da8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831962225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_wi
th_pre_cond.831962225
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1435972230
Short name T97
Test name
Test status
Simulation time 35613894152 ps
CPU time 49.82 seconds
Started Jul 11 04:54:37 PM PDT 24
Finished Jul 11 04:55:34 PM PDT 24
Peak memory 201816 kb
Host smart-4b57fa9b-d5b8-4cfb-8371-5c8b4f01b2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435972230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.1435972230
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2599947332
Short name T658
Test name
Test status
Simulation time 42545674509 ps
CPU time 13.85 seconds
Started Jul 11 04:54:42 PM PDT 24
Finished Jul 11 04:55:01 PM PDT 24
Peak memory 201772 kb
Host smart-4f0517bf-8ac3-4b1d-a7e5-e46fa7a085ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599947332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.2599947332
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1734024109
Short name T507
Test name
Test status
Simulation time 131365253458 ps
CPU time 83.29 seconds
Started Jul 11 04:54:39 PM PDT 24
Finished Jul 11 04:56:08 PM PDT 24
Peak memory 201748 kb
Host smart-90b8784a-bdfa-413a-a8a7-9fca7fe64df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734024109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.1734024109
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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