| | | | | | |
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.aDataKnown_M
| 0 | 0 | 1068383312 | 3424504 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A
| 0 | 0 | 1068382754 | 6003 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.contigMask_M
| 0 | 0 | 1068383312 | 18037125 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.dDataKnown_A
| 0 | 0 | 1068383312 | 195635 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A
| 0 | 0 | 1068382754 | 6275 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAParam_M
| 0 | 0 | 1068383312 | 20690527 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalDParam_A
| 0 | 0 | 1068383312 | 588288 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M
| 0 | 0 | 1068383312 | 20690527 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A
| 0 | 0 | 1068383312 | 588288 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respOpcode_A
| 0 | 0 | 1068383312 | 588288 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A
| 0 | 0 | 1068383312 | 588288 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A
| 0 | 0 | 1068382754 | 3965 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A
| 0 | 0 | 1068382754 | 3640 | 0 | 0 |
|
tb.dut.tlul_assert_device.p_dbw.TlDbw_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.u_reg.en2addrHit
| 0 | 0 | 1068382754 | 268893 | 0 | 0 |
|
tb.dut.u_reg.reAfterRv
| 0 | 0 | 1068382754 | 268893 | 0 | 0 |
|
tb.dut.u_reg.rePulse
| 0 | 0 | 1068382754 | 140340 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1231739 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1392 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1392 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1392 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 1332 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1400 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1139894 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1223 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1223 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1223 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 1159 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1231 | 0 | 0 |
|
tb.dut.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1773964 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1954 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1954 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1954 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 1895 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1962 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1730534 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1889 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1889 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1889 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 1826 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1896 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1708258 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1873 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1873 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1873 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 1808 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1879 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1735887 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1912 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1912 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1912 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 1847 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1919 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1768343 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1953 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1953 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1953 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 1889 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1959 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1734102 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1916 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1916 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1916 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 1849 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1923 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1695854 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1877 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1877 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1877 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 1813 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1884 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1736062 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1909 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1909 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1909 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 1845 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1914 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1273751 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1251 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1251 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1251 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 1192 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1259 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1206147 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1212 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1212 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1212 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 1154 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1221 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1263934 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1268 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1268 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1268 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 1203 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1274 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1245479 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1254 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1254 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1254 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 1192 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1262 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 7105792 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 7431 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 7431 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 7431 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 7368 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 7438 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 6956839 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 7323 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 7323 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 7323 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 7265 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 7332 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 6693675 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 7230 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 7230 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 7230 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 7169 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 7236 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 6988194 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 7462 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 7462 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 7462 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 7396 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 7468 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 7682119 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 8136 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 8136 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 8136 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 8075 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 8142 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 7451374 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 7938 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 7938 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 7938 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 7877 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 7946 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 7255841 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 7910 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 7910 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 7910 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 7850 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 7918 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 7548482 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 8123 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 8123 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 8123 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 8059 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 8130 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1827877 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 2051 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 2051 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 2051 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 1990 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 2058 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1070118 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1035 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1035 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1035 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 971 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1042 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1846109 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 2053 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 2053 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 2053 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 1992 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 2062 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 2753388 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 2948 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 2948 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 2948 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 2885 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 2954 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 5172592 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 6169 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 6169 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 6169 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 6107 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 6181 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 6220743 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 7371 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 7371 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 7371 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 7305 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 7381 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 5113657 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 6080 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 6080 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 6080 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 6020 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 6094 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 909 | 909 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1027249 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1023 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1023 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1023 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 960 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1029 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1056277 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1063 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1063 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1063 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 998 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1069 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1021757 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1019 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1019 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1019 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 962 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1027 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1043319 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1027 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1068382754 | 1027 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6018862 | 1027 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 964 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1037 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.BusySrcReqChk_A
| 0 | 0 | 1068382754 | 1051016 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.DstReqKnown_A
| 0 | 0 | 6018862 | 5207216 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.SrcAckBusyChk_A
| 0 | 0 | 1068382754 | 1177 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.SrcBusyKnown_A
| 0 | 0 | 1068382754 | 1066825072 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 6018862 | 768 | 0 | 909 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 6018862 | 768 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 1068382754 | 1945 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 6018862 | 1059 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6018862 | 1118 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1068382754 | 1185 | 0 | 0 |
|
tb.dut.u_reg.wePulse
| 0 | 0 | 1068382754 | 128553 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.CntClr_A
| 0 | 0 | 5765374 | 267 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.CntIncr_A
| 0 | 0 | 5765374 | 44023 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.CntNoWrap_A
| 0 | 0 | 5765374 | 5138983 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DetectStDropOut_A
| 0 | 0 | 5765374 | 2 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DetectedOut_A
| 0 | 0 | 5765374 | 794 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DetectedPulseOut_A
| 0 | 0 | 5765374 | 115 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DisabledIdleSt_A
| 0 | 0 | 5765374 | 5063143 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DisabledNoDetection_A
| 0 | 0 | 5765374 | 5065383 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.EnterDebounceSt_A
| 0 | 0 | 5765374 | 153 | 0 | 0 |
|