Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T2,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T23,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T23,T24
1	0	Covered	T1,T2,T12
1	1	Covered	T2,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T23,T24
0	1	Covered	T27,T77
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T23,T24
0	1	Covered	T2,T23,T24
1	0	Covered	T52,T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T23,T24
1	-	Covered	T2,T23,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T23,T24
DetectSt	168	Covered	T2,T23,T24
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T2,T23,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T23,T24
DebounceSt->IdleSt	163	Covered	T2,T24,T27
DetectSt->IdleSt	186	Covered	T27,T77
DetectSt->StableSt	191	Covered	T2,T23,T24
IdleSt->DebounceSt	148	Covered	T2,T23,T24
StableSt->IdleSt	206	Covered	T2,T23,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T23,T24
0	1	Covered	T2,T23,T24
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T23,T24
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T23,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T24,T27
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T27,T77
DetectSt	-	-	-	-	0	1	-	Covered	T2,T23,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T23,T24
StableSt	-	-	-	-	-	-	0	Covered	T2,T23,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	267	0	0
CntIncr_A	5765374	44023	0	0
CntNoWrap_A	5765374	5138983	0	0
DetectStDropOut_A	5765374	2	0	0
DetectedOut_A	5765374	794	0	0
DetectedPulseOut_A	5765374	115	0	0
DisabledIdleSt_A	5765374	5063143	0	0
DisabledNoDetection_A	5765374	5065383	0	0
EnterDebounceSt_A	5765374	153	0	0
EnterDetectSt_A	5765374	117	0	0
EnterStableSt_A	5765374	115	0	0
PulseIsPulse_A	5765374	115	0	0
StayInStableSt	5765374	679	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5765374	6989	0	0
gen_low_level_sva.LowLevelEvent_A	5765374	5141548	0	0
gen_not_sticky_sva.StableStDropOut_A	5765374	113	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	267	0	0
T2	13420	5	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T23	0	2	0	0
T24	0	4	0	0
T27	0	8	0	0
T28	0	2	0	0
T32	0	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	4	0	0
T46	433	0	0	0
T88	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	44023	0	0
T2	13420	119	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T23	0	12	0	0
T24	0	206	0	0
T27	0	277	0	0
T28	0	66	0	0
T32	0	26	0	0
T42	0	83	0	0
T43	0	34	0	0
T44	0	131	0	0
T46	433	0	0	0
T88	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5138983	0	0
T1	28795	28313	0	0
T2	13420	7379	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	2	0	0
T27	18350	1	0	0
T32	36325	0	0	0
T37	29747	0	0	0
T54	2484	0	0	0
T68	4525	0	0	0
T77	0	1	0	0
T101	437	0	0	0
T102	569	0	0	0
T103	449	0	0	0
T104	497	0	0	0
T105	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	794	0	0
T2	13420	12	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T23	0	2	0	0
T24	0	6	0	0
T27	0	14	0	0
T28	0	7	0	0
T42	0	9	0	0
T43	0	8	0	0
T44	0	18	0	0
T46	433	0	0	0
T88	0	9	0	0
T106	0	2	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	115	0	0
T2	13420	2	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T27	0	2	0	0
T28	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T46	433	0	0	0
T88	0	1	0	0
T106	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5063143	0	0
T1	28795	28313	0	0
T2	13420	7145	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5065383	0	0
T1	28795	28325	0	0
T2	13420	7160	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	153	0	0
T2	13420	3	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T23	0	1	0	0
T24	0	3	0	0
T27	0	5	0	0
T28	0	1	0	0
T32	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T46	433	0	0	0
T88	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	117	0	0
T2	13420	2	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T27	0	3	0	0
T28	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T46	433	0	0	0
T88	0	1	0	0
T106	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	115	0	0
T2	13420	2	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T27	0	2	0	0
T28	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T46	433	0	0	0
T88	0	1	0	0
T106	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	115	0	0
T2	13420	2	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T27	0	2	0	0
T28	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T46	433	0	0	0
T88	0	1	0	0
T106	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	679	0	0
T2	13420	10	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T23	0	1	0	0
T24	0	5	0	0
T27	0	12	0	0
T28	0	6	0	0
T42	0	8	0	0
T43	0	7	0	0
T44	0	16	0	0
T46	433	0	0	0
T88	0	8	0	0
T106	0	1	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	6989	0	0
T1	28795	12	0	0
T2	13420	40	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	1	0	0
T6	15908	14	0	0
T12	16327	13	0	0
T13	492	8	0	0
T14	522	7	0	0
T15	527	4	0	0
T46	0	5	0	0
T107	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	113	0	0
T2	13420	2	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T27	0	2	0	0
T28	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T46	433	0	0	0
T88	0	1	0	0
T106	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T19,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T19,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T19,T20,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T1,T2,T12
1	1	Covered	T19,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T32
0	1	Covered	T32,T34,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T32
0	1	Unreachable
1	0	Covered	T19,T20,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T20,T21
DetectSt	168	Covered	T19,T20,T32
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T19,T20,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T20,T32
DebounceSt->IdleSt	163	Covered	T21,T34,T109
DetectSt->IdleSt	186	Covered	T32,T34,T80
DetectSt->StableSt	191	Covered	T19,T20,T32
IdleSt->DebounceSt	148	Covered	T19,T20,T21
StableSt->IdleSt	206	Covered	T19,T20,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T20,T21
0	1	Covered	T19,T20,T21
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T32
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T20,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T34,T109
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T32,T34,T80
DetectSt	-	-	-	-	0	1	-	Covered	T19,T20,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T20,T32
StableSt	-	-	-	-	-	-	0	Covered	T19,T20,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	158	0	0
CntIncr_A	5765374	198852	0	0
CntNoWrap_A	5765374	5139092	0	0
DetectStDropOut_A	5765374	12	0	0
DetectedOut_A	5765374	217884	0	0
DetectedPulseOut_A	5765374	52	0	0
DisabledIdleSt_A	5765374	4331088	0	0
DisabledNoDetection_A	5765374	4333386	0	0
EnterDebounceSt_A	5765374	95	0	0
EnterDetectSt_A	5765374	64	0	0
EnterStableSt_A	5765374	52	0	0
PulseIsPulse_A	5765374	52	0	0
StayInStableSt	5765374	217832	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5765374	6989	0	0
gen_low_level_sva.LowLevelEvent_A	5765374	5141548	0	0
gen_sticky_sva.StableStDropOut_A	5765374	387260	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	158	0	0
T19	1121	6	0	0
T20	1329	6	0	0
T21	1979	1	0	0
T27	18350	0	0	0
T28	0	2	0	0
T32	0	8	0	0
T34	0	5	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T44	0	2	0	0
T53	23934	0	0	0
T55	0	2	0	0
T57	0	2	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	198852	0	0
T19	1121	84	0	0
T20	1329	123	0	0
T21	1979	46	0	0
T27	18350	0	0	0
T28	0	82	0	0
T32	0	326	0	0
T34	0	72	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T44	0	81	0	0
T53	23934	0	0	0
T55	0	24	0	0
T57	0	24	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5139092	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	12	0	0
T32	36325	2	0	0
T34	0	1	0	0
T41	736	0	0	0
T42	633	0	0	0
T68	4525	0	0	0
T80	0	2	0	0
T102	569	0	0	0
T103	449	0	0	0
T104	497	0	0	0
T105	424	0	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	5	0	0
T114	493	0	0	0
T115	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	217884	0	0
T19	1121	47	0	0
T20	1329	524	0	0
T21	1979	0	0	0
T27	18350	0	0	0
T28	0	28	0	0
T32	0	81	0	0
T34	0	199	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T44	0	183	0	0
T53	23934	0	0	0
T55	0	81	0	0
T57	0	60	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	308	0	0
T108	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	52	0	0
T19	1121	3	0	0
T20	1329	3	0	0
T21	1979	0	0	0
T27	18350	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T34	0	1	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T44	0	1	0	0
T53	23934	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	1	0	0
T108	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4331088	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4333386	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	95	0	0
T19	1121	3	0	0
T20	1329	3	0	0
T21	1979	1	0	0
T27	18350	0	0	0
T28	0	1	0	0
T32	0	4	0	0
T34	0	3	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T44	0	1	0	0
T53	23934	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	64	0	0
T19	1121	3	0	0
T20	1329	3	0	0
T21	1979	0	0	0
T27	18350	0	0	0
T28	0	1	0	0
T32	0	4	0	0
T34	0	2	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T44	0	1	0	0
T53	23934	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	1	0	0
T108	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	52	0	0
T19	1121	3	0	0
T20	1329	3	0	0
T21	1979	0	0	0
T27	18350	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T34	0	1	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T44	0	1	0	0
T53	23934	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	1	0	0
T108	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	52	0	0
T19	1121	3	0	0
T20	1329	3	0	0
T21	1979	0	0	0
T27	18350	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T34	0	1	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T44	0	1	0	0
T53	23934	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	1	0	0
T108	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	217832	0	0
T19	1121	44	0	0
T20	1329	521	0	0
T21	1979	0	0	0
T27	18350	0	0	0
T28	0	27	0	0
T32	0	79	0	0
T34	0	198	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T44	0	182	0	0
T53	23934	0	0	0
T55	0	80	0	0
T57	0	59	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	307	0	0
T108	0	2	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	6989	0	0
T1	28795	12	0	0
T2	13420	40	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	1	0	0
T6	15908	14	0	0
T12	16327	13	0	0
T13	492	8	0	0
T14	522	7	0	0
T15	527	4	0	0
T46	0	5	0	0
T107	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	387260	0	0
T19	1121	462	0	0
T20	1329	164	0	0
T21	1979	0	0	0
T27	18350	0	0	0
T28	0	24	0	0
T32	0	218	0	0
T34	0	244	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T44	0	239	0	0
T53	23934	0	0	0
T55	0	192	0	0
T57	0	67	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	65	0	0
T108	0	52	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T3,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T3,T13
1	1	Covered	T2,T3,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T19,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T19,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T19,T20,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T2,T3,T13
1	1	Covered	T19,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Covered	T20,T84,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Unreachable
1	0	Covered	T19,T20,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T20,T21
DetectSt	168	Covered	T19,T20,T21
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T19,T20,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T20,T21
DebounceSt->IdleSt	163	Covered	T20,T44,T34
DetectSt->IdleSt	186	Covered	T20,T84,T85
DetectSt->StableSt	191	Covered	T19,T20,T21
IdleSt->DebounceSt	148	Covered	T19,T20,T21
StableSt->IdleSt	206	Covered	T19,T20,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T20,T21
0	1	Covered	T19,T20,T21
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T2,T3,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T20,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T44,T34
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T20,T84,T85
DetectSt	-	-	-	-	0	1	-	Covered	T19,T20,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T20,T21
StableSt	-	-	-	-	-	-	0	Covered	T19,T20,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	169	0	0
CntIncr_A	5765374	69063	0	0
CntNoWrap_A	5765374	5139081	0	0
DetectStDropOut_A	5765374	14	0	0
DetectedOut_A	5765374	231603	0	0
DetectedPulseOut_A	5765374	47	0	0
DisabledIdleSt_A	5765374	4331088	0	0
DisabledNoDetection_A	5765374	4333386	0	0
EnterDebounceSt_A	5765374	109	0	0
EnterDetectSt_A	5765374	61	0	0
EnterStableSt_A	5765374	47	0	0
PulseIsPulse_A	5765374	47	0	0
StayInStableSt	5765374	231556	0	0
gen_high_level_sva.HighLevelEvent_A	5765374	5141548	0	0
gen_sticky_sva.StableStDropOut_A	5765374	209256	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	169	0	0
T19	1121	6	0	0
T20	1329	13	0	0
T21	1979	2	0	0
T27	18350	0	0	0
T28	0	2	0	0
T32	0	4	0	0
T34	0	7	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T44	0	3	0	0
T53	23934	0	0	0
T55	0	2	0	0
T57	0	2	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	69063	0	0
T19	1121	51	0	0
T20	1329	224	0	0
T21	1979	49	0	0
T27	18350	0	0	0
T28	0	49	0	0
T32	0	123	0	0
T34	0	444	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T44	0	138	0	0
T53	23934	0	0	0
T55	0	59	0	0
T57	0	10	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5139081	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	14	0	0
T20	1329	4	0	0
T21	1979	0	0	0
T27	18350	0	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T53	23934	0	0	0
T54	2484	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T84	0	1	0	0
T85	0	3	0	0
T100	0	3	0	0
T101	437	0	0	0
T116	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	231603	0	0
T19	1121	25	0	0
T20	1329	68	0	0
T21	1979	32	0	0
T27	18350	0	0	0
T28	0	34	0	0
T32	0	252	0	0
T34	0	151	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T53	23934	0	0	0
T55	0	160	0	0
T57	0	70	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T109	0	180	0	0
T110	0	87	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	47	0	0
T19	1121	3	0	0
T20	1329	2	0	0
T21	1979	1	0	0
T27	18350	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T34	0	1	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T53	23934	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T109	0	1	0	0
T110	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4331088	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4333386	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	109	0	0
T19	1121	3	0	0
T20	1329	7	0	0
T21	1979	1	0	0
T27	18350	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T34	0	6	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T44	0	3	0	0
T53	23934	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	61	0	0
T19	1121	3	0	0
T20	1329	6	0	0
T21	1979	1	0	0
T27	18350	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T34	0	1	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T53	23934	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T109	0	1	0	0
T110	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	47	0	0
T19	1121	3	0	0
T20	1329	2	0	0
T21	1979	1	0	0
T27	18350	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T34	0	1	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T53	23934	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T109	0	1	0	0
T110	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	47	0	0
T19	1121	3	0	0
T20	1329	2	0	0
T21	1979	1	0	0
T27	18350	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T34	0	1	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T53	23934	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T109	0	1	0	0
T110	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	231556	0	0
T19	1121	22	0	0
T20	1329	66	0	0
T21	1979	31	0	0
T27	18350	0	0	0
T28	0	33	0	0
T32	0	250	0	0
T34	0	150	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T53	23934	0	0	0
T55	0	159	0	0
T57	0	69	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T109	0	179	0	0
T110	0	86	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	209256	0	0
T19	1121	505	0	0
T20	1329	226	0	0
T21	1979	36	0	0
T27	18350	0	0	0
T28	0	39	0	0
T32	0	281	0	0
T34	0	50	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T53	23934	0	0	0
T55	0	66	0	0
T57	0	109	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T109	0	579	0	0
T110	0	191	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T19,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T19,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T19,T20,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T19,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Covered	T34,T80,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Unreachable
1	0	Covered	T19,T20,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T20,T21
DetectSt	168	Covered	T19,T20,T21
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T19,T20,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T20,T21
DebounceSt->IdleSt	163	Covered	T44,T34,T80
DetectSt->IdleSt	186	Covered	T34,T80,T81
DetectSt->StableSt	191	Covered	T19,T20,T21
IdleSt->DebounceSt	148	Covered	T19,T20,T21
StableSt->IdleSt	206	Covered	T19,T20,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T20,T21
0	1	Covered	T19,T20,T21
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T20,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T34,T80
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T34,T80,T81
DetectSt	-	-	-	-	0	1	-	Covered	T19,T20,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T20,T21
StableSt	-	-	-	-	-	-	0	Covered	T19,T20,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	181	0	0
CntIncr_A	5765374	43430	0	0
CntNoWrap_A	5765374	5139069	0	0
DetectStDropOut_A	5765374	18	0	0
DetectedOut_A	5765374	61726	0	0
DetectedPulseOut_A	5765374	48	0	0
DisabledIdleSt_A	5765374	4331088	0	0
DisabledNoDetection_A	5765374	4333386	0	0
EnterDebounceSt_A	5765374	116	0	0
EnterDetectSt_A	5765374	66	0	0
EnterStableSt_A	5765374	48	0	0
PulseIsPulse_A	5765374	48	0	0
StayInStableSt	5765374	61678	0	0
gen_high_event_sva.HighLevelEvent_A	5765374	5141548	0	0
gen_high_level_sva.HighLevelEvent_A	5765374	5141548	0	0
gen_sticky_sva.StableStDropOut_A	5765374	658910	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	181	0	0
T19	1121	6	0	0
T20	1329	6	0	0
T21	1979	2	0	0
T27	18350	0	0	0
T28	0	2	0	0
T32	0	4	0	0
T34	0	9	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T44	0	3	0	0
T53	23934	0	0	0
T55	0	2	0	0
T57	0	2	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	43430	0	0
T19	1121	219	0	0
T20	1329	120	0	0
T21	1979	85	0	0
T27	18350	0	0	0
T28	0	99	0	0
T32	0	52	0	0
T34	0	288	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T44	0	177	0	0
T53	23934	0	0	0
T55	0	37	0	0
T57	0	21	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5139069	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	18	0	0
T33	4491	0	0	0
T34	42456	2	0	0
T71	4769	0	0	0
T80	0	3	0	0
T81	0	1	0	0
T100	0	1	0	0
T113	0	2	0	0
T117	0	2	0	0
T118	0	1	0	0
T119	0	3	0	0
T120	0	2	0	0
T121	0	1	0	0
T122	7025	0	0	0
T123	407	0	0	0
T124	483	0	0	0
T125	491	0	0	0
T126	504	0	0	0
T127	14601	0	0	0
T128	529	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	61726	0	0
T19	1121	312	0	0
T20	1329	427	0	0
T21	1979	18	0	0
T27	18350	0	0	0
T28	0	15	0	0
T32	0	176	0	0
T34	0	92	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T53	23934	0	0	0
T55	0	95	0	0
T57	0	77	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	211	0	0
T108	0	10	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	48	0	0
T19	1121	3	0	0
T20	1329	3	0	0
T21	1979	1	0	0
T27	18350	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T34	0	1	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T53	23934	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	1	0	0
T108	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4331088	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4333386	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	116	0	0
T19	1121	3	0	0
T20	1329	3	0	0
T21	1979	1	0	0
T27	18350	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T34	0	6	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T44	0	3	0	0
T53	23934	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	66	0	0
T19	1121	3	0	0
T20	1329	3	0	0
T21	1979	1	0	0
T27	18350	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T34	0	3	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T53	23934	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	1	0	0
T108	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	48	0	0
T19	1121	3	0	0
T20	1329	3	0	0
T21	1979	1	0	0
T27	18350	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T34	0	1	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T53	23934	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	1	0	0
T108	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	48	0	0
T19	1121	3	0	0
T20	1329	3	0	0
T21	1979	1	0	0
T27	18350	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T34	0	1	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T53	23934	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	1	0	0
T108	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	61678	0	0
T19	1121	309	0	0
T20	1329	424	0	0
T21	1979	17	0	0
T27	18350	0	0	0
T28	0	14	0	0
T32	0	174	0	0
T34	0	91	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T53	23934	0	0	0
T55	0	94	0	0
T57	0	76	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	210	0	0
T108	0	9	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	658910	0	0
T19	1121	88	0	0
T20	1329	284	0	0
T21	1979	30	0	0
T27	18350	0	0	0
T28	0	27	0	0
T32	0	458	0	0
T34	0	113	0	0
T37	29747	0	0	0
T38	26543	0	0	0
T53	23934	0	0	0
T55	0	168	0	0
T57	0	110	0	0
T58	494	0	0	0
T59	5557	0	0	0
T60	11733	0	0	0
T73	0	191	0	0
T108	0	61	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T5,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T2,T5,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T5,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T5,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T30
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T30
0	1	Covered	T30,T32,T28
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T5,T30
1	-	Covered	T30,T32,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T5,T30
DetectSt	168	Covered	T2,T5,T30
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T2,T5,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T5,T30
DebounceSt->IdleSt	163	Covered	T34,T129,T130
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T5,T30
IdleSt->DebounceSt	148	Covered	T2,T5,T30
StableSt->IdleSt	206	Covered	T2,T30,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T5,T30
0	1	Covered	T2,T5,T30
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T30
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T5,T30
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T5,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T129,T130
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T5,T30
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T5,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T32,T28
StableSt	-	-	-	-	-	-	0	Covered	T2,T5,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	94	0	0
CntIncr_A	5765374	2461	0	0
CntNoWrap_A	5765374	5139156	0	0
DetectStDropOut_A	5765374	0	0	0
DetectedOut_A	5765374	4035	0	0
DetectedPulseOut_A	5765374	45	0	0
DisabledIdleSt_A	5765374	5121181	0	0
DisabledNoDetection_A	5765374	5123427	0	0
EnterDebounceSt_A	5765374	49	0	0
EnterDetectSt_A	5765374	45	0	0
EnterStableSt_A	5765374	45	0	0
PulseIsPulse_A	5765374	45	0	0
StayInStableSt	5765374	3963	0	0
gen_high_level_sva.HighLevelEvent_A	5765374	5141548	0	0
gen_not_sticky_sva.StableStDropOut_A	5765374	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	94	0	0
T2	13420	2	0	0
T3	628	0	0	0
T5	566	2	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	2	0	0
T30	0	4	0	0
T32	0	2	0	0
T34	0	3	0	0
T46	433	0	0	0
T81	0	2	0	0
T131	0	2	0	0
T132	0	2	0	0
T133	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	2461	0	0
T2	13420	95	0	0
T3	628	0	0	0
T5	566	16	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	23	0	0
T30	0	56	0	0
T32	0	21	0	0
T34	0	168	0	0
T46	433	0	0	0
T81	0	14	0	0
T131	0	97	0	0
T132	0	54	0	0
T133	0	75	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5139156	0	0
T1	28795	28313	0	0
T2	13420	7382	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	163	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4035	0	0
T2	13420	41	0	0
T3	628	0	0	0
T5	566	54	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	17	0	0
T30	0	111	0	0
T32	0	74	0	0
T34	0	48	0	0
T46	433	0	0	0
T81	0	43	0	0
T131	0	167	0	0
T132	0	46	0	0
T133	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	45	0	0
T2	13420	1	0	0
T3	628	0	0	0
T5	566	1	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T34	0	1	0	0
T46	433	0	0	0
T81	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5121181	0	0
T1	28795	28313	0	0
T2	13420	6624	0	0
T3	628	3	0	0
T4	407	6	0	0
T5	566	4	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5123427	0	0
T1	28795	28325	0	0
T2	13420	6640	0	0
T3	628	3	0	0
T4	407	7	0	0
T5	566	4	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	49	0	0
T2	13420	1	0	0
T3	628	0	0	0
T5	566	1	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T46	433	0	0	0
T81	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	45	0	0
T2	13420	1	0	0
T3	628	0	0	0
T5	566	1	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T34	0	1	0	0
T46	433	0	0	0
T81	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	45	0	0
T2	13420	1	0	0
T3	628	0	0	0
T5	566	1	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T34	0	1	0	0
T46	433	0	0	0
T81	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	45	0	0
T2	13420	1	0	0
T3	628	0	0	0
T5	566	1	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T34	0	1	0	0
T46	433	0	0	0
T81	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	3963	0	0
T2	13420	39	0	0
T3	628	0	0	0
T5	566	52	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T28	0	16	0	0
T30	0	108	0	0
T32	0	73	0	0
T34	0	46	0	0
T46	433	0	0	0
T81	0	41	0	0
T131	0	165	0	0
T132	0	44	0	0
T133	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	17	0	0
T19	1121	0	0	0
T20	1329	0	0	0
T24	708	0	0	0
T28	0	1	0	0
T30	770	1	0	0
T31	868	0	0	0
T32	0	1	0	0
T58	494	0	0	0
T64	498	0	0	0
T83	0	1	0	0
T86	30216	0	0	0
T87	2102	0	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	2	0	0
T140	679	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T32,T28,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T32,T28,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T32,T28,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T32,T28
1	0	Covered	T1,T2,T12
1	1	Covered	T32,T28,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T32,T28,T33
0	1	Covered	T76,T83,T141
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T29
0	1	Covered	T32,T28,T29
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T32,T33,T29
1	-	Covered	T32,T28,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T28,T33
DetectSt	168	Covered	T32,T28,T33
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T32,T28,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T32,T28,T33
DebounceSt->IdleSt	163	Covered	T142,T134,T143
DetectSt->IdleSt	186	Covered	T76,T83,T141
DetectSt->StableSt	191	Covered	T32,T28,T33
IdleSt->DebounceSt	148	Covered	T32,T28,T33
StableSt->IdleSt	206	Covered	T32,T28,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T32,T28,T33
0	1	Covered	T32,T28,T33
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T32,T28,T33
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T28,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T74
DebounceSt	-	0	1	1	-	-	-	Covered	T32,T28,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T142,T134,T143
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T28,T33
DetectSt	-	-	-	-	1	-	-	Covered	T76,T83,T141
DetectSt	-	-	-	-	0	1	-	Covered	T32,T28,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T28,T29
StableSt	-	-	-	-	-	-	0	Covered	T32,T33,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	126	0	0
CntIncr_A	5765374	9372	0	0
CntNoWrap_A	5765374	5139124	0	0
DetectStDropOut_A	5765374	4	0	0
DetectedOut_A	5765374	16545	0	0
DetectedPulseOut_A	5765374	56	0	0
DisabledIdleSt_A	5765374	5097702	0	0
DisabledNoDetection_A	5765374	5099944	0	0
EnterDebounceSt_A	5765374	66	0	0
EnterDetectSt_A	5765374	60	0	0
EnterStableSt_A	5765374	56	0	0
PulseIsPulse_A	5765374	56	0	0
StayInStableSt	5765374	16468	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5765374	2536	0	0
gen_low_level_sva.LowLevelEvent_A	5765374	5141548	0	0
gen_not_sticky_sva.StableStDropOut_A	5765374	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	126	0	0
T28	0	2	0	0
T29	0	2	0	0
T32	36325	4	0	0
T33	0	2	0	0
T41	736	0	0	0
T42	633	0	0	0
T68	4525	0	0	0
T76	0	2	0	0
T102	569	0	0	0
T103	449	0	0	0
T104	497	0	0	0
T105	424	0	0	0
T114	493	0	0	0
T115	522	0	0	0
T131	0	2	0	0
T133	0	2	0	0
T142	0	1	0	0
T144	0	2	0	0
T145	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	9372	0	0
T28	0	32	0	0
T29	0	21	0	0
T32	36325	42	0	0
T33	0	70	0	0
T41	736	0	0	0
T42	633	0	0	0
T68	4525	0	0	0
T76	0	29	0	0
T102	569	0	0	0
T103	449	0	0	0
T104	497	0	0	0
T105	424	0	0	0
T114	493	0	0	0
T115	522	0	0	0
T131	0	97	0	0
T133	0	75	0	0
T142	0	11	0	0
T144	0	81	0	0
T145	0	31	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5139124	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4	0	0
T76	512	1	0	0
T83	0	1	0	0
T85	1670	0	0	0
T141	0	1	0	0
T146	0	1	0	0
T147	502	0	0	0
T148	521	0	0	0
T149	406	0	0	0
T150	429	0	0	0
T151	5446	0	0	0
T152	1963	0	0	0
T153	593	0	0	0
T154	12669	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	16545	0	0
T28	0	1	0	0
T29	0	20	0	0
T32	36325	53	0	0
T33	0	251	0	0
T41	736	0	0	0
T42	633	0	0	0
T68	4525	0	0	0
T102	569	0	0	0
T103	449	0	0	0
T104	497	0	0	0
T105	424	0	0	0
T114	493	0	0	0
T115	522	0	0	0
T131	0	44	0	0
T133	0	25	0	0
T144	0	301	0	0
T145	0	195	0	0
T155	0	39	0	0
T156	0	112	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	56	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	36325	2	0	0
T33	0	1	0	0
T41	736	0	0	0
T42	633	0	0	0
T68	4525	0	0	0
T102	569	0	0	0
T103	449	0	0	0
T104	497	0	0	0
T105	424	0	0	0
T114	493	0	0	0
T115	522	0	0	0
T131	0	1	0	0
T133	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5097702	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	3	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5099944	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	3	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	66	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	36325	2	0	0
T33	0	1	0	0
T41	736	0	0	0
T42	633	0	0	0
T68	4525	0	0	0
T76	0	1	0	0
T102	569	0	0	0
T103	449	0	0	0
T104	497	0	0	0
T105	424	0	0	0
T114	493	0	0	0
T115	522	0	0	0
T131	0	1	0	0
T133	0	1	0	0
T142	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	60	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	36325	2	0	0
T33	0	1	0	0
T41	736	0	0	0
T42	633	0	0	0
T68	4525	0	0	0
T76	0	1	0	0
T102	569	0	0	0
T103	449	0	0	0
T104	497	0	0	0
T105	424	0	0	0
T114	493	0	0	0
T115	522	0	0	0
T131	0	1	0	0
T133	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	56	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	36325	2	0	0
T33	0	1	0	0
T41	736	0	0	0
T42	633	0	0	0
T68	4525	0	0	0
T102	569	0	0	0
T103	449	0	0	0
T104	497	0	0	0
T105	424	0	0	0
T114	493	0	0	0
T115	522	0	0	0
T131	0	1	0	0
T133	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	56	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	36325	2	0	0
T33	0	1	0	0
T41	736	0	0	0
T42	633	0	0	0
T68	4525	0	0	0
T102	569	0	0	0
T103	449	0	0	0
T104	497	0	0	0
T105	424	0	0	0
T114	493	0	0	0
T115	522	0	0	0
T131	0	1	0	0
T133	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	16468	0	0
T29	0	19	0	0
T32	36325	50	0	0
T33	0	249	0	0
T41	736	0	0	0
T42	633	0	0	0
T68	4525	0	0	0
T102	569	0	0	0
T103	449	0	0	0
T104	497	0	0	0
T105	424	0	0	0
T114	493	0	0	0
T115	522	0	0	0
T131	0	43	0	0
T133	0	24	0	0
T144	0	299	0	0
T145	0	193	0	0
T155	0	38	0	0
T156	0	111	0	0
T157	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	2536	0	0
T2	13420	32	0	0
T3	628	0	0	0
T5	566	1	0	0
T6	15908	0	0	0
T7	550	1	0	0
T12	16327	0	0	0
T13	492	6	0	0
T14	522	5	0	0
T15	527	4	0	0
T46	433	3	0	0
T47	0	3	0	0
T48	0	6	0	0
T107	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	34	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	36325	1	0	0
T41	736	0	0	0
T42	633	0	0	0
T68	4525	0	0	0
T102	569	0	0	0
T103	449	0	0	0
T104	497	0	0	0
T105	424	0	0	0
T114	493	0	0	0
T115	522	0	0	0
T131	0	1	0	0
T133	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0