Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl_combo
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.15 100.00 92.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_combo.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sysrst_ctrl_combo 96.15 100.00 92.31



Module Instance : tb.dut.u_sysrst_ctrl_combo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.15 100.00 92.31


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.12 100.00 97.61 100.00 98.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_combo_trigger[0].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[0].u_sysrst_ctrl_detect 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[0].u_sysrst_ctrl_detect_pre 99.05 100.00 100.00 100.00 95.24 100.00
gen_combo_trigger[1].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[1].u_sysrst_ctrl_detect 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[1].u_sysrst_ctrl_detect_pre 99.05 100.00 100.00 100.00 95.24 100.00
gen_combo_trigger[2].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[2].u_sysrst_ctrl_detect 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[2].u_sysrst_ctrl_detect_pre 97.99 100.00 94.74 100.00 95.24 100.00
gen_combo_trigger[3].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect_pre 99.05 100.00 100.00 100.00 95.24 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sysrst_ctrl_combo
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_combo.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_combo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 1 1
54 4 4
66 4 4
70 4 4
92 4 4
106 4 4
111 4 4
151 1 1
154 1 1
155 1 1


Cond Coverage for Module : sysrst_ctrl_combo
TotalCoveredPercent
Conditions524892.31
Logical524892.31
Non-Logical00
Event00

 LINE       70
 EXPRESSION ((in & gen_combo_trigger[0].cfg_in_pre) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT8,T10,T25
1CoveredT1,T4,T2

 LINE       70
 EXPRESSION ((in & gen_combo_trigger[1].cfg_in_pre) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT8,T10,T25
1CoveredT1,T4,T2

 LINE       70
 EXPRESSION ((in & gen_combo_trigger[2].cfg_in_pre) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT8,T10,T25
1CoveredT1,T4,T2

 LINE       70
 EXPRESSION ((in & gen_combo_trigger[3].cfg_in_pre) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT8,T10,T25
1CoveredT1,T4,T2

 LINE       106
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[0].cfg_in_sel)) && 
      2  ((gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en) || ((!gen_combo_trigger[0].cfg_combo_pre_en))))
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT8,T10,T25
11CoveredT1,T2,T12

 LINE       106
 SUB-EXPRESSION ((gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en) || ((!gen_combo_trigger[0].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------
-1--2-StatusTests
00CoveredT8,T10,T25
01CoveredT1,T4,T2
10CoveredT8,T10,T37

 LINE       106
 SUB-EXPRESSION (gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01CoveredT8,T10,T25
10Not Covered
11CoveredT8,T10,T37

 LINE       106
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[1].cfg_in_sel)) && 
      2  ((gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en) || ((!gen_combo_trigger[1].cfg_combo_pre_en))))
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT8,T10,T25
11CoveredT1,T2,T12

 LINE       106
 SUB-EXPRESSION ((gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en) || ((!gen_combo_trigger[1].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------
-1--2-StatusTests
00CoveredT8,T10,T25
01CoveredT1,T4,T2
10CoveredT8,T25,T38

 LINE       106
 SUB-EXPRESSION (gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01CoveredT8,T10,T25
10Not Covered
11CoveredT8,T25,T38

 LINE       106
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[2].cfg_in_sel)) && 
      2  ((gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en) || ((!gen_combo_trigger[2].cfg_combo_pre_en))))
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT8,T10,T25
11CoveredT1,T2,T12

 LINE       106
 SUB-EXPRESSION ((gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en) || ((!gen_combo_trigger[2].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------
-1--2-StatusTests
00CoveredT8,T10,T25
01CoveredT1,T4,T2
10CoveredT8,T10,T25

 LINE       106
 SUB-EXPRESSION (gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01CoveredT8,T10,T25
10Not Covered
11CoveredT8,T10,T25

 LINE       106
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[3].cfg_in_sel)) && 
      2  ((gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en) || ((!gen_combo_trigger[3].cfg_combo_pre_en))))
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT8,T10,T25
11CoveredT1,T2,T12

 LINE       106
 SUB-EXPRESSION ((gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en) || ((!gen_combo_trigger[3].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------
-1--2-StatusTests
00CoveredT8,T10,T25
01CoveredT1,T4,T2
10CoveredT10,T25,T38

 LINE       106
 SUB-EXPRESSION (gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01CoveredT8,T10,T25
10Not Covered
11CoveredT10,T25,T38

 LINE       111
 EXPRESSION ((in & gen_combo_trigger[0].cfg_in_sel) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T12
1CoveredT1,T4,T2

 LINE       111
 EXPRESSION ((in & gen_combo_trigger[1].cfg_in_sel) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T12
1CoveredT1,T4,T2

 LINE       111
 EXPRESSION ((in & gen_combo_trigger[2].cfg_in_sel) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T12
1CoveredT1,T4,T2

 LINE       111
 EXPRESSION ((in & gen_combo_trigger[3].cfg_in_sel) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T12
1CoveredT1,T4,T2
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%