Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T10,T25
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T10,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T10,T25

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T10,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T25
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T25
0	1	Covered	T40,T38,T69
1	0	Covered	T25,T38,T90

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T37
0	1	Covered	T8,T10,T37
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T10,T37
1	-	Covered	T8,T10,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T10,T25
DetectSt	168	Covered	T8,T10,T25
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T8,T10,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T10,T25
DebounceSt->IdleSt	163	Covered	T68,T234,T223
DetectSt->IdleSt	186	Covered	T25,T40,T38
DetectSt->StableSt	191	Covered	T8,T10,T37
IdleSt->DebounceSt	148	Covered	T8,T10,T25
StableSt->IdleSt	206	Covered	T8,T10,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T10,T25
0	1	Covered	T8,T10,T25
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T25
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T10,T25
IdleSt	0	-	-	-	-	-	-	Covered	T8,T10,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T10,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T68,T234,T223
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T10,T25
DetectSt	-	-	-	-	1	-	-	Covered	T25,T40,T38
DetectSt	-	-	-	-	0	1	-	Covered	T8,T10,T37
DetectSt	-	-	-	-	0	0	-	Covered	T8,T10,T25
StableSt	-	-	-	-	-	-	1	Covered	T8,T10,T37
StableSt	-	-	-	-	-	-	0	Covered	T8,T10,T37
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	3022	0	0
CntIncr_A	5765374	103291	0	0
CntNoWrap_A	5765374	5136228	0	0
DetectStDropOut_A	5765374	441	0	0
DetectedOut_A	5765374	77914	0	0
DetectedPulseOut_A	5765374	839	0	0
DisabledIdleSt_A	5765374	4641771	0	0
DisabledNoDetection_A	5765374	4643889	0	0
EnterDebounceSt_A	5765374	1530	0	0
EnterDetectSt_A	5765374	1492	0	0
EnterStableSt_A	5765374	839	0	0
PulseIsPulse_A	5765374	839	0	0
StayInStableSt	5765374	76990	0	0
gen_high_event_sva.HighLevelEvent_A	5765374	5141548	0	0
gen_high_level_sva.HighLevelEvent_A	5765374	5141548	0	0
gen_not_sticky_sva.StableStDropOut_A	5765374	753	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	3022	0	0
T8	12309	48	0	0
T9	481	0	0	0
T10	0	54	0	0
T22	493	0	0	0
T25	0	32	0	0
T37	0	26	0	0
T38	0	10	0	0
T39	17057	0	0	0
T40	0	32	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T68	0	19	0	0
T69	0	60	0	0
T70	0	22	0	0
T71	0	30	0	0
T72	404	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	103291	0	0
T8	12309	1200	0	0
T9	481	0	0	0
T10	0	702	0	0
T22	493	0	0	0
T25	0	4921	0	0
T37	0	975	0	0
T38	0	306	0	0
T39	17057	0	0	0
T40	0	873	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T68	0	722	0	0
T69	0	1262	0	0
T70	0	704	0	0
T71	0	635	0	0
T72	404	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5136228	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	441	0	0
T11	16145	0	0	0
T30	770	0	0	0
T38	0	1	0	0
T40	5366	16	0	0
T63	495	0	0	0
T66	502	0	0	0
T67	523	0	0	0
T69	0	30	0	0
T71	0	15	0	0
T90	0	5	0	0
T91	0	12	0	0
T92	0	11	0	0
T94	0	4	0	0
T95	0	14	0	0
T97	0	12	0	0
T235	550	0	0	0
T236	423	0	0	0
T237	422	0	0	0
T238	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	77914	0	0
T8	12309	1181	0	0
T9	481	0	0	0
T10	0	3258	0	0
T22	493	0	0	0
T37	0	1868	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T70	0	104	0	0
T72	404	0	0	0
T127	0	1999	0	0
T239	0	1134	0	0
T240	0	8783	0	0
T241	0	85	0	0
T242	0	831	0	0
T243	0	1360	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	839	0	0
T8	12309	24	0	0
T9	481	0	0	0
T10	0	27	0	0
T22	493	0	0	0
T37	0	13	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T70	0	11	0	0
T72	404	0	0	0
T127	0	26	0	0
T239	0	29	0	0
T240	0	22	0	0
T241	0	1	0	0
T242	0	22	0	0
T243	0	21	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4641771	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4643889	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	1530	0	0
T8	12309	24	0	0
T9	481	0	0	0
T10	0	27	0	0
T22	493	0	0	0
T25	0	16	0	0
T37	0	13	0	0
T38	0	5	0	0
T39	17057	0	0	0
T40	0	16	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T68	0	19	0	0
T69	0	30	0	0
T70	0	11	0	0
T71	0	15	0	0
T72	404	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	1492	0	0
T8	12309	24	0	0
T9	481	0	0	0
T10	0	27	0	0
T22	493	0	0	0
T25	0	16	0	0
T37	0	13	0	0
T38	0	5	0	0
T39	17057	0	0	0
T40	0	16	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T69	0	30	0	0
T70	0	11	0	0
T71	0	15	0	0
T72	404	0	0	0
T127	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	839	0	0
T8	12309	24	0	0
T9	481	0	0	0
T10	0	27	0	0
T22	493	0	0	0
T37	0	13	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T70	0	11	0	0
T72	404	0	0	0
T127	0	26	0	0
T239	0	29	0	0
T240	0	22	0	0
T241	0	1	0	0
T242	0	22	0	0
T243	0	21	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	839	0	0
T8	12309	24	0	0
T9	481	0	0	0
T10	0	27	0	0
T22	493	0	0	0
T37	0	13	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T70	0	11	0	0
T72	404	0	0	0
T127	0	26	0	0
T239	0	29	0	0
T240	0	22	0	0
T241	0	1	0	0
T242	0	22	0	0
T243	0	21	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	76990	0	0
T8	12309	1157	0	0
T9	481	0	0	0
T10	0	3223	0	0
T22	493	0	0	0
T37	0	1849	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T70	0	93	0	0
T72	404	0	0	0
T127	0	1971	0	0
T239	0	1105	0	0
T240	0	8757	0	0
T241	0	83	0	0
T242	0	809	0	0
T243	0	1339	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	753	0	0
T8	12309	24	0	0
T9	481	0	0	0
T10	0	19	0	0
T22	493	0	0	0
T37	0	7	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T70	0	11	0	0
T72	404	0	0	0
T127	0	24	0	0
T239	0	29	0	0
T240	0	18	0	0
T242	0	22	0	0
T243	0	21	0	0
T244	0	27	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T2,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T12
0	1	Covered	T2,T60,T27
1	0	Covered	T52,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T39
0	1	Covered	T1,T12,T39
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T12,T39
1	-	Covered	T1,T12,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T12
DetectSt	168	Covered	T1,T2,T12
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T12,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T12
DebounceSt->IdleSt	163	Covered	T12,T39,T86
DetectSt->IdleSt	186	Covered	T2,T60,T27
DetectSt->StableSt	191	Covered	T1,T12,T39
IdleSt->DebounceSt	148	Covered	T1,T2,T12
StableSt->IdleSt	206	Covered	T1,T12,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T12
0	1	Covered	T1,T2,T12
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T12
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T39,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T12
DetectSt	-	-	-	-	1	-	-	Covered	T2,T60,T27
DetectSt	-	-	-	-	0	1	-	Covered	T1,T12,T39
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T12
StableSt	-	-	-	-	-	-	1	Covered	T1,T12,T39
StableSt	-	-	-	-	-	-	0	Covered	T1,T12,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	956	0	0
CntIncr_A	5765374	52271	0	0
CntNoWrap_A	5765374	5138294	0	0
DetectStDropOut_A	5765374	74	0	0
DetectedOut_A	5765374	15497	0	0
DetectedPulseOut_A	5765374	362	0	0
DisabledIdleSt_A	5765374	4737868	0	0
DisabledNoDetection_A	5765374	4739389	0	0
EnterDebounceSt_A	5765374	518	0	0
EnterDetectSt_A	5765374	442	0	0
EnterStableSt_A	5765374	362	0	0
PulseIsPulse_A	5765374	362	0	0
StayInStableSt	5765374	15116	0	0
gen_high_level_sva.HighLevelEvent_A	5765374	5141548	0	0
gen_not_sticky_sva.StableStDropOut_A	5765374	341	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	956	0	0
T1	28795	14	0	0
T2	13420	2	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T9	0	2	0	0
T10	0	10	0	0
T11	0	2	0	0
T12	16327	5	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T39	0	9	0	0
T53	0	8	0	0
T86	0	14	0	0
T87	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	52271	0	0
T1	28795	924	0	0
T2	13420	45	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T9	0	25	0	0
T10	0	280	0	0
T11	0	101	0	0
T12	16327	226	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T39	0	726	0	0
T53	0	724	0	0
T86	0	1410	0	0
T87	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5138294	0	0
T1	28795	28299	0	0
T2	13420	7382	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15094	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	74	0	0
T2	13420	1	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T7	550	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T27	0	2	0	0
T28	0	2	0	0
T46	433	0	0	0
T60	0	4	0	0
T89	0	8	0	0
T93	0	1	0	0
T96	0	3	0	0
T98	0	4	0	0
T99	0	8	0	0
T100	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	15497	0	0
T1	28795	29	0	0
T2	13420	0	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T9	0	4	0	0
T10	0	401	0	0
T11	0	38	0	0
T12	16327	160	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T37	0	706	0	0
T39	0	13	0	0
T53	0	32	0	0
T86	0	39	0	0
T87	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	362	0	0
T1	28795	7	0	0
T2	13420	0	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T9	0	1	0	0
T10	0	5	0	0
T11	0	1	0	0
T12	16327	2	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T37	0	4	0	0
T39	0	3	0	0
T53	0	4	0	0
T86	0	6	0	0
T87	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4737868	0	0
T1	28795	24172	0	0
T2	13420	6281	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	12087	0	0
T12	16327	10076	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4739389	0	0
T1	28795	24172	0	0
T2	13420	6296	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	12087	0	0
T12	16327	10076	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	518	0	0
T1	28795	7	0	0
T2	13420	1	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T9	0	1	0	0
T10	0	5	0	0
T11	0	1	0	0
T12	16327	3	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T39	0	6	0	0
T53	0	4	0	0
T86	0	8	0	0
T87	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	442	0	0
T1	28795	7	0	0
T2	13420	1	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T9	0	1	0	0
T10	0	5	0	0
T11	0	1	0	0
T12	16327	2	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T39	0	3	0	0
T53	0	4	0	0
T86	0	6	0	0
T87	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	362	0	0
T1	28795	7	0	0
T2	13420	0	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T9	0	1	0	0
T10	0	5	0	0
T11	0	1	0	0
T12	16327	2	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T37	0	4	0	0
T39	0	3	0	0
T53	0	4	0	0
T86	0	6	0	0
T87	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	362	0	0
T1	28795	7	0	0
T2	13420	0	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T9	0	1	0	0
T10	0	5	0	0
T11	0	1	0	0
T12	16327	2	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T37	0	4	0	0
T39	0	3	0	0
T53	0	4	0	0
T86	0	6	0	0
T87	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	15116	0	0
T1	28795	22	0	0
T2	13420	0	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T9	0	3	0	0
T10	0	396	0	0
T11	0	37	0	0
T12	16327	158	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T37	0	702	0	0
T39	0	10	0	0
T53	0	28	0	0
T86	0	33	0	0
T87	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	341	0	0
T1	28795	7	0	0
T2	13420	0	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T9	0	1	0	0
T10	0	5	0	0
T11	0	1	0	0
T12	16327	2	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T37	0	4	0	0
T39	0	3	0	0
T53	0	4	0	0
T86	0	6	0	0
T87	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T10,T25
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T10,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T10,T25

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T10,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T25
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T25
0	1	Covered	T10,T40,T69
1	0	Covered	T10,T70,T245

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T25,T38
0	1	Covered	T8,T25,T38
1	0	Covered	T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T25,T38
1	-	Covered	T8,T25,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T10,T25
DetectSt	168	Covered	T8,T10,T25
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T8,T25,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T10,T25
DebounceSt->IdleSt	163	Covered	T68,T234,T223
DetectSt->IdleSt	186	Covered	T10,T40,T69
DetectSt->StableSt	191	Covered	T8,T25,T38
IdleSt->DebounceSt	148	Covered	T8,T10,T25
StableSt->IdleSt	206	Covered	T8,T25,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T10,T25
0	1	Covered	T8,T10,T25
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T25
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T10,T25
IdleSt	0	-	-	-	-	-	-	Covered	T8,T10,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T10,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T68,T234,T223
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T10,T25
DetectSt	-	-	-	-	1	-	-	Covered	T10,T40,T69
DetectSt	-	-	-	-	0	1	-	Covered	T8,T25,T38
DetectSt	-	-	-	-	0	0	-	Covered	T8,T10,T25
StableSt	-	-	-	-	-	-	1	Covered	T8,T25,T38
StableSt	-	-	-	-	-	-	0	Covered	T8,T25,T38
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	3884	0	0
CntIncr_A	5765374	135668	0	0
CntNoWrap_A	5765374	5135366	0	0
DetectStDropOut_A	5765374	645	0	0
DetectedOut_A	5765374	85903	0	0
DetectedPulseOut_A	5765374	947	0	0
DisabledIdleSt_A	5765374	4637615	0	0
DisabledNoDetection_A	5765374	4639712	0	0
EnterDebounceSt_A	5765374	1965	0	0
EnterDetectSt_A	5765374	1919	0	0
EnterStableSt_A	5765374	947	0	0
PulseIsPulse_A	5765374	947	0	0
StayInStableSt	5765374	84851	0	0
gen_high_event_sva.HighLevelEvent_A	5765374	5141548	0	0
gen_high_level_sva.HighLevelEvent_A	5765374	5141548	0	0
gen_not_sticky_sva.StableStDropOut_A	5765374	833	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	3884	0	0
T8	12309	30	0	0
T9	481	0	0	0
T10	0	18	0	0
T22	493	0	0	0
T25	0	42	0	0
T37	0	26	0	0
T38	0	34	0	0
T39	17057	0	0	0
T40	0	64	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T68	0	23	0	0
T69	0	46	0	0
T70	0	30	0	0
T71	0	20	0	0
T72	404	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	135668	0	0
T8	12309	585	0	0
T9	481	0	0	0
T10	0	440	0	0
T22	493	0	0	0
T25	0	4914	0	0
T37	0	832	0	0
T38	0	986	0	0
T39	17057	0	0	0
T40	0	1762	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T68	0	874	0	0
T69	0	968	0	0
T70	0	1077	0	0
T71	0	423	0	0
T72	404	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5135366	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	645	0	0
T10	23916	5	0	0
T11	16145	0	0	0
T25	25594	0	0	0
T40	5366	32	0	0
T61	496	0	0	0
T62	492	0	0	0
T69	0	23	0	0
T71	0	10	0	0
T91	0	17	0	0
T92	0	19	0	0
T94	0	8	0	0
T95	0	28	0	0
T235	550	0	0	0
T236	423	0	0	0
T237	422	0	0	0
T243	0	14	0	0
T245	0	10	0	0
T246	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	85903	0	0
T8	12309	4390	0	0
T9	481	0	0	0
T22	493	0	0	0
T25	0	2167	0	0
T37	0	2011	0	0
T38	0	1184	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T72	404	0	0	0
T90	0	1855	0	0
T127	0	415	0	0
T239	0	2068	0	0
T240	0	4651	0	0
T247	0	693	0	0
T248	0	1472	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	947	0	0
T8	12309	15	0	0
T9	481	0	0	0
T22	493	0	0	0
T25	0	21	0	0
T37	0	13	0	0
T38	0	17	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T72	404	0	0	0
T90	0	23	0	0
T127	0	11	0	0
T239	0	23	0	0
T240	0	12	0	0
T247	0	10	0	0
T248	0	29	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4637615	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4639712	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	1965	0	0
T8	12309	15	0	0
T9	481	0	0	0
T10	0	9	0	0
T22	493	0	0	0
T25	0	21	0	0
T37	0	13	0	0
T38	0	17	0	0
T39	17057	0	0	0
T40	0	32	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T68	0	23	0	0
T69	0	23	0	0
T70	0	15	0	0
T71	0	10	0	0
T72	404	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	1919	0	0
T8	12309	15	0	0
T9	481	0	0	0
T10	0	9	0	0
T22	493	0	0	0
T25	0	21	0	0
T37	0	13	0	0
T38	0	17	0	0
T39	17057	0	0	0
T40	0	32	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T69	0	23	0	0
T70	0	15	0	0
T71	0	10	0	0
T72	404	0	0	0
T127	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	947	0	0
T8	12309	15	0	0
T9	481	0	0	0
T22	493	0	0	0
T25	0	21	0	0
T37	0	13	0	0
T38	0	17	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T72	404	0	0	0
T90	0	23	0	0
T127	0	11	0	0
T239	0	23	0	0
T240	0	12	0	0
T247	0	10	0	0
T248	0	29	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	947	0	0
T8	12309	15	0	0
T9	481	0	0	0
T22	493	0	0	0
T25	0	21	0	0
T37	0	13	0	0
T38	0	17	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T72	404	0	0	0
T90	0	23	0	0
T127	0	11	0	0
T239	0	23	0	0
T240	0	12	0	0
T247	0	10	0	0
T248	0	29	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	84851	0	0
T8	12309	4374	0	0
T9	481	0	0	0
T22	493	0	0	0
T25	0	2146	0	0
T37	0	1992	0	0
T38	0	1164	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T72	404	0	0	0
T90	0	1830	0	0
T127	0	403	0	0
T239	0	2042	0	0
T240	0	4636	0	0
T247	0	683	0	0
T248	0	1440	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	833	0	0
T8	12309	14	0	0
T9	481	0	0	0
T22	493	0	0	0
T25	0	21	0	0
T37	0	7	0	0
T38	0	14	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T72	404	0	0	0
T90	0	21	0	0
T127	0	10	0	0
T239	0	20	0	0
T240	0	9	0	0
T247	0	10	0	0
T248	0	26	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T2,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T12
0	1	Covered	T249,T250,T93
1	0	Covered	T52,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T12
0	1	Covered	T1,T2,T12
1	0	Covered	T52,T74,T251

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T12
1	-	Covered	T1,T2,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T12
DetectSt	168	Covered	T1,T2,T12
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T2,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T12
DebounceSt->IdleSt	163	Covered	T12,T11,T86
DetectSt->IdleSt	186	Covered	T249,T250,T93
DetectSt->StableSt	191	Covered	T1,T2,T12
IdleSt->DebounceSt	148	Covered	T1,T2,T12
StableSt->IdleSt	206	Covered	T1,T2,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T12
0	1	Covered	T1,T2,T12
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T12
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T11,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T12
DetectSt	-	-	-	-	1	-	-	Covered	T249,T250,T93
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T12
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	1002	0	0
CntIncr_A	5765374	50304	0	0
CntNoWrap_A	5765374	5138248	0	0
DetectStDropOut_A	5765374	76	0	0
DetectedOut_A	5765374	17704	0	0
DetectedPulseOut_A	5765374	390	0	0
DisabledIdleSt_A	5765374	4732213	0	0
DisabledNoDetection_A	5765374	4733759	0	0
EnterDebounceSt_A	5765374	532	0	0
EnterDetectSt_A	5765374	470	0	0
EnterStableSt_A	5765374	390	0	0
PulseIsPulse_A	5765374	390	0	0
StayInStableSt	5765374	17292	0	0
gen_high_level_sva.HighLevelEvent_A	5765374	5141548	0	0
gen_not_sticky_sva.StableStDropOut_A	5765374	364	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	1002	0	0
T1	28795	12	0	0
T2	13420	2	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	10	0	0
T8	0	2	0	0
T11	0	9	0	0
T12	16327	12	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T38	0	10	0	0
T53	0	4	0	0
T60	0	6	0	0
T86	0	13	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	50304	0	0
T1	28795	414	0	0
T2	13420	24	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	470	0	0
T8	0	55	0	0
T11	0	499	0	0
T12	16327	688	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T38	0	210	0	0
T53	0	368	0	0
T60	0	198	0	0
T86	0	765	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5138248	0	0
T1	28795	28301	0	0
T2	13420	7382	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15467	0	0
T12	16327	15087	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	76	0	0
T44	9441	0	0	0
T45	24022	0	0	0
T55	729	0	0	0
T56	1106	0	0	0
T89	40692	0	0	0
T93	0	6	0	0
T98	0	12	0	0
T168	0	9	0	0
T249	21307	4	0	0
T250	0	5	0	0
T252	0	4	0	0
T253	0	1	0	0
T254	0	6	0	0
T255	0	6	0	0
T256	0	2	0	0
T257	507	0	0	0
T258	493	0	0	0
T259	522	0	0	0
T260	713	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	17704	0	0
T1	28795	408	0	0
T2	13420	19	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	98	0	0
T8	0	341	0	0
T11	0	124	0	0
T12	16327	362	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T38	0	427	0	0
T53	0	10	0	0
T60	0	129	0	0
T86	0	579	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	390	0	0
T1	28795	6	0	0
T2	13420	1	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	5	0	0
T8	0	1	0	0
T11	0	4	0	0
T12	16327	4	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T38	0	5	0	0
T53	0	2	0	0
T60	0	3	0	0
T86	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4732213	0	0
T1	28795	24172	0	0
T2	13420	6281	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	12087	0	0
T12	16327	10110	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4733759	0	0
T1	28795	24172	0	0
T2	13420	6296	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	12087	0	0
T12	16327	10111	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	532	0	0
T1	28795	6	0	0
T2	13420	1	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	5	0	0
T8	0	1	0	0
T11	0	5	0	0
T12	16327	8	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T38	0	5	0	0
T53	0	2	0	0
T60	0	3	0	0
T86	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	470	0	0
T1	28795	6	0	0
T2	13420	1	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	5	0	0
T8	0	1	0	0
T11	0	4	0	0
T12	16327	4	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T38	0	5	0	0
T53	0	2	0	0
T60	0	3	0	0
T86	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	390	0	0
T1	28795	6	0	0
T2	13420	1	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	5	0	0
T8	0	1	0	0
T11	0	4	0	0
T12	16327	4	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T38	0	5	0	0
T53	0	2	0	0
T60	0	3	0	0
T86	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	390	0	0
T1	28795	6	0	0
T2	13420	1	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	5	0	0
T8	0	1	0	0
T11	0	4	0	0
T12	16327	4	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T38	0	5	0	0
T53	0	2	0	0
T60	0	3	0	0
T86	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	17292	0	0
T1	28795	402	0	0
T2	13420	18	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	93	0	0
T8	0	340	0	0
T11	0	120	0	0
T12	16327	358	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T38	0	422	0	0
T53	0	8	0	0
T60	0	126	0	0
T86	0	573	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	364	0	0
T1	28795	6	0	0
T2	13420	1	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	5	0	0
T8	0	1	0	0
T11	0	4	0	0
T12	16327	4	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T38	0	5	0	0
T53	0	2	0	0
T60	0	3	0	0
T86	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T10,T25
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T10,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T10,T25

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T10,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T25
1	0	Covered	T8,T10,T25
1	1	Covered	T8,T10,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T25
0	1	Covered	T40,T69,T71
1	0	Covered	T70,T90,T244

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T25
0	1	Covered	T8,T10,T25
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T10,T25
1	-	Covered	T8,T10,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T10,T25
DetectSt	168	Covered	T8,T10,T25
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T8,T10,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T10,T25
DebounceSt->IdleSt	163	Covered	T68,T234,T223
DetectSt->IdleSt	186	Covered	T40,T69,T70
DetectSt->StableSt	191	Covered	T8,T10,T25
IdleSt->DebounceSt	148	Covered	T8,T10,T25
StableSt->IdleSt	206	Covered	T8,T10,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T10,T25
0	1	Covered	T8,T10,T25
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T25
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T10,T25
IdleSt	0	-	-	-	-	-	-	Covered	T8,T10,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T10,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T68,T234,T223
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T10,T25
DetectSt	-	-	-	-	1	-	-	Covered	T40,T69,T70
DetectSt	-	-	-	-	0	1	-	Covered	T8,T10,T25
DetectSt	-	-	-	-	0	0	-	Covered	T8,T10,T25
StableSt	-	-	-	-	-	-	1	Covered	T8,T10,T25
StableSt	-	-	-	-	-	-	0	Covered	T8,T10,T25
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	3311	0	0
CntIncr_A	5765374	113981	0	0
CntNoWrap_A	5765374	5135939	0	0
DetectStDropOut_A	5765374	496	0	0
DetectedOut_A	5765374	88736	0	0
DetectedPulseOut_A	5765374	998	0	0
DisabledIdleSt_A	5765374	4630074	0	0
DisabledNoDetection_A	5765374	4632174	0	0
EnterDebounceSt_A	5765374	1682	0	0
EnterDetectSt_A	5765374	1629	0	0
EnterStableSt_A	5765374	998	0	0
PulseIsPulse_A	5765374	998	0	0
StayInStableSt	5765374	87637	0	0
gen_high_event_sva.HighLevelEvent_A	5765374	5141548	0	0
gen_high_level_sva.HighLevelEvent_A	5765374	5141548	0	0
gen_not_sticky_sva.StableStDropOut_A	5765374	897	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	3311	0	0
T8	12309	50	0	0
T9	481	0	0	0
T10	0	28	0	0
T22	493	0	0	0
T25	0	54	0	0
T37	0	28	0	0
T38	0	42	0	0
T39	17057	0	0	0
T40	0	54	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T68	0	13	0	0
T69	0	32	0	0
T70	0	30	0	0
T71	0	40	0	0
T72	404	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	113981	0	0
T8	12309	1475	0	0
T9	481	0	0	0
T10	0	406	0	0
T22	493	0	0	0
T25	0	5886	0	0
T37	0	924	0	0
T38	0	1134	0	0
T39	17057	0	0	0
T40	0	1485	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T68	0	494	0	0
T69	0	666	0	0
T70	0	1077	0	0
T71	0	847	0	0
T72	404	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5135939	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	496	0	0
T11	16145	0	0	0
T30	770	0	0	0
T40	5366	27	0	0
T63	495	0	0	0
T66	502	0	0	0
T67	523	0	0	0
T69	0	16	0	0
T71	0	20	0	0
T91	0	8	0	0
T92	0	13	0	0
T94	0	25	0	0
T95	0	28	0	0
T97	0	24	0	0
T235	550	0	0	0
T236	423	0	0	0
T237	422	0	0	0
T238	402	0	0	0
T244	0	10	0	0
T261	0	17	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	88736	0	0
T8	12309	4168	0	0
T9	481	0	0	0
T10	0	1179	0	0
T22	493	0	0	0
T25	0	4192	0	0
T37	0	3857	0	0
T38	0	2070	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T72	404	0	0	0
T127	0	1642	0	0
T239	0	1518	0	0
T240	0	1095	0	0
T245	0	1855	0	0
T247	0	2551	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	998	0	0
T8	12309	25	0	0
T9	481	0	0	0
T10	0	14	0	0
T22	493	0	0	0
T25	0	27	0	0
T37	0	14	0	0
T38	0	21	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T72	404	0	0	0
T127	0	23	0	0
T239	0	21	0	0
T240	0	5	0	0
T245	0	12	0	0
T247	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4630074	0	0
T1	28795	28313	0	0
T2	13420	7384	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15477	0	0
T12	16327	15099	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4632174	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	1682	0	0
T8	12309	25	0	0
T9	481	0	0	0
T10	0	14	0	0
T22	493	0	0	0
T25	0	27	0	0
T37	0	14	0	0
T38	0	21	0	0
T39	17057	0	0	0
T40	0	27	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T68	0	13	0	0
T69	0	16	0	0
T70	0	15	0	0
T71	0	20	0	0
T72	404	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	1629	0	0
T8	12309	25	0	0
T9	481	0	0	0
T10	0	14	0	0
T22	493	0	0	0
T25	0	27	0	0
T37	0	14	0	0
T38	0	21	0	0
T39	17057	0	0	0
T40	0	27	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T69	0	16	0	0
T70	0	15	0	0
T71	0	20	0	0
T72	404	0	0	0
T127	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	998	0	0
T8	12309	25	0	0
T9	481	0	0	0
T10	0	14	0	0
T22	493	0	0	0
T25	0	27	0	0
T37	0	14	0	0
T38	0	21	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T72	404	0	0	0
T127	0	23	0	0
T239	0	21	0	0
T240	0	5	0	0
T245	0	12	0	0
T247	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	998	0	0
T8	12309	25	0	0
T9	481	0	0	0
T10	0	14	0	0
T22	493	0	0	0
T25	0	27	0	0
T37	0	14	0	0
T38	0	21	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T72	404	0	0	0
T127	0	23	0	0
T239	0	21	0	0
T240	0	5	0	0
T245	0	12	0	0
T247	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	87637	0	0
T8	12309	4142	0	0
T9	481	0	0	0
T10	0	1161	0	0
T22	493	0	0	0
T25	0	4165	0	0
T37	0	3837	0	0
T38	0	2040	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T72	404	0	0	0
T127	0	1617	0	0
T239	0	1495	0	0
T240	0	1090	0	0
T245	0	1840	0	0
T247	0	2525	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	897	0	0
T8	12309	24	0	0
T9	481	0	0	0
T10	0	10	0	0
T22	493	0	0	0
T25	0	27	0	0
T37	0	8	0	0
T38	0	12	0	0
T39	17057	0	0	0
T47	422	0	0	0
T48	527	0	0	0
T49	427	0	0	0
T50	501	0	0	0
T51	630	0	0	0
T72	404	0	0	0
T127	0	21	0	0
T239	0	19	0	0
T240	0	5	0	0
T245	0	9	0	0
T247	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T2,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T12
0	1	Covered	T1,T32,T45
1	0	Covered	T52,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T6
0	1	Covered	T2,T12,T6
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T12,T6
1	-	Covered	T2,T12,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T12
DetectSt	168	Covered	T1,T2,T12
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T2,T12,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T12
DebounceSt->IdleSt	163	Covered	T12,T39,T86
DetectSt->IdleSt	186	Covered	T1,T32,T45
DetectSt->StableSt	191	Covered	T2,T12,T6
IdleSt->DebounceSt	148	Covered	T1,T2,T12
StableSt->IdleSt	206	Covered	T2,T12,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T12
0	1	Covered	T1,T2,T12
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T12
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T39,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T12
DetectSt	-	-	-	-	1	-	-	Covered	T1,T32,T45
DetectSt	-	-	-	-	0	1	-	Covered	T2,T12,T6
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T12
StableSt	-	-	-	-	-	-	1	Covered	T2,T12,T6
StableSt	-	-	-	-	-	-	0	Covered	T2,T12,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5765374	888	0	0
CntIncr_A	5765374	47843	0	0
CntNoWrap_A	5765374	5138362	0	0
DetectStDropOut_A	5765374	55	0	0
DetectedOut_A	5765374	17394	0	0
DetectedPulseOut_A	5765374	363	0	0
DisabledIdleSt_A	5765374	4726043	0	0
DisabledNoDetection_A	5765374	4727605	0	0
EnterDebounceSt_A	5765374	466	0	0
EnterDetectSt_A	5765374	422	0	0
EnterStableSt_A	5765374	363	0	0
PulseIsPulse_A	5765374	363	0	0
StayInStableSt	5765374	17004	0	0
gen_high_level_sva.HighLevelEvent_A	5765374	5141548	0	0
gen_not_sticky_sva.StableStDropOut_A	5765374	334	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	888	0	0
T1	28795	12	0	0
T2	13420	2	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	10	0	0
T8	0	2	0	0
T10	0	6	0	0
T11	0	6	0	0
T12	16327	12	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T25	0	6	0	0
T39	0	5	0	0
T86	0	13	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	47843	0	0
T1	28795	819	0	0
T2	13420	33	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	510	0	0
T8	0	76	0	0
T10	0	237	0	0
T11	0	384	0	0
T12	16327	1028	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T25	0	702	0	0
T39	0	369	0	0
T86	0	885	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5138362	0	0
T1	28795	28301	0	0
T2	13420	7382	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	15467	0	0
T12	16327	15087	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	55	0	0
T1	28795	6	0	0
T2	13420	0	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	0	0	0
T12	16327	0	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T32	0	1	0	0
T45	0	3	0	0
T81	0	2	0	0
T89	0	5	0	0
T93	0	4	0	0
T134	0	1	0	0
T172	0	3	0	0
T262	0	3	0	0
T263	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	17394	0	0
T2	13420	10	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	58	0	0
T7	550	0	0	0
T8	0	320	0	0
T10	0	172	0	0
T11	0	35	0	0
T12	16327	22	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T25	0	143	0	0
T39	0	50	0	0
T46	433	0	0	0
T53	0	321	0	0
T86	0	459	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	363	0	0
T2	13420	1	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	5	0	0
T7	550	0	0	0
T8	0	1	0	0
T10	0	3	0	0
T11	0	3	0	0
T12	16327	4	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T25	0	3	0	0
T39	0	2	0	0
T46	433	0	0	0
T53	0	4	0	0
T86	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4726043	0	0
T1	28795	24172	0	0
T2	13420	6281	0	0
T3	628	227	0	0
T4	407	6	0	0
T5	566	165	0	0
T6	15908	12087	0	0
T12	16327	10110	0	0
T13	492	91	0	0
T14	522	121	0	0
T15	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	4727605	0	0
T1	28795	24172	0	0
T2	13420	6296	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	12087	0	0
T12	16327	10111	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	466	0	0
T1	28795	6	0	0
T2	13420	1	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	5	0	0
T8	0	1	0	0
T10	0	3	0	0
T11	0	3	0	0
T12	16327	8	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T25	0	3	0	0
T39	0	3	0	0
T86	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	422	0	0
T1	28795	6	0	0
T2	13420	1	0	0
T3	628	0	0	0
T4	407	0	0	0
T5	566	0	0	0
T6	15908	5	0	0
T8	0	1	0	0
T10	0	3	0	0
T11	0	3	0	0
T12	16327	4	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T25	0	3	0	0
T39	0	2	0	0
T86	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	363	0	0
T2	13420	1	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	5	0	0
T7	550	0	0	0
T8	0	1	0	0
T10	0	3	0	0
T11	0	3	0	0
T12	16327	4	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T25	0	3	0	0
T39	0	2	0	0
T46	433	0	0	0
T53	0	4	0	0
T86	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	363	0	0
T2	13420	1	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	5	0	0
T7	550	0	0	0
T8	0	1	0	0
T10	0	3	0	0
T11	0	3	0	0
T12	16327	4	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T25	0	3	0	0
T39	0	2	0	0
T46	433	0	0	0
T53	0	4	0	0
T86	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	17004	0	0
T2	13420	9	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	53	0	0
T7	550	0	0	0
T8	0	319	0	0
T10	0	169	0	0
T11	0	32	0	0
T12	16327	18	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T25	0	140	0	0
T39	0	48	0	0
T46	433	0	0	0
T53	0	317	0	0
T86	0	453	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	5141548	0	0
T1	28795	28325	0	0
T2	13420	7401	0	0
T3	628	228	0	0
T4	407	7	0	0
T5	566	166	0	0
T6	15908	15483	0	0
T12	16327	15105	0	0
T13	492	92	0	0
T14	522	122	0	0
T15	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5765374	334	0	0
T2	13420	1	0	0
T3	628	0	0	0
T5	566	0	0	0
T6	15908	5	0	0
T7	550	0	0	0
T8	0	1	0	0
T10	0	3	0	0
T11	0	3	0	0
T12	16327	4	0	0
T13	492	0	0	0
T14	522	0	0	0
T15	527	0	0	0
T25	0	3	0	0
T39	0	2	0	0
T46	433	0	0	0
T53	0	4	0	0
T86	0	6	0	0