Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T18,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T6,T18,T3

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T18,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T18,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T6,T18,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T18,T3
0	1	Covered	T84,T107,T108
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T18,T3
0	1	Covered	T6,T18,T3
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T18,T3
1	-	Covered	T6,T18,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T18,T3
DetectSt	168	Covered	T6,T18,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T6,T18,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T18,T3
DebounceSt->IdleSt	163	Covered	T47,T39,T95
DetectSt->IdleSt	186	Covered	T84,T107,T108
DetectSt->StableSt	191	Covered	T6,T18,T3
IdleSt->DebounceSt	148	Covered	T6,T18,T3
StableSt->IdleSt	206	Covered	T6,T18,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T18,T3
0	1	Covered	T6,T18,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T18,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T18,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T18,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T39,T95
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T18,T3
DetectSt	-	-	-	-	1	-	-	Covered	T84,T107,T108
DetectSt	-	-	-	-	0	1	-	Covered	T6,T18,T3
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T18,T3
StableSt	-	-	-	-	-	-	0	Covered	T6,T18,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	283	0	0
CntIncr_A	8751421	221377	0	0
CntNoWrap_A	8751421	8084596	0	0
DetectStDropOut_A	8751421	4	0	0
DetectedOut_A	8751421	945	0	0
DetectedPulseOut_A	8751421	123	0	0
DisabledIdleSt_A	8751421	7856678	0	0
DisabledNoDetection_A	8751421	7859076	0	0
EnterDebounceSt_A	8751421	158	0	0
EnterDetectSt_A	8751421	127	0	0
EnterStableSt_A	8751421	123	0	0
PulseIsPulse_A	8751421	123	0	0
StayInStableSt	8751421	822	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8751421	6972	0	0
gen_low_level_sva.LowLevelEvent_A	8751421	8087324	0	0
gen_not_sticky_sva.StableStDropOut_A	8751421	123	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	283	0	0
T1	18209	0	0	0
T2	6931	0	0	0
T3	0	2	0	0
T6	695	4	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	4	0	0
T21	422	0	0	0
T22	506	0	0	0
T28	0	2	0	0
T39	0	17	0	0
T46	0	2	0	0
T47	0	3	0	0
T49	0	4	0	0
T51	0	2	0	0
T95	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	221377	0	0
T1	18209	0	0	0
T2	6931	0	0	0
T3	0	17	0	0
T6	695	76	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	108	0	0
T21	422	0	0	0
T22	506	0	0	0
T28	0	82	0	0
T39	0	480	0	0
T46	0	32	0	0
T47	0	121	0	0
T49	0	84	0	0
T51	0	98	0	0
T95	0	153	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8084596	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	290	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	4	0	0
T44	1565	0	0	0
T84	682	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T113	26996	0	0	0
T114	6259	0	0	0
T115	509	0	0	0
T116	11074	0	0	0
T117	409	0	0	0
T118	505	0	0	0
T119	498	0	0	0
T120	418	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	945	0	0
T1	18209	0	0	0
T2	6931	0	0	0
T3	0	5	0	0
T6	695	16	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	12	0	0
T21	422	0	0	0
T22	506	0	0	0
T28	0	9	0	0
T39	0	56	0	0
T46	0	12	0	0
T47	0	5	0	0
T49	0	16	0	0
T51	0	8	0	0
T95	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	123	0	0
T1	18209	0	0	0
T2	6931	0	0	0
T3	0	1	0	0
T6	695	2	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	2	0	0
T21	422	0	0	0
T22	506	0	0	0
T28	0	1	0	0
T39	0	7	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T95	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7856678	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	119	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7859076	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	119	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	158	0	0
T1	18209	0	0	0
T2	6931	0	0	0
T3	0	1	0	0
T6	695	2	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	2	0	0
T21	422	0	0	0
T22	506	0	0	0
T28	0	1	0	0
T39	0	10	0	0
T46	0	1	0	0
T47	0	2	0	0
T49	0	2	0	0
T51	0	1	0	0
T95	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	127	0	0
T1	18209	0	0	0
T2	6931	0	0	0
T3	0	1	0	0
T6	695	2	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	2	0	0
T21	422	0	0	0
T22	506	0	0	0
T28	0	1	0	0
T39	0	7	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T95	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	123	0	0
T1	18209	0	0	0
T2	6931	0	0	0
T3	0	1	0	0
T6	695	2	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	2	0	0
T21	422	0	0	0
T22	506	0	0	0
T28	0	1	0	0
T39	0	7	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T95	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	123	0	0
T1	18209	0	0	0
T2	6931	0	0	0
T3	0	1	0	0
T6	695	2	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	2	0	0
T21	422	0	0	0
T22	506	0	0	0
T28	0	1	0	0
T39	0	7	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T95	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	822	0	0
T1	18209	0	0	0
T2	6931	0	0	0
T3	0	4	0	0
T6	695	14	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	10	0	0
T21	422	0	0	0
T22	506	0	0	0
T28	0	8	0	0
T39	0	49	0	0
T46	0	11	0	0
T47	0	4	0	0
T49	0	14	0	0
T51	0	7	0	0
T123	0	3	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	6972	0	0
T1	18209	29	0	0
T2	6931	27	0	0
T4	524	6	0	0
T5	503	6	0	0
T6	695	3	0	0
T14	19415	32	0	0
T15	968	0	0	0
T16	523	4	0	0
T17	0	26	0	0
T18	0	3	0	0
T21	422	0	0	0
T22	506	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	123	0	0
T1	18209	0	0	0
T2	6931	0	0	0
T3	0	1	0	0
T6	695	2	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	0	0	0
T17	5170	0	0	0
T18	708	2	0	0
T21	422	0	0	0
T22	506	0	0	0
T28	0	1	0	0
T39	0	7	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T95	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T59,T41,T76

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T27,T28
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T59,T41,T76
0	1	Covered	T91,T92,T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T59,T41,T76
0	1	Unreachable
1	0	Covered	T59,T41,T76

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T27,T28
DetectSt	168	Covered	T59,T41,T76
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T59,T41,T76

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T59,T41,T76
DebounceSt->IdleSt	163	Covered	T3,T27,T28
DetectSt->IdleSt	186	Covered	T91,T92,T93
DetectSt->StableSt	191	Covered	T59,T41,T76
IdleSt->DebounceSt	148	Covered	T3,T27,T28
StableSt->IdleSt	206	Covered	T59,T41,T76

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T27,T28
0	1	Covered	T3,T27,T28
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T59,T41,T76
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T59,T41,T76
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T27,T28
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T91,T92,T93
DetectSt	-	-	-	-	0	1	-	Covered	T59,T41,T76
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T59,T41,T76
StableSt	-	-	-	-	-	-	0	Covered	T59,T41,T76
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	156	0	0
CntIncr_A	8751421	241266	0	0
CntNoWrap_A	8751421	8084723	0	0
DetectStDropOut_A	8751421	6	0	0
DetectedOut_A	8751421	134946	0	0
DetectedPulseOut_A	8751421	45	0	0
DisabledIdleSt_A	8751421	6848141	0	0
DisabledNoDetection_A	8751421	6850584	0	0
EnterDebounceSt_A	8751421	106	0	0
EnterDetectSt_A	8751421	51	0	0
EnterStableSt_A	8751421	45	0	0
PulseIsPulse_A	8751421	45	0	0
StayInStableSt	8751421	134901	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8751421	6972	0	0
gen_low_level_sva.LowLevelEvent_A	8751421	8087324	0	0
gen_sticky_sva.StableStDropOut_A	8751421	173826	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	156	0	0
T3	173053	4	0	0
T7	9947	0	0	0
T20	438	0	0	0
T27	0	3	0	0
T28	0	5	0	0
T29	2070	0	0	0
T41	0	2	0	0
T45	438	0	0	0
T59	0	2	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T75	0	5	0	0
T76	0	2	0	0
T77	0	4	0	0
T78	0	2	0	0
T79	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	241266	0	0
T3	173053	153792	0	0
T7	9947	0	0	0
T20	438	0	0	0
T27	0	153	0	0
T28	0	170	0	0
T29	2070	0	0	0
T41	0	52	0	0
T45	438	0	0	0
T59	0	94	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T75	0	390	0	0
T76	0	74	0	0
T77	0	178	0	0
T78	0	49	0	0
T79	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8084723	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	6	0	0
T91	25790	1	0	0
T92	1531	2	0	0
T93	0	1	0	0
T106	27531	0	0	0
T136	0	2	0	0
T137	577	0	0	0
T138	391870	0	0	0
T139	18289	0	0	0
T140	20033	0	0	0
T141	522	0	0	0
T142	15271	0	0	0
T143	434	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	134946	0	0
T41	0	237	0	0
T59	1060	193	0	0
T76	0	244	0	0
T77	0	347	0	0
T78	0	37	0	0
T79	0	206	0	0
T95	700	0	0	0
T123	675	0	0	0
T125	0	288	0	0
T126	0	206	0	0
T127	0	370	0	0
T128	0	77	0	0
T144	525	0	0	0
T145	608	0	0	0
T146	504	0	0	0
T147	490	0	0	0
T148	492	0	0	0
T149	5884	0	0	0
T150	492	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	45	0	0
T41	0	1	0	0
T59	1060	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T95	700	0	0	0
T123	675	0	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	2	0	0
T128	0	1	0	0
T144	525	0	0	0
T145	608	0	0	0
T146	504	0	0	0
T147	490	0	0	0
T148	492	0	0	0
T149	5884	0	0	0
T150	492	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	6848141	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	6850584	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	106	0	0
T3	173053	4	0	0
T7	9947	0	0	0
T20	438	0	0	0
T27	0	3	0	0
T28	0	5	0	0
T29	2070	0	0	0
T41	0	1	0	0
T45	438	0	0	0
T59	0	1	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T75	0	5	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	51	0	0
T41	0	1	0	0
T59	1060	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T95	700	0	0	0
T123	675	0	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	2	0	0
T128	0	1	0	0
T144	525	0	0	0
T145	608	0	0	0
T146	504	0	0	0
T147	490	0	0	0
T148	492	0	0	0
T149	5884	0	0	0
T150	492	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	45	0	0
T41	0	1	0	0
T59	1060	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T95	700	0	0	0
T123	675	0	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	2	0	0
T128	0	1	0	0
T144	525	0	0	0
T145	608	0	0	0
T146	504	0	0	0
T147	490	0	0	0
T148	492	0	0	0
T149	5884	0	0	0
T150	492	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	45	0	0
T41	0	1	0	0
T59	1060	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0
T95	700	0	0	0
T123	675	0	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	2	0	0
T128	0	1	0	0
T144	525	0	0	0
T145	608	0	0	0
T146	504	0	0	0
T147	490	0	0	0
T148	492	0	0	0
T149	5884	0	0	0
T150	492	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	134901	0	0
T41	0	236	0	0
T59	1060	192	0	0
T76	0	243	0	0
T77	0	345	0	0
T78	0	36	0	0
T79	0	205	0	0
T95	700	0	0	0
T123	675	0	0	0
T125	0	287	0	0
T126	0	205	0	0
T127	0	368	0	0
T128	0	76	0	0
T144	525	0	0	0
T145	608	0	0	0
T146	504	0	0	0
T147	490	0	0	0
T148	492	0	0	0
T149	5884	0	0	0
T150	492	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	6972	0	0
T1	18209	29	0	0
T2	6931	27	0	0
T4	524	6	0	0
T5	503	6	0	0
T6	695	3	0	0
T14	19415	32	0	0
T15	968	0	0	0
T16	523	4	0	0
T17	0	26	0	0
T18	0	3	0	0
T21	422	0	0	0
T22	506	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	173826	0	0
T41	0	303	0	0
T59	1060	319	0	0
T76	0	87	0	0
T77	0	147	0	0
T78	0	114	0	0
T79	0	58	0	0
T95	700	0	0	0
T123	675	0	0	0
T125	0	166718	0	0
T126	0	334	0	0
T127	0	607	0	0
T128	0	25	0	0
T144	525	0	0	0
T145	608	0	0	0
T146	504	0	0	0
T147	490	0	0	0
T148	492	0	0	0
T149	5884	0	0	0
T150	492	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T22

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T22
1	1	Covered	T4,T5,T22

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T27,T28
1	0	Covered	T4,T5,T22
1	1	Covered	T3,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T27,T28
0	1	Covered	T89,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T27,T28
0	1	Unreachable
1	0	Covered	T3,T27,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T27,T28
DetectSt	168	Covered	T3,T27,T28
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T27,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T27,T28
DebounceSt->IdleSt	163	Covered	T77,T92,T151
DetectSt->IdleSt	186	Covered	T89,T90
DetectSt->StableSt	191	Covered	T3,T27,T28
IdleSt->DebounceSt	148	Covered	T3,T27,T28
StableSt->IdleSt	206	Covered	T3,T27,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T27,T28
0	1	Covered	T3,T27,T28
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T27,T28
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T22
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T77,T92,T151
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T89,T90
DetectSt	-	-	-	-	0	1	-	Covered	T3,T27,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T27,T28
StableSt	-	-	-	-	-	-	0	Covered	T3,T27,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	137	0	0
CntIncr_A	8751421	269152	0	0
CntNoWrap_A	8751421	8084742	0	0
DetectStDropOut_A	8751421	3	0	0
DetectedOut_A	8751421	279014	0	0
DetectedPulseOut_A	8751421	42	0	0
DisabledIdleSt_A	8751421	6848141	0	0
DisabledNoDetection_A	8751421	6850584	0	0
EnterDebounceSt_A	8751421	93	0	0
EnterDetectSt_A	8751421	45	0	0
EnterStableSt_A	8751421	42	0	0
PulseIsPulse_A	8751421	42	0	0
StayInStableSt	8751421	278972	0	0
gen_high_level_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_sticky_sva.StableStDropOut_A	8751421	571199	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	137	0	0
T3	173053	2	0	0
T7	9947	0	0	0
T20	438	0	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	2070	0	0	0
T41	0	2	0	0
T45	438	0	0	0
T59	0	2	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	3	0	0
T78	0	2	0	0
T79	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	269152	0	0
T3	173053	58	0	0
T7	9947	0	0	0
T20	438	0	0	0
T27	0	56	0	0
T28	0	45	0	0
T29	2070	0	0	0
T41	0	45	0	0
T45	438	0	0	0
T59	0	40	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T75	0	29201	0	0
T76	0	11	0	0
T77	0	171	0	0
T78	0	95	0	0
T79	0	79	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8084742	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	3	0	0
T89	24295	1	0	0
T90	0	2	0	0
T152	29775	0	0	0
T153	4118	0	0	0
T154	1110	0	0	0
T155	8402	0	0	0
T156	981	0	0	0
T157	2340	0	0	0
T158	2442	0	0	0
T159	1565	0	0	0
T160	420	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	279014	0	0
T3	173053	180	0	0
T7	9947	0	0	0
T20	438	0	0	0
T27	0	153	0	0
T28	0	209	0	0
T29	2070	0	0	0
T41	0	198	0	0
T45	438	0	0	0
T59	0	176	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T75	0	145115	0	0
T76	0	59	0	0
T78	0	71	0	0
T79	0	218	0	0
T101	0	417	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	42	0	0
T3	173053	1	0	0
T7	9947	0	0	0
T20	438	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	2070	0	0	0
T41	0	1	0	0
T45	438	0	0	0
T59	0	1	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T101	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	6848141	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	6850584	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	93	0	0
T3	173053	1	0	0
T7	9947	0	0	0
T20	438	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	2070	0	0	0
T41	0	1	0	0
T45	438	0	0	0
T59	0	1	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	3	0	0
T78	0	1	0	0
T79	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	45	0	0
T3	173053	1	0	0
T7	9947	0	0	0
T20	438	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	2070	0	0	0
T41	0	1	0	0
T45	438	0	0	0
T59	0	1	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T101	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	42	0	0
T3	173053	1	0	0
T7	9947	0	0	0
T20	438	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	2070	0	0	0
T41	0	1	0	0
T45	438	0	0	0
T59	0	1	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T101	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	42	0	0
T3	173053	1	0	0
T7	9947	0	0	0
T20	438	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	2070	0	0	0
T41	0	1	0	0
T45	438	0	0	0
T59	0	1	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T101	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	278972	0	0
T3	173053	179	0	0
T7	9947	0	0	0
T20	438	0	0	0
T27	0	152	0	0
T28	0	208	0	0
T29	2070	0	0	0
T41	0	197	0	0
T45	438	0	0	0
T59	0	175	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T75	0	145114	0	0
T76	0	58	0	0
T78	0	70	0	0
T79	0	217	0	0
T101	0	416	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	571199	0	0
T3	173053	153644	0	0
T7	9947	0	0	0
T20	438	0	0	0
T27	0	343	0	0
T28	0	117	0	0
T29	2070	0	0	0
T41	0	347	0	0
T45	438	0	0	0
T59	0	406	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T75	0	462	0	0
T76	0	345	0	0
T78	0	33	0	0
T79	0	57	0	0
T101	0	314324	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T22

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T27,T28
1	0	Covered	T4,T5,T22
1	1	Covered	T3,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T59
0	1	Covered	T3,T77,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T59
0	1	Unreachable
1	0	Covered	T27,T28,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T27,T28
DetectSt	168	Covered	T3,T27,T28
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T27,T28,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T27,T28
DebounceSt->IdleSt	163	Covered	T3,T75,T77
DetectSt->IdleSt	186	Covered	T3,T77,T78
DetectSt->StableSt	191	Covered	T27,T28,T59
IdleSt->DebounceSt	148	Covered	T3,T27,T28
StableSt->IdleSt	206	Covered	T27,T28,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T27,T28
0	1	Covered	T3,T27,T28
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T27,T28
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T22
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T75,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T3,T77,T78
DetectSt	-	-	-	-	0	1	-	Covered	T27,T28,T59
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T27,T28,T59
StableSt	-	-	-	-	-	-	0	Covered	T27,T28,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	170	0	0
CntIncr_A	8751421	257551	0	0
CntNoWrap_A	8751421	8084709	0	0
DetectStDropOut_A	8751421	22	0	0
DetectedOut_A	8751421	70679	0	0
DetectedPulseOut_A	8751421	45	0	0
DisabledIdleSt_A	8751421	6848141	0	0
DisabledNoDetection_A	8751421	6850584	0	0
EnterDebounceSt_A	8751421	104	0	0
EnterDetectSt_A	8751421	67	0	0
EnterStableSt_A	8751421	45	0	0
PulseIsPulse_A	8751421	45	0	0
StayInStableSt	8751421	70634	0	0
gen_high_event_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_high_level_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_sticky_sva.StableStDropOut_A	8751421	523568	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	170	0	0
T3	173053	7	0	0
T7	9947	0	0	0
T20	438	0	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	2070	0	0	0
T41	0	2	0	0
T45	438	0	0	0
T59	0	2	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T75	0	3	0	0
T76	0	2	0	0
T77	0	5	0	0
T78	0	2	0	0
T79	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	257551	0	0
T3	173053	216	0	0
T7	9947	0	0	0
T20	438	0	0	0
T27	0	87	0	0
T28	0	25	0	0
T29	2070	0	0	0
T41	0	87	0	0
T45	438	0	0	0
T59	0	98	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T75	0	60	0	0
T76	0	12	0	0
T77	0	141	0	0
T78	0	53	0	0
T79	0	34	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8084709	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	22	0	0
T3	173053	3	0	0
T7	9947	0	0	0
T20	438	0	0	0
T29	2070	0	0	0
T45	438	0	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T90	0	1	0	0
T101	0	3	0	0
T127	0	5	0	0
T161	0	4	0	0
T162	0	2	0	0
T163	0	1	0	0
T164	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	70679	0	0
T27	1006	401	0	0
T28	0	164	0	0
T32	723	0	0	0
T41	0	471	0	0
T56	1011	0	0	0
T59	0	488	0	0
T75	0	95	0	0
T76	0	69	0	0
T77	0	1	0	0
T79	0	51	0	0
T101	0	62948	0	0
T125	0	196	0	0
T129	879	0	0	0
T130	431	0	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	45	0	0
T27	1006	1	0	0
T28	0	1	0	0
T32	723	0	0	0
T41	0	1	0	0
T56	1011	0	0	0
T59	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0
T101	0	1	0	0
T125	0	1	0	0
T129	879	0	0	0
T130	431	0	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	6848141	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	6850584	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	104	0	0
T3	173053	4	0	0
T7	9947	0	0	0
T20	438	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	2070	0	0	0
T41	0	1	0	0
T45	438	0	0	0
T59	0	1	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	0	3	0	0
T78	0	1	0	0
T79	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	67	0	0
T3	173053	3	0	0
T7	9947	0	0	0
T20	438	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	2070	0	0	0
T41	0	1	0	0
T45	438	0	0	0
T59	0	1	0	0
T60	504	0	0	0
T61	503	0	0	0
T62	447	0	0	0
T63	501	0	0	0
T64	414	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	45	0	0
T27	1006	1	0	0
T28	0	1	0	0
T32	723	0	0	0
T41	0	1	0	0
T56	1011	0	0	0
T59	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0
T101	0	1	0	0
T125	0	1	0	0
T129	879	0	0	0
T130	431	0	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	45	0	0
T27	1006	1	0	0
T28	0	1	0	0
T32	723	0	0	0
T41	0	1	0	0
T56	1011	0	0	0
T59	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0
T101	0	1	0	0
T125	0	1	0	0
T129	879	0	0	0
T130	431	0	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	70634	0	0
T27	1006	400	0	0
T28	0	163	0	0
T32	723	0	0	0
T41	0	470	0	0
T56	1011	0	0	0
T59	0	487	0	0
T75	0	94	0	0
T76	0	68	0	0
T79	0	50	0	0
T101	0	62947	0	0
T125	0	195	0	0
T126	0	247	0	0
T129	879	0	0	0
T130	431	0	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	523568	0	0
T27	1006	82	0	0
T28	0	183	0	0
T32	723	0	0	0
T41	0	43	0	0
T56	1011	0	0	0
T59	0	39	0	0
T75	0	139715	0	0
T76	0	340	0	0
T77	0	185	0	0
T79	0	270	0	0
T101	0	42	0	0
T125	0	166817	0	0
T129	879	0	0	0
T130	431	0	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T42,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T32,T42,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T42,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T42,T38
1	0	Covered	T4,T5,T6
1	1	Covered	T32,T42,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T32,T42,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T32,T42,T38
0	1	Covered	T32,T37,T102
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T32,T42,T38
1	-	Covered	T32,T37,T102

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T42,T38
DetectSt	168	Covered	T32,T42,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T32,T42,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T32,T42,T38
DebounceSt->IdleSt	163	Covered	T36,T165,T166
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T32,T42,T38
IdleSt->DebounceSt	148	Covered	T32,T42,T38
StableSt->IdleSt	206	Covered	T32,T36,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T32,T42,T38
0	1	Covered	T32,T42,T38
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T32,T42,T38
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T42,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T32,T42,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T165,T166
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T42,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T32,T42,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T37,T102
StableSt	-	-	-	-	-	-	0	Covered	T32,T42,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	92	0	0
CntIncr_A	8751421	79617	0	0
CntNoWrap_A	8751421	8084787	0	0
DetectStDropOut_A	8751421	0	0	0
DetectedOut_A	8751421	26212	0	0
DetectedPulseOut_A	8751421	43	0	0
DisabledIdleSt_A	8751421	7563197	0	0
DisabledNoDetection_A	8751421	7565580	0	0
EnterDebounceSt_A	8751421	49	0	0
EnterDetectSt_A	8751421	43	0	0
EnterStableSt_A	8751421	43	0	0
PulseIsPulse_A	8751421	43	0	0
StayInStableSt	8751421	26146	0	0
gen_high_level_sva.HighLevelEvent_A	8751421	8087324	0	0
gen_not_sticky_sva.StableStDropOut_A	8751421	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	92	0	0
T32	723	2	0	0
T34	32992	0	0	0
T36	0	5	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	3069	0	0	0
T42	0	2	0	0
T44	0	2	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T102	0	4	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	79617	0	0
T32	723	62	0	0
T34	32992	0	0	0
T36	0	32	0	0
T37	0	34	0	0
T38	0	16	0	0
T40	3069	0	0	0
T42	0	61	0	0
T44	0	36	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T102	0	48	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T167	0	89	0	0
T168	0	61	0	0
T169	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8084787	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	26212	0	0
T32	723	6	0	0
T34	32992	0	0	0
T36	0	107	0	0
T37	0	76	0	0
T38	0	134	0	0
T40	3069	0	0	0
T42	0	38	0	0
T44	0	91	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T102	0	196	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T167	0	259	0	0
T168	0	43	0	0
T169	0	20	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	43	0	0
T32	723	1	0	0
T34	32992	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	3069	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T102	0	2	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7563197	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7565580	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	49	0	0
T32	723	1	0	0
T34	32992	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	3069	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T102	0	2	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	43	0	0
T32	723	1	0	0
T34	32992	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	3069	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T102	0	2	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	43	0	0
T32	723	1	0	0
T34	32992	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	3069	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T102	0	2	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	43	0	0
T32	723	1	0	0
T34	32992	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	3069	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T102	0	2	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	26146	0	0
T32	723	5	0	0
T34	32992	0	0	0
T36	0	103	0	0
T37	0	75	0	0
T38	0	132	0	0
T40	3069	0	0	0
T42	0	36	0	0
T44	0	89	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T102	0	193	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T167	0	257	0	0
T168	0	41	0	0
T169	0	19	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	20	0	0
T32	723	1	0	0
T34	32992	0	0	0
T37	0	1	0	0
T40	3069	0	0	0
T48	5266	0	0	0
T56	1011	0	0	0
T88	0	1	0	0
T89	0	2	0	0
T102	0	1	0	0
T131	505	0	0	0
T132	17911	0	0	0
T133	503	0	0	0
T134	421	0	0	0
T135	447	0	0	0
T166	0	1	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T40,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T40,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T40,T39,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T38,T39
1	0	Covered	T4,T5,T22
1	1	Covered	T40,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T39,T35
0	1	Covered	T85,T170
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T39,T35
0	1	Covered	T40,T39,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T39,T35
1	-	Covered	T40,T39,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T38,T39
DetectSt	168	Covered	T40,T39,T35
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T40,T39,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T39,T35
DebounceSt->IdleSt	163	Covered	T38,T82,T173
DetectSt->IdleSt	186	Covered	T85,T170
DetectSt->StableSt	191	Covered	T40,T39,T35
IdleSt->DebounceSt	148	Covered	T40,T38,T39
StableSt->IdleSt	206	Covered	T40,T39,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T38,T39
0	1	Covered	T40,T38,T39
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T39,T35
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T39,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T173
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T38,T39
DetectSt	-	-	-	-	1	-	-	Covered	T85,T170
DetectSt	-	-	-	-	0	1	-	Covered	T40,T39,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T39,T36
StableSt	-	-	-	-	-	-	0	Covered	T40,T39,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8751421	132	0	0
CntIncr_A	8751421	351964	0	0
CntNoWrap_A	8751421	8084747	0	0
DetectStDropOut_A	8751421	2	0	0
DetectedOut_A	8751421	261045	0	0
DetectedPulseOut_A	8751421	62	0	0
DisabledIdleSt_A	8751421	7142088	0	0
DisabledNoDetection_A	8751421	7144486	0	0
EnterDebounceSt_A	8751421	69	0	0
EnterDetectSt_A	8751421	64	0	0
EnterStableSt_A	8751421	62	0	0
PulseIsPulse_A	8751421	62	0	0
StayInStableSt	8751421	260957	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8751421	2726	0	0
gen_low_level_sva.LowLevelEvent_A	8751421	8087324	0	0
gen_not_sticky_sva.StableStDropOut_A	8751421	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	132	0	0
T34	32992	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	4	0	0
T40	3069	2	0	0
T42	570	0	0	0
T44	0	2	0	0
T48	5266	0	0	0
T57	912	0	0	0
T65	490	0	0	0
T66	503	0	0	0
T73	6308	0	0	0
T80	3888	0	0	0
T96	1573	0	0	0
T167	0	2	0	0
T169	0	4	0	0
T174	0	2	0	0
T175	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	351964	0	0
T34	32992	0	0	0
T35	0	32	0	0
T36	0	12	0	0
T38	0	16	0	0
T39	0	130	0	0
T40	3069	82	0	0
T42	570	0	0	0
T44	0	36	0	0
T48	5266	0	0	0
T57	912	0	0	0
T65	490	0	0	0
T66	503	0	0	0
T73	6308	0	0	0
T80	3888	0	0	0
T96	1573	0	0	0
T167	0	89	0	0
T169	0	94	0	0
T174	0	59	0	0
T175	0	86	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8084747	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	2	0	0
T85	545	1	0	0
T88	975	0	0	0
T170	0	1	0	0
T176	8899	0	0	0
T177	10939	0	0	0
T178	1349	0	0	0
T179	6016	0	0	0
T180	691	0	0	0
T181	720	0	0	0
T182	544	0	0	0
T183	12320	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	261045	0	0
T34	32992	0	0	0
T35	0	60	0	0
T36	0	68	0	0
T39	0	89	0	0
T40	3069	187	0	0
T42	570	0	0	0
T44	0	76	0	0
T48	5266	0	0	0
T57	912	0	0	0
T65	490	0	0	0
T66	503	0	0	0
T73	6308	0	0	0
T80	3888	0	0	0
T96	1573	0	0	0
T167	0	36	0	0
T169	0	84	0	0
T174	0	115	0	0
T175	0	318	0	0
T184	0	16	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	62	0	0
T34	32992	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	2	0	0
T40	3069	1	0	0
T42	570	0	0	0
T44	0	1	0	0
T48	5266	0	0	0
T57	912	0	0	0
T65	490	0	0	0
T66	503	0	0	0
T73	6308	0	0	0
T80	3888	0	0	0
T96	1573	0	0	0
T167	0	1	0	0
T169	0	2	0	0
T174	0	1	0	0
T175	0	1	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7142088	0	0
T1	18209	17780	0	0
T2	6931	6530	0	0
T4	524	123	0	0
T5	503	102	0	0
T6	695	294	0	0
T14	19415	18983	0	0
T15	968	567	0	0
T16	523	122	0	0
T21	422	21	0	0
T22	506	105	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	7144486	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	69	0	0
T34	32992	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	3069	1	0	0
T42	570	0	0	0
T44	0	1	0	0
T48	5266	0	0	0
T57	912	0	0	0
T65	490	0	0	0
T66	503	0	0	0
T73	6308	0	0	0
T80	3888	0	0	0
T96	1573	0	0	0
T167	0	1	0	0
T169	0	2	0	0
T174	0	1	0	0
T175	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	64	0	0
T34	32992	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	2	0	0
T40	3069	1	0	0
T42	570	0	0	0
T44	0	1	0	0
T48	5266	0	0	0
T57	912	0	0	0
T65	490	0	0	0
T66	503	0	0	0
T73	6308	0	0	0
T80	3888	0	0	0
T96	1573	0	0	0
T167	0	1	0	0
T169	0	2	0	0
T174	0	1	0	0
T175	0	1	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	62	0	0
T34	32992	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	2	0	0
T40	3069	1	0	0
T42	570	0	0	0
T44	0	1	0	0
T48	5266	0	0	0
T57	912	0	0	0
T65	490	0	0	0
T66	503	0	0	0
T73	6308	0	0	0
T80	3888	0	0	0
T96	1573	0	0	0
T167	0	1	0	0
T169	0	2	0	0
T174	0	1	0	0
T175	0	1	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	62	0	0
T34	32992	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	2	0	0
T40	3069	1	0	0
T42	570	0	0	0
T44	0	1	0	0
T48	5266	0	0	0
T57	912	0	0	0
T65	490	0	0	0
T66	503	0	0	0
T73	6308	0	0	0
T80	3888	0	0	0
T96	1573	0	0	0
T167	0	1	0	0
T169	0	2	0	0
T174	0	1	0	0
T175	0	1	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	260957	0	0
T34	32992	0	0	0
T35	0	58	0	0
T36	0	67	0	0
T39	0	86	0	0
T40	3069	186	0	0
T42	570	0	0	0
T44	0	75	0	0
T48	5266	0	0	0
T57	912	0	0	0
T65	490	0	0	0
T66	503	0	0	0
T73	6308	0	0	0
T80	3888	0	0	0
T96	1573	0	0	0
T167	0	35	0	0
T169	0	81	0	0
T174	0	113	0	0
T175	0	317	0	0
T184	0	15	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	2726	0	0
T1	18209	0	0	0
T2	6931	0	0	0
T4	524	3	0	0
T5	503	6	0	0
T6	695	0	0	0
T14	19415	0	0	0
T15	968	0	0	0
T16	523	4	0	0
T20	0	3	0	0
T21	422	0	0	0
T22	506	6	0	0
T29	0	9	0	0
T60	0	5	0	0
T61	0	3	0	0
T62	0	6	0	0
T63	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	8087324	0	0
T1	18209	17785	0	0
T2	6931	6531	0	0
T4	524	124	0	0
T5	503	103	0	0
T6	695	295	0	0
T14	19415	18988	0	0
T15	968	568	0	0
T16	523	123	0	0
T21	422	22	0	0
T22	506	106	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8751421	36	0	0
T34	32992	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	3069	1	0	0
T42	570	0	0	0
T44	0	1	0	0
T48	5266	0	0	0
T57	912	0	0	0
T65	490	0	0	0
T66	503	0	0	0
T73	6308	0	0	0
T80	3888	0	0	0
T85	0	1	0	0
T88	0	1	0	0
T96	1573	0	0	0
T167	0	1	0	0
T169	0	1	0	0
T175	0	1	0	0
T184	0	1	0	0