Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T2
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T2
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T30,T31,T52

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T30,T31,T52

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T30,T31,T52

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T52
1	0	Covered	T5,T6,T2
1	1	Covered	T30,T31,T52

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T52
0	1	Covered	T109,T111
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T52
0	1	Covered	T30,T31,T52
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T31,T52
1	-	Covered	T30,T31,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T30,T31,T52
DetectSt	168	Covered	T30,T31,T52
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T30,T31,T52

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T30,T31,T52
DebounceSt->IdleSt	163	Covered	T70,T62,T135
DetectSt->IdleSt	186	Covered	T109,T111
DetectSt->StableSt	191	Covered	T30,T31,T52
IdleSt->DebounceSt	148	Covered	T30,T31,T52
StableSt->IdleSt	206	Covered	T30,T31,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T30,T31,T52
0	1	Covered	T30,T31,T52
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T52
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T30,T31,T52
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T30,T31,T52
DebounceSt	-	0	1	0	-	-	-	Covered	T70,T135,T136
DebounceSt	-	0	0	-	-	-	-	Covered	T30,T31,T52
DetectSt	-	-	-	-	1	-	-	Covered	T109,T111
DetectSt	-	-	-	-	0	1	-	Covered	T30,T31,T52
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T31,T52
StableSt	-	-	-	-	-	-	0	Covered	T30,T31,T52
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	306	0	0
CntIncr_A	8194048	176612	0	0
CntNoWrap_A	8194048	7548599	0	0
DetectStDropOut_A	8194048	2	0	0
DetectedOut_A	8194048	940	0	0
DetectedPulseOut_A	8194048	141	0	0
DisabledIdleSt_A	8194048	7364999	0	0
DisabledNoDetection_A	8194048	7367343	0	0
EnterDebounceSt_A	8194048	168	0	0
EnterDetectSt_A	8194048	143	0	0
EnterStableSt_A	8194048	141	0	0
PulseIsPulse_A	8194048	141	0	0
StayInStableSt	8194048	799	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8194048	6970	0	0
gen_low_level_sva.LowLevelEvent_A	8194048	7551311	0	0
gen_not_sticky_sva.StableStDropOut_A	8194048	140	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	306	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T30	593	6	0	0
T31	38205	4	0	0
T50	0	4	0	0
T51	26891	0	0	0
T52	0	4	0	0
T53	0	4	0	0
T54	0	4	0	0
T55	0	4	0	0
T56	0	2	0	0
T57	0	4	0	0
T58	0	2	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	176612	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T30	593	56	0	0
T31	38205	37605	0	0
T50	0	59	0	0
T51	26891	0	0	0
T52	0	115	0	0
T53	0	81	0	0
T54	0	156	0	0
T55	0	22524	0	0
T56	0	38	0	0
T57	0	68	0	0
T58	0	62	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548599	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	2	0	0
T109	718	1	0	0
T111	0	1	0	0
T119	402	0	0	0
T120	21165	0	0	0
T121	9623	0	0	0
T122	492	0	0	0
T123	4768	0	0	0
T124	2046	0	0	0
T125	427	0	0	0
T126	493	0	0	0
T127	440	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	940	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T30	593	14	0	0
T31	38205	8	0	0
T50	0	8	0	0
T51	26891	0	0	0
T52	0	14	0	0
T53	0	8	0	0
T54	0	13	0	0
T55	0	13	0	0
T56	0	10	0	0
T57	0	15	0	0
T58	0	10	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	141	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T30	593	3	0	0
T31	38205	2	0	0
T50	0	2	0	0
T51	26891	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7364999	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7367343	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	168	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T30	593	3	0	0
T31	38205	2	0	0
T50	0	2	0	0
T51	26891	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	143	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T30	593	3	0	0
T31	38205	2	0	0
T50	0	2	0	0
T51	26891	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	141	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T30	593	3	0	0
T31	38205	2	0	0
T50	0	2	0	0
T51	26891	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	141	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T30	593	3	0	0
T31	38205	2	0	0
T50	0	2	0	0
T51	26891	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	799	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T30	593	11	0	0
T31	38205	6	0	0
T50	0	6	0	0
T51	26891	0	0	0
T52	0	12	0	0
T53	0	6	0	0
T54	0	11	0	0
T55	0	11	0	0
T56	0	9	0	0
T57	0	13	0	0
T58	0	9	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	6970	0	0
T1	509	0	0	0
T2	1112	1	0	0
T3	0	31	0	0
T4	0	1	0	0
T5	501	5	0	0
T6	502	3	0	0
T7	404	0	0	0
T9	0	15	0	0
T14	969	0	0	0
T15	670	0	0	0
T16	402	0	0	0
T17	15312	37	0	0
T18	407	0	0	0
T20	0	1	0	0
T25	0	7	0	0
T27	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	140	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T30	593	3	0	0
T31	38205	2	0	0
T50	0	2	0	0
T51	26891	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T2
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T2
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T11,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T9,T11,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T11,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T24
1	0	Covered	T5,T6,T2
1	1	Covered	T9,T11,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T24
0	1	Covered	T56,T95,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T24
0	1	Unreachable
1	0	Covered	T9,T11,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T11,T24
DetectSt	168	Covered	T9,T11,T24
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T9,T11,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T24
DebounceSt->IdleSt	163	Covered	T66,T67,T50
DetectSt->IdleSt	186	Covered	T56,T95,T96
DetectSt->StableSt	191	Covered	T9,T11,T24
IdleSt->DebounceSt	148	Covered	T9,T11,T24
StableSt->IdleSt	206	Covered	T9,T11,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T11,T24
0	1	Covered	T9,T11,T24
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T24
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T11,T24
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T66,T67,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T11,T24
DetectSt	-	-	-	-	1	-	-	Covered	T56,T95,T96
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T11,T24
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	194	0	0
CntIncr_A	8194048	272976	0	0
CntNoWrap_A	8194048	7548711	0	0
DetectStDropOut_A	8194048	10	0	0
DetectedOut_A	8194048	975368	0	0
DetectedPulseOut_A	8194048	56	0	0
DisabledIdleSt_A	8194048	5479245	0	0
DisabledNoDetection_A	8194048	5481650	0	0
EnterDebounceSt_A	8194048	128	0	0
EnterDetectSt_A	8194048	66	0	0
EnterStableSt_A	8194048	56	0	0
PulseIsPulse_A	8194048	56	0	0
StayInStableSt	8194048	975312	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8194048	6970	0	0
gen_low_level_sva.LowLevelEvent_A	8194048	7551311	0	0
gen_sticky_sva.StableStDropOut_A	8194048	658523	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	194	0	0
T9	710855	4	0	0
T10	17295	0	0	0
T11	1454	2	0	0
T12	504	0	0	0
T24	0	2	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T50	0	7	0	0
T56	0	6	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	2	0	0
T84	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	272976	0	0
T9	710855	49198	0	0
T10	17295	0	0	0
T11	1454	98	0	0
T12	504	0	0	0
T24	0	83	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T50	0	273	0	0
T56	0	200	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	81	0	0
T66	0	97	0	0
T67	0	71	0	0
T68	0	78	0	0
T84	0	184	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548711	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	10	0	0
T56	14199	1	0	0
T57	688	0	0	0
T82	16890	0	0	0
T91	0	2	0	0
T95	0	2	0	0
T96	0	4	0	0
T115	8402	0	0	0
T116	421	0	0	0
T117	510	0	0	0
T118	771	0	0	0
T137	0	1	0	0
T138	673	0	0	0
T139	513	0	0	0
T140	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	975368	0	0
T9	710855	423782	0	0
T10	17295	0	0	0
T11	1454	816	0	0
T12	504	0	0	0
T24	0	47	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T50	0	35	0	0
T56	0	504	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T68	0	6	0	0
T93	0	438	0	0
T129	0	833	0	0
T130	0	281	0	0
T131	0	255	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	56	0	0
T9	710855	2	0	0
T10	17295	0	0	0
T11	1454	1	0	0
T12	504	0	0	0
T24	0	1	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T50	0	1	0	0
T56	0	2	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T68	0	1	0	0
T93	0	1	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	5479245	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	5481650	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	128	0	0
T9	710855	2	0	0
T10	17295	0	0	0
T11	1454	1	0	0
T12	504	0	0	0
T24	0	1	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T50	0	6	0	0
T56	0	3	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T84	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	66	0	0
T9	710855	2	0	0
T10	17295	0	0	0
T11	1454	1	0	0
T12	504	0	0	0
T24	0	1	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T50	0	1	0	0
T56	0	3	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T68	0	1	0	0
T93	0	1	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	56	0	0
T9	710855	2	0	0
T10	17295	0	0	0
T11	1454	1	0	0
T12	504	0	0	0
T24	0	1	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T50	0	1	0	0
T56	0	2	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T68	0	1	0	0
T93	0	1	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	56	0	0
T9	710855	2	0	0
T10	17295	0	0	0
T11	1454	1	0	0
T12	504	0	0	0
T24	0	1	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T50	0	1	0	0
T56	0	2	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T68	0	1	0	0
T93	0	1	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	975312	0	0
T9	710855	423780	0	0
T10	17295	0	0	0
T11	1454	815	0	0
T12	504	0	0	0
T24	0	46	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T50	0	34	0	0
T56	0	502	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T68	0	5	0	0
T93	0	437	0	0
T129	0	831	0	0
T130	0	280	0	0
T131	0	254	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	6970	0	0
T1	509	0	0	0
T2	1112	1	0	0
T3	0	31	0	0
T4	0	1	0	0
T5	501	5	0	0
T6	502	3	0	0
T7	404	0	0	0
T9	0	15	0	0
T14	969	0	0	0
T15	670	0	0	0
T16	402	0	0	0
T17	15312	37	0	0
T18	407	0	0	0
T20	0	1	0	0
T25	0	7	0	0
T27	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	658523	0	0
T9	710855	599	0	0
T10	17295	0	0	0
T11	1454	88	0	0
T12	504	0	0	0
T24	0	28	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T50	0	37	0	0
T56	0	325	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T68	0	36	0	0
T93	0	181	0	0
T129	0	166	0	0
T130	0	273	0	0
T131	0	206	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T2
1	1	Covered	T5,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T11,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T9,T11,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T11,T66,T67

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T24
1	0	Covered	T5,T6,T2
1	1	Covered	T9,T11,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T66,T67
0	1	Covered	T50,T93,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T66,T67
0	1	Unreachable
1	0	Covered	T11,T66,T67

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T11,T24
DetectSt	168	Covered	T11,T66,T67
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T11,T66,T67

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T66,T67
DebounceSt->IdleSt	163	Covered	T9,T24,T56
DetectSt->IdleSt	186	Covered	T50,T93,T94
DetectSt->StableSt	191	Covered	T11,T66,T67
IdleSt->DebounceSt	148	Covered	T9,T11,T24
StableSt->IdleSt	206	Covered	T11,T66,T67

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T11,T24
0	1	Covered	T9,T11,T24
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T66,T67
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T11,T24
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T66,T67
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T24,T56
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T11,T24
DetectSt	-	-	-	-	1	-	-	Covered	T50,T93,T94
DetectSt	-	-	-	-	0	1	-	Covered	T11,T66,T67
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T66,T67
StableSt	-	-	-	-	-	-	0	Covered	T11,T66,T67
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	209	0	0
CntIncr_A	8194048	181274	0	0
CntNoWrap_A	8194048	7548696	0	0
DetectStDropOut_A	8194048	21	0	0
DetectedOut_A	8194048	10235	0	0
DetectedPulseOut_A	8194048	51	0	0
DisabledIdleSt_A	8194048	5479245	0	0
DisabledNoDetection_A	8194048	5481650	0	0
EnterDebounceSt_A	8194048	137	0	0
EnterDetectSt_A	8194048	72	0	0
EnterStableSt_A	8194048	51	0	0
PulseIsPulse_A	8194048	51	0	0
StayInStableSt	8194048	10184	0	0
gen_high_level_sva.HighLevelEvent_A	8194048	7551311	0	0
gen_sticky_sva.StableStDropOut_A	8194048	889562	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	209	0	0
T9	710855	10	0	0
T10	17295	0	0	0
T11	1454	2	0	0
T12	504	0	0	0
T24	0	1	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T50	0	7	0	0
T56	0	7	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	2	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	1	0	0
T84	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	181274	0	0
T9	710855	790	0	0
T10	17295	0	0	0
T11	1454	37	0	0
T12	504	0	0	0
T24	0	69	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T50	0	223	0	0
T56	0	312	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	82	0	0
T66	0	77	0	0
T67	0	70	0	0
T68	0	21	0	0
T84	0	49	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548696	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	21	0	0
T50	180438	1	0	0
T74	6354	0	0	0
T91	0	1	0	0
T93	0	2	0	0
T94	0	1	0	0
T97	5168	0	0	0
T141	0	5	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	3	0	0
T145	0	1	0	0
T146	0	4	0	0
T147	509	0	0	0
T148	29272	0	0	0
T149	422	0	0	0
T150	732	0	0	0
T151	426	0	0	0
T152	21158	0	0	0
T153	8084	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	10235	0	0
T11	1454	284	0	0
T12	504	0	0	0
T26	491	0	0	0
T31	38205	0	0	0
T51	26891	0	0	0
T56	0	285	0	0
T60	425	0	0	0
T61	422	0	0	0
T66	0	38	0	0
T67	0	47	0	0
T75	502	0	0	0
T84	0	271	0	0
T93	0	146	0	0
T94	0	312	0	0
T128	404	0	0	0
T129	0	379	0	0
T130	0	416	0	0
T131	0	342	0	0
T134	447	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	51	0	0
T11	1454	1	0	0
T12	504	0	0	0
T26	491	0	0	0
T31	38205	0	0	0
T51	26891	0	0	0
T56	0	1	0	0
T60	425	0	0	0
T61	422	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T75	502	0	0	0
T84	0	1	0	0
T93	0	1	0	0
T94	0	2	0	0
T128	404	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	1	0	0
T134	447	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	5479245	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	5481650	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	137	0	0
T9	710855	10	0	0
T10	17295	0	0	0
T11	1454	1	0	0
T12	504	0	0	0
T24	0	1	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T50	0	6	0	0
T56	0	6	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T84	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	72	0	0
T11	1454	1	0	0
T12	504	0	0	0
T26	491	0	0	0
T31	38205	0	0	0
T50	0	1	0	0
T51	26891	0	0	0
T56	0	1	0	0
T60	425	0	0	0
T61	422	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T75	502	0	0	0
T84	0	1	0	0
T93	0	3	0	0
T128	404	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	1	0	0
T134	447	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	51	0	0
T11	1454	1	0	0
T12	504	0	0	0
T26	491	0	0	0
T31	38205	0	0	0
T51	26891	0	0	0
T56	0	1	0	0
T60	425	0	0	0
T61	422	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T75	502	0	0	0
T84	0	1	0	0
T93	0	1	0	0
T94	0	2	0	0
T128	404	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	1	0	0
T134	447	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	51	0	0
T11	1454	1	0	0
T12	504	0	0	0
T26	491	0	0	0
T31	38205	0	0	0
T51	26891	0	0	0
T56	0	1	0	0
T60	425	0	0	0
T61	422	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T75	502	0	0	0
T84	0	1	0	0
T93	0	1	0	0
T94	0	2	0	0
T128	404	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	1	0	0
T134	447	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	10184	0	0
T11	1454	283	0	0
T12	504	0	0	0
T26	491	0	0	0
T31	38205	0	0	0
T51	26891	0	0	0
T56	0	284	0	0
T60	425	0	0	0
T61	422	0	0	0
T66	0	37	0	0
T67	0	46	0	0
T75	502	0	0	0
T84	0	270	0	0
T93	0	145	0	0
T94	0	310	0	0
T128	404	0	0	0
T129	0	377	0	0
T130	0	415	0	0
T131	0	341	0	0
T134	447	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	889562	0	0
T11	1454	695	0	0
T12	504	0	0	0
T26	491	0	0	0
T31	38205	0	0	0
T51	26891	0	0	0
T56	0	149	0	0
T60	425	0	0	0
T61	422	0	0	0
T66	0	134	0	0
T67	0	76	0	0
T75	502	0	0	0
T84	0	176	0	0
T93	0	183	0	0
T94	0	647284	0	0
T128	404	0	0	0
T129	0	731	0	0
T130	0	147	0	0
T131	0	87	0	0
T134	447	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T11,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T9,T11,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T11,T24,T66

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T24
1	0	Covered	T5,T6,T2
1	1	Covered	T9,T11,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T24,T66
0	1	Covered	T68,T91,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T24,T66
0	1	Unreachable
1	0	Covered	T11,T24,T66

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T11,T24
DetectSt	168	Covered	T11,T24,T66
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T11,T24,T66

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T24,T66
DebounceSt->IdleSt	163	Covered	T9,T50,T62
DetectSt->IdleSt	186	Covered	T68,T91,T92
DetectSt->StableSt	191	Covered	T11,T24,T66
IdleSt->DebounceSt	148	Covered	T9,T11,T24
StableSt->IdleSt	206	Covered	T11,T24,T66

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T11,T24
0	1	Covered	T9,T11,T24
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T24,T66
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T11,T24
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T24,T66
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T50,T130
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T11,T24
DetectSt	-	-	-	-	1	-	-	Covered	T68,T91,T92
DetectSt	-	-	-	-	0	1	-	Covered	T11,T24,T66
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T24,T66
StableSt	-	-	-	-	-	-	0	Covered	T11,T24,T66
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	191	0	0
CntIncr_A	8194048	433406	0	0
CntNoWrap_A	8194048	7548714	0	0
DetectStDropOut_A	8194048	5	0	0
DetectedOut_A	8194048	216255	0	0
DetectedPulseOut_A	8194048	53	0	0
DisabledIdleSt_A	8194048	5479245	0	0
DisabledNoDetection_A	8194048	5481650	0	0
EnterDebounceSt_A	8194048	133	0	0
EnterDetectSt_A	8194048	58	0	0
EnterStableSt_A	8194048	53	0	0
PulseIsPulse_A	8194048	53	0	0
StayInStableSt	8194048	216202	0	0
gen_high_event_sva.HighLevelEvent_A	8194048	7551311	0	0
gen_high_level_sva.HighLevelEvent_A	8194048	7551311	0	0
gen_sticky_sva.StableStDropOut_A	8194048	229599	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	191	0	0
T9	710855	10	0	0
T10	17295	0	0	0
T11	1454	2	0	0
T12	504	0	0	0
T24	0	2	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T50	0	6	0	0
T56	0	4	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	2	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	2	0	0
T84	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	433406	0	0
T9	710855	930	0	0
T10	17295	0	0	0
T11	1454	76	0	0
T12	504	0	0	0
T24	0	67	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T50	0	155240	0	0
T56	0	98	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	83	0	0
T66	0	84	0	0
T67	0	12	0	0
T68	0	14	0	0
T84	0	34	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548714	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	5	0	0
T62	7480	0	0	0
T68	911	1	0	0
T69	36602	0	0	0
T70	14574	0	0	0
T91	0	1	0	0
T92	0	1	0	0
T154	0	2	0	0
T155	590	0	0	0
T156	435	0	0	0
T157	15808	0	0	0
T158	23049	0	0	0
T159	1039	0	0	0
T160	30537	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	216255	0	0
T11	1454	469	0	0
T12	504	0	0	0
T24	0	1	0	0
T26	491	0	0	0
T31	38205	0	0	0
T51	26891	0	0	0
T56	0	765	0	0
T60	425	0	0	0
T61	422	0	0	0
T66	0	62	0	0
T67	0	6	0	0
T75	502	0	0	0
T84	0	192	0	0
T128	404	0	0	0
T129	0	520	0	0
T131	0	332	0	0
T132	0	286	0	0
T133	0	50	0	0
T134	447	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	53	0	0
T11	1454	1	0	0
T12	504	0	0	0
T24	0	1	0	0
T26	491	0	0	0
T31	38205	0	0	0
T51	26891	0	0	0
T56	0	2	0	0
T60	425	0	0	0
T61	422	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T75	502	0	0	0
T84	0	1	0	0
T128	404	0	0	0
T129	0	2	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	447	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	5479245	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	5481650	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	133	0	0
T9	710855	10	0	0
T10	17295	0	0	0
T11	1454	1	0	0
T12	504	0	0	0
T24	0	1	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T50	0	6	0	0
T56	0	2	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T84	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	58	0	0
T11	1454	1	0	0
T12	504	0	0	0
T24	0	1	0	0
T26	491	0	0	0
T31	38205	0	0	0
T51	26891	0	0	0
T56	0	2	0	0
T60	425	0	0	0
T61	422	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T75	502	0	0	0
T84	0	1	0	0
T128	404	0	0	0
T129	0	2	0	0
T131	0	1	0	0
T132	0	1	0	0
T134	447	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	53	0	0
T11	1454	1	0	0
T12	504	0	0	0
T24	0	1	0	0
T26	491	0	0	0
T31	38205	0	0	0
T51	26891	0	0	0
T56	0	2	0	0
T60	425	0	0	0
T61	422	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T75	502	0	0	0
T84	0	1	0	0
T128	404	0	0	0
T129	0	2	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	447	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	53	0	0
T11	1454	1	0	0
T12	504	0	0	0
T24	0	1	0	0
T26	491	0	0	0
T31	38205	0	0	0
T51	26891	0	0	0
T56	0	2	0	0
T60	425	0	0	0
T61	422	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T75	502	0	0	0
T84	0	1	0	0
T128	404	0	0	0
T129	0	2	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	447	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	216202	0	0
T11	1454	468	0	0
T12	504	0	0	0
T26	491	0	0	0
T31	38205	0	0	0
T51	26891	0	0	0
T56	0	763	0	0
T60	425	0	0	0
T61	422	0	0	0
T66	0	61	0	0
T67	0	5	0	0
T75	502	0	0	0
T84	0	191	0	0
T95	0	773	0	0
T128	404	0	0	0
T129	0	518	0	0
T131	0	331	0	0
T132	0	285	0	0
T133	0	49	0	0
T134	447	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	229599	0	0
T11	1454	476	0	0
T12	504	0	0	0
T24	0	105	0	0
T26	491	0	0	0
T31	38205	0	0	0
T51	26891	0	0	0
T56	0	213	0	0
T60	425	0	0	0
T61	422	0	0	0
T66	0	114	0	0
T67	0	181	0	0
T75	502	0	0	0
T84	0	272	0	0
T128	404	0	0	0
T129	0	582	0	0
T131	0	149	0	0
T132	0	430	0	0
T133	0	45394	0	0
T134	447	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T4,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T46
1	0	Covered	T5,T6,T7
1	1	Covered	T2,T4,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T46
0	1	Covered	T161
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T46
0	1	Covered	T4,T47,T56
1	0	Covered	T62,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T46
1	-	Covered	T4,T47,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T46
DetectSt	168	Covered	T2,T4,T46
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T4,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T46
DebounceSt->IdleSt	163	Covered	T2,T162,T143
DetectSt->IdleSt	186	Covered	T161
DetectSt->StableSt	191	Covered	T2,T4,T46
IdleSt->DebounceSt	148	Covered	T2,T4,T46
StableSt->IdleSt	206	Covered	T4,T47,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T46
0	1	Covered	T2,T4,T46
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T46
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T46
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T162
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T46
DetectSt	-	-	-	-	1	-	-	Covered	T161
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T47,T56
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	76	0	0
CntIncr_A	8194048	45791	0	0
CntNoWrap_A	8194048	7548829	0	0
DetectStDropOut_A	8194048	1	0	0
DetectedOut_A	8194048	2407	0	0
DetectedPulseOut_A	8194048	36	0	0
DisabledIdleSt_A	8194048	7430123	0	0
DisabledNoDetection_A	8194048	7432478	0	0
EnterDebounceSt_A	8194048	40	0	0
EnterDetectSt_A	8194048	37	0	0
EnterStableSt_A	8194048	36	0	0
PulseIsPulse_A	8194048	36	0	0
StayInStableSt	8194048	2351	0	0
gen_high_level_sva.HighLevelEvent_A	8194048	7551311	0	0
gen_not_sticky_sva.StableStDropOut_A	8194048	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	76	0	0
T2	1112	3	0	0
T3	19806	0	0	0
T4	724	2	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T50	0	2	0	0
T56	0	2	0	0
T62	0	2	0	0
T64	412	0	0	0
T70	0	6	0	0
T118	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	45791	0	0
T2	1112	198	0	0
T3	19806	0	0	0
T4	724	50	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	86	0	0
T46	0	91	0	0
T47	0	72	0	0
T50	0	97	0	0
T56	0	88	0	0
T62	0	28	0	0
T64	412	0	0	0
T70	0	103	0	0
T118	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548829	0	0
T1	509	108	0	0
T2	1112	708	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	1	0	0
T161	4070	1	0	0
T163	15047	0	0	0
T164	499	0	0	0
T165	46155	0	0	0
T166	4402	0	0	0
T167	425	0	0	0
T168	980	0	0	0
T169	1405	0	0	0
T170	484	0	0	0
T171	646	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	2407	0	0
T2	1112	37	0	0
T3	19806	0	0	0
T4	724	29	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	38	0	0
T46	0	39	0	0
T47	0	128	0	0
T50	0	174	0	0
T56	0	196	0	0
T62	0	5	0	0
T64	412	0	0	0
T70	0	319	0	0
T118	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	36	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	3	0	0
T118	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7430123	0	0
T1	509	108	0	0
T2	1112	4	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7432478	0	0
T1	509	109	0	0
T2	1112	4	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	40	0	0
T2	1112	2	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	3	0	0
T118	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	37	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	3	0	0
T118	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	36	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	3	0	0
T118	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	36	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	3	0	0
T118	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	2351	0	0
T2	1112	35	0	0
T3	19806	0	0	0
T4	724	28	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	36	0	0
T46	0	37	0	0
T47	0	127	0	0
T50	0	173	0	0
T56	0	195	0	0
T62	0	4	0	0
T64	412	0	0	0
T70	0	314	0	0
T118	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	14	0	0
T4	724	1	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T27	502	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T59	516	0	0	0
T64	412	0	0	0
T65	406	0	0	0
T70	0	1	0	0
T107	0	2	0	0
T161	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T42,T44,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T42,T44,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T42,T44,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T42,T44,T49
1	0	Covered	T5,T6,T2
1	1	Covered	T42,T44,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T44,T47,T48
0	1	Covered	T42,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T44,T47,T48
0	1	Covered	T44,T47,T48
1	0	Covered	T62,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T44,T47,T48
1	-	Covered	T44,T47,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T42,T44,T47
DetectSt	168	Covered	T42,T44,T47
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T44,T47,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T42,T44,T47
DebounceSt->IdleSt	163	Covered	T175,T176,T91
DetectSt->IdleSt	186	Covered	T42,T88
DetectSt->StableSt	191	Covered	T44,T47,T48
IdleSt->DebounceSt	148	Covered	T42,T44,T47
StableSt->IdleSt	206	Covered	T44,T47,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T42,T44,T47
0	1	Covered	T42,T44,T47
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T44,T47
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T42,T44,T47
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T42,T44,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T175,T176,T91
DebounceSt	-	0	0	-	-	-	-	Covered	T42,T44,T47
DetectSt	-	-	-	-	1	-	-	Covered	T42,T88
DetectSt	-	-	-	-	0	1	-	Covered	T44,T47,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T44,T47,T48
StableSt	-	-	-	-	-	-	0	Covered	T44,T47,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	109	0	0
CntIncr_A	8194048	66444	0	0
CntNoWrap_A	8194048	7548796	0	0
DetectStDropOut_A	8194048	2	0	0
DetectedOut_A	8194048	20842	0	0
DetectedPulseOut_A	8194048	51	0	0
DisabledIdleSt_A	8194048	7364475	0	0
DisabledNoDetection_A	8194048	7366836	0	0
EnterDebounceSt_A	8194048	56	0	0
EnterDetectSt_A	8194048	53	0	0
EnterStableSt_A	8194048	51	0	0
PulseIsPulse_A	8194048	51	0	0
StayInStableSt	8194048	20770	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8194048	2596	0	0
gen_low_level_sva.LowLevelEvent_A	8194048	7551311	0	0
gen_not_sticky_sva.StableStDropOut_A	8194048	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	109	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T42	543	2	0	0
T44	3072	4	0	0
T47	0	4	0	0
T48	0	2	0	0
T52	666	0	0	0
T62	0	2	0	0
T72	491	0	0	0
T78	521	0	0	0
T88	0	2	0	0
T150	0	6	0	0
T177	0	4	0	0
T178	0	4	0	0
T179	0	2	0	0
T180	430	0	0	0
T181	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	66444	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T42	543	40	0	0
T44	3072	146	0	0
T47	0	144	0	0
T48	0	66	0	0
T52	666	0	0	0
T62	0	28	0	0
T72	491	0	0	0
T78	521	0	0	0
T88	0	43920	0	0
T150	0	84	0	0
T177	0	19832	0	0
T178	0	166	0	0
T179	0	25	0	0
T180	430	0	0	0
T181	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548796	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	2	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T42	543	1	0	0
T44	3072	0	0	0
T52	666	0	0	0
T72	491	0	0	0
T78	521	0	0	0
T88	0	1	0	0
T180	430	0	0	0
T181	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	20842	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T44	3072	84	0	0
T45	769	0	0	0
T47	0	52	0	0
T48	0	48	0	0
T52	666	0	0	0
T62	0	4	0	0
T72	491	0	0	0
T78	521	0	0	0
T150	0	126	0	0
T177	0	17477	0	0
T178	0	291	0	0
T179	0	95	0	0
T180	430	0	0	0
T181	422	0	0	0
T182	0	43	0	0
T183	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	51	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T44	3072	2	0	0
T45	769	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T52	666	0	0	0
T62	0	1	0	0
T72	491	0	0	0
T78	521	0	0	0
T150	0	3	0	0
T177	0	2	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	430	0	0	0
T181	422	0	0	0
T182	0	1	0	0
T183	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7364475	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7366836	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	56	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T42	543	1	0	0
T44	3072	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T52	666	0	0	0
T62	0	1	0	0
T72	491	0	0	0
T78	521	0	0	0
T88	0	1	0	0
T150	0	3	0	0
T177	0	2	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	430	0	0	0
T181	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	53	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T42	543	1	0	0
T44	3072	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T52	666	0	0	0
T62	0	1	0	0
T72	491	0	0	0
T78	521	0	0	0
T88	0	1	0	0
T150	0	3	0	0
T177	0	2	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	430	0	0	0
T181	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	51	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T44	3072	2	0	0
T45	769	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T52	666	0	0	0
T62	0	1	0	0
T72	491	0	0	0
T78	521	0	0	0
T150	0	3	0	0
T177	0	2	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	430	0	0	0
T181	422	0	0	0
T182	0	1	0	0
T183	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	51	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T44	3072	2	0	0
T45	769	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T52	666	0	0	0
T62	0	1	0	0
T72	491	0	0	0
T78	521	0	0	0
T150	0	3	0	0
T177	0	2	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	430	0	0	0
T181	422	0	0	0
T182	0	1	0	0
T183	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	20770	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T44	3072	81	0	0
T45	769	0	0	0
T47	0	49	0	0
T48	0	47	0	0
T52	666	0	0	0
T62	0	3	0	0
T72	491	0	0	0
T78	521	0	0	0
T150	0	122	0	0
T177	0	17475	0	0
T178	0	288	0	0
T179	0	93	0	0
T180	430	0	0	0
T181	422	0	0	0
T182	0	42	0	0
T183	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	2596	0	0
T1	509	0	0	0
T2	1112	2	0	0
T4	0	2	0	0
T5	501	6	0	0
T6	502	5	0	0
T7	404	0	0	0
T14	969	0	0	0
T15	670	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T20	0	3	0	0
T25	0	4	0	0
T27	0	3	0	0
T28	0	6	0	0
T60	0	2	0	0
T61	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	28	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T44	3072	1	0	0
T45	769	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T52	666	0	0	0
T72	491	0	0	0
T78	521	0	0	0
T150	0	2	0	0
T177	0	2	0	0
T178	0	1	0	0
T180	430	0	0	0
T181	422	0	0	0
T182	0	1	0	0
T184	0	1	0	0
T185	0	2	0	0
T186	0	1	0	0