Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	89.69	91.30	90.48		83.33	90.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	89.69	91.30	90.48		83.33	90.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	89.77	91.30	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	92.41	93.48	95.24		83.33	90.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
92.41	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
89.77	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
89.69	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
89.69	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T17,T3
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T17,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T17,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T17,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T3
1	0	Covered	T17,T3,T10
1	1	Covered	T1,T17,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T3
0	1	Covered	T51,T83,T80
1	0	Covered	T62,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T3
0	1	Covered	T1,T3,T10
1	0	Covered	T62,T85,T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T17,T3
1	-	Covered	T1,T3,T10

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
92.41	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
89.77	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T30,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T30,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T30,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T30,T31
1	0	Covered	T5,T6,T1
1	1	Covered	T2,T30,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T30,T31
0	1	Covered	T42,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T30,T31
0	1	Covered	T2,T30,T31
1	0	Covered	T62,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T30,T31
1	-	Covered	T2,T30,T31

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T3,T10
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T17,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T17,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T17,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T3,T10
1	0	Covered	T17,T3,T10
1	1	Covered	T1,T17,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T3
0	1	Covered	T17,T81,T39
1	0	Covered	T17,T3,T10

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T3
0	1	Covered	T17,T3,T10
1	0	Covered	T89,T63,T90

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T17,T3
1	-	Covered	T17,T3,T10

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T11,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T11,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T11,T24,T66

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T24
1	0	Covered	T5,T6,T2
1	1	Covered	T9,T11,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T24,T66
0	1	Covered	T68,T91,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T24,T66
0	1	Unreachable
1	0	Covered	T11,T24,T66

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
89.69	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
89.69	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Covered	T5,T6,T7
1	1	Covered	T2,T4,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T8
0	1	Covered	T42,T50,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T8
0	1	Covered	T2,T4,T44
1	0	Covered	T62,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T8
1	-	Covered	T2,T4,T44

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T2
1	1	Covered	T5,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T11,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T11,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T11,T66,T67

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T24
1	0	Covered	T5,T6,T2
1	1	Covered	T9,T11,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T66,T67
0	1	Covered	T50,T93,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T66,T67
0	1	Unreachable
1	0	Covered	T11,T66,T67

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T2
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T2
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T11,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T11,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T11,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T24
1	0	Covered	T5,T6,T2
1	1	Covered	T9,T11,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T24
0	1	Covered	T56,T95,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T24
0	1	Unreachable
1	0	Covered	T9,T11,T24

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T30,T31
DetectSt	168	Covered	T2,T30,T31
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T30,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T30,T31
DebounceSt->IdleSt	163	Covered	T8,T49,T70
DetectSt->IdleSt	186	Covered	T42,T56,T50
DetectSt->StableSt	191	Covered	T2,T30,T31
IdleSt->DebounceSt	148	Covered	T2,T30,T31
StableSt->IdleSt	206	Covered	T2,T30,T31

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
92.41	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.77	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
89.69	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
89.69	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T30,T31
0	1	Covered	T2,T30,T31
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T30,T31
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T30,T31
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T30,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T49,T70
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T30,T31
DetectSt	-	-	-	-	1	-	-	Covered	T42,T56,T50
DetectSt	-	-	-	-	0	1	-	Covered	T2,T30,T31
DetectSt	-	-	-	-	0	0	-	Covered	T1,T17,T3
StableSt	-	-	-	-	-	-	1	Covered	T2,T30,T31
StableSt	-	-	-	-	-	-	0	Covered	T2,T30,T31
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T17,T3
0	1	Covered	T1,T17,T3
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T17,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T17,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T17,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T50,T62
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T17,T3
DetectSt	-	-	-	-	1	-	-	Covered	T17,T3,T10
DetectSt	-	-	-	-	0	1	-	Covered	T1,T17,T10
DetectSt	-	-	-	-	0	0	-	Covered	T1,T17,T3
StableSt	-	-	-	-	-	-	1	Covered	T17,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T17,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	213045248	18611	0	0
CntIncr_A	213045248	2192564	0	0
CntNoWrap_A	213045248	196252919	0	0
DetectStDropOut_A	213045248	1619	0	0
DetectedOut_A	213045248	1873335	0	0
DetectedPulseOut_A	213045248	6473	0	0
DisabledIdleSt_A	213045248	184551942	0	0
DisabledNoDetection_A	213045248	184609626	0	0
EnterDebounceSt_A	213045248	9655	0	0
EnterDetectSt_A	213045248	8978	0	0
EnterStableSt_A	213045248	6473	0	0
PulseIsPulse_A	213045248	6473	0	0
StayInStableSt	213045248	1865856	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	73746432	51845	0	0
gen_high_event_sva.HighLevelEvent_A	40970240	37756555	0	0
gen_high_level_sva.HighLevelEvent_A	139298816	128372287	0	0
gen_low_level_sva.LowLevelEvent_A	73746432	67961799	0	0
gen_not_sticky_sva.StableStDropOut_A	188463104	5238	0	0
gen_sticky_sva.StableStDropOut_A	24582144	1777684	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213045248	18611	0	0
T1	1018	4	0	0
T2	2224	0	0	0
T3	59418	0	0	0
T10	17295	26	0	0
T11	1454	0	0	0
T12	504	4	0	0
T13	0	4	0	0
T14	1938	0	0	0
T15	1340	0	0	0
T16	804	0	0	0
T17	45936	60	0	0
T18	1221	0	0	0
T19	2448	0	0	0
T20	1266	0	0	0
T25	496	0	0	0
T28	522	0	0	0
T30	593	6	0	0
T31	38205	4	0	0
T35	0	48	0	0
T36	0	50	0	0
T37	0	8	0	0
T38	0	54	0	0
T40	0	4	0	0
T50	0	4	0	0
T51	26891	0	0	0
T52	0	4	0	0
T53	0	4	0	0
T54	0	4	0	0
T55	0	4	0	0
T56	0	2	0	0
T57	0	4	0	0
T58	0	2	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T83	0	11	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213045248	2192564	0	0
T1	1018	46	0	0
T2	2224	0	0	0
T3	59418	0	0	0
T10	17295	540	0	0
T11	1454	0	0	0
T12	504	46	0	0
T13	0	46	0	0
T14	1938	0	0	0
T15	1340	0	0	0
T16	804	0	0	0
T17	45936	1532	0	0
T18	1221	0	0	0
T19	2448	0	0	0
T20	1266	0	0	0
T25	496	0	0	0
T28	522	0	0	0
T30	593	56	0	0
T31	38205	37605	0	0
T35	0	1402	0	0
T36	0	1708	0	0
T37	0	276	0	0
T38	0	2349	0	0
T40	0	308	0	0
T50	0	59	0	0
T51	26891	0	0	0
T52	0	115	0	0
T53	0	81	0	0
T54	0	156	0	0
T55	0	22524	0	0
T56	0	38	0	0
T57	0	68	0	0
T58	0	62	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T83	0	632	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213045248	196252919	0	0
T1	13234	2804	0	0
T2	28912	18461	0	0
T5	13026	2600	0	0
T6	13052	2626	0	0
T7	10504	78	0	0
T14	25194	14768	0	0
T15	17420	6994	0	0
T16	10452	26	0	0
T17	398112	386438	0	0
T18	10582	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213045248	1619	0	0
T41	20930	4	0	0
T55	23138	0	0	0
T56	14199	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T69	0	12	0	0
T81	5517	28	0	0
T82	0	15	0	0
T97	0	26	0	0
T98	0	13	0	0
T99	0	3	0	0
T100	0	12	0	0
T101	0	24	0	0
T102	0	11	0	0
T103	0	1	0	0
T104	0	15	0	0
T105	0	9	0	0
T106	0	7	0	0
T107	0	2	0	0
T108	0	4	0	0
T109	718	1	0	0
T110	0	4	0	0
T111	0	1	0	0
T112	407	0	0	0
T113	447	0	0	0
T114	27767	0	0	0
T115	8402	0	0	0
T116	421	0	0	0
T117	510	0	0	0
T118	771	0	0	0
T119	402	0	0	0
T120	21165	0	0	0
T121	9623	0	0	0
T122	492	0	0	0
T123	4768	0	0	0
T124	2046	0	0	0
T125	427	0	0	0
T126	493	0	0	0
T127	440	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213045248	1873335	0	0
T1	1018	86	0	0
T2	2224	0	0	0
T3	59418	0	0	0
T10	17295	746	0	0
T11	1454	0	0	0
T12	504	82	0	0
T13	0	90	0	0
T14	1938	0	0	0
T15	1340	0	0	0
T16	804	0	0	0
T17	45936	0	0	0
T18	1221	0	0	0
T19	2448	0	0	0
T20	1266	0	0	0
T25	496	0	0	0
T28	522	0	0	0
T30	593	14	0	0
T31	38205	8	0	0
T35	0	1305	0	0
T36	0	3384	0	0
T37	0	1075	0	0
T38	0	929	0	0
T39	0	794	0	0
T40	0	37	0	0
T50	0	8	0	0
T51	26891	0	0	0
T52	0	14	0	0
T53	0	8	0	0
T54	0	13	0	0
T55	0	13	0	0
T56	0	10	0	0
T57	0	15	0	0
T58	0	10	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T83	0	105	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213045248	6473	0	0
T1	1018	2	0	0
T2	2224	0	0	0
T3	59418	0	0	0
T10	17295	13	0	0
T11	1454	0	0	0
T12	504	2	0	0
T13	0	2	0	0
T14	1938	0	0	0
T15	1340	0	0	0
T16	804	0	0	0
T17	45936	0	0	0
T18	1221	0	0	0
T19	2448	0	0	0
T20	1266	0	0	0
T25	496	0	0	0
T28	522	0	0	0
T30	593	3	0	0
T31	38205	2	0	0
T35	0	24	0	0
T36	0	25	0	0
T37	0	12	0	0
T38	0	27	0	0
T39	0	6	0	0
T40	0	1	0	0
T50	0	2	0	0
T51	26891	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T83	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213045248	184551942	0	0
T1	13234	2622	0	0
T2	28912	12123	0	0
T5	13026	2600	0	0
T6	13052	2626	0	0
T7	10504	78	0	0
T14	25194	14768	0	0
T15	17420	6994	0	0
T16	10452	26	0	0
T17	398112	371566	0	0
T18	10582	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213045248	184609626	0	0
T1	13234	2646	0	0
T2	28912	12140	0	0
T5	13026	2626	0	0
T6	13052	2652	0	0
T7	10504	104	0	0
T14	25194	14794	0	0
T15	17420	7020	0	0
T16	10452	52	0	0
T17	398112	371684	0	0
T18	10582	182	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213045248	9655	0	0
T1	1018	2	0	0
T2	2224	0	0	0
T3	59418	0	0	0
T10	17295	13	0	0
T11	1454	0	0	0
T12	504	2	0	0
T13	0	2	0	0
T14	1938	0	0	0
T15	1340	0	0	0
T16	804	0	0	0
T17	45936	30	0	0
T18	1221	0	0	0
T19	2448	0	0	0
T20	1266	0	0	0
T25	496	0	0	0
T28	522	0	0	0
T30	593	3	0	0
T31	38205	2	0	0
T35	0	24	0	0
T36	0	25	0	0
T37	0	4	0	0
T38	0	27	0	0
T40	0	3	0	0
T50	0	2	0	0
T51	26891	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T83	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213045248	8978	0	0
T1	1018	2	0	0
T2	2224	0	0	0
T3	59418	0	0	0
T10	17295	13	0	0
T11	1454	0	0	0
T12	504	2	0	0
T13	0	2	0	0
T14	1938	0	0	0
T15	1340	0	0	0
T16	804	0	0	0
T17	45936	30	0	0
T18	1221	0	0	0
T19	2448	0	0	0
T20	1266	0	0	0
T25	496	0	0	0
T28	522	0	0	0
T30	593	3	0	0
T31	38205	2	0	0
T35	0	24	0	0
T36	0	25	0	0
T37	0	4	0	0
T38	0	27	0	0
T40	0	1	0	0
T50	0	2	0	0
T51	26891	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T83	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213045248	6473	0	0
T1	1018	2	0	0
T2	2224	0	0	0
T3	59418	0	0	0
T10	17295	13	0	0
T11	1454	0	0	0
T12	504	2	0	0
T13	0	2	0	0
T14	1938	0	0	0
T15	1340	0	0	0
T16	804	0	0	0
T17	45936	0	0	0
T18	1221	0	0	0
T19	2448	0	0	0
T20	1266	0	0	0
T25	496	0	0	0
T28	522	0	0	0
T30	593	3	0	0
T31	38205	2	0	0
T35	0	24	0	0
T36	0	25	0	0
T37	0	12	0	0
T38	0	27	0	0
T39	0	6	0	0
T40	0	1	0	0
T50	0	2	0	0
T51	26891	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T83	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213045248	6473	0	0
T1	1018	2	0	0
T2	2224	0	0	0
T3	59418	0	0	0
T10	17295	13	0	0
T11	1454	0	0	0
T12	504	2	0	0
T13	0	2	0	0
T14	1938	0	0	0
T15	1340	0	0	0
T16	804	0	0	0
T17	45936	0	0	0
T18	1221	0	0	0
T19	2448	0	0	0
T20	1266	0	0	0
T25	496	0	0	0
T28	522	0	0	0
T30	593	3	0	0
T31	38205	2	0	0
T35	0	24	0	0
T36	0	25	0	0
T37	0	12	0	0
T38	0	27	0	0
T39	0	6	0	0
T40	0	1	0	0
T50	0	2	0	0
T51	26891	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T83	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	213045248	1865856	0	0
T1	1018	83	0	0
T2	2224	0	0	0
T3	59418	0	0	0
T10	17295	730	0	0
T11	1454	0	0	0
T12	504	79	0	0
T13	0	87	0	0
T14	1938	0	0	0
T15	1340	0	0	0
T16	804	0	0	0
T17	45936	0	0	0
T18	1221	0	0	0
T19	2448	0	0	0
T20	1266	0	0	0
T25	496	0	0	0
T28	522	0	0	0
T30	593	11	0	0
T31	38205	6	0	0
T35	0	1277	0	0
T36	0	3355	0	0
T37	0	1059	0	0
T38	0	901	0	0
T39	0	785	0	0
T40	0	36	0	0
T50	0	6	0	0
T51	26891	0	0	0
T52	0	12	0	0
T53	0	6	0	0
T54	0	11	0	0
T55	0	11	0	0
T56	0	9	0	0
T57	0	13	0	0
T58	0	9	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T83	0	101	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73746432	51845	0	0
T1	4581	3	0	0
T2	10008	11	0	0
T3	0	214	0	0
T4	0	10	0	0
T5	4509	52	0	0
T6	4518	38	0	0
T7	3636	0	0	0
T8	0	1	0	0
T9	0	45	0	0
T14	8721	4	0	0
T15	6030	3	0	0
T16	3618	0	0	0
T17	137808	230	0	0
T18	3663	0	0	0
T19	0	5	0	0
T20	0	19	0	0
T25	0	57	0	0
T27	0	37	0	0
T28	0	6	0	0
T60	0	2	0	0
T61	0	1	0	0
T65	0	2	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40970240	37756555	0	0
T1	2545	545	0	0
T2	5560	3560	0	0
T5	2505	505	0	0
T6	2510	510	0	0
T7	2020	20	0	0
T14	4845	2845	0	0
T15	3350	1350	0	0
T16	2010	10	0	0
T17	76560	74380	0	0
T18	2035	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139298816	128372287	0	0
T1	8653	1853	0	0
T2	18904	12104	0	0
T5	8517	1717	0	0
T6	8534	1734	0	0
T7	6868	68	0	0
T14	16473	9673	0	0
T15	11390	4590	0	0
T16	6834	34	0	0
T17	260304	252892	0	0
T18	6919	119	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73746432	67961799	0	0
T1	4581	981	0	0
T2	10008	6408	0	0
T5	4509	909	0	0
T6	4518	918	0	0
T7	3636	36	0	0
T14	8721	5121	0	0
T15	6030	2430	0	0
T16	3618	18	0	0
T17	137808	133884	0	0
T18	3663	63	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188463104	5238	0	0
T1	509	1	0	0
T2	1112	0	0	0
T3	19806	0	0	0
T10	34590	10	0	0
T11	2908	0	0	0
T12	1008	1	0	0
T13	0	1	0	0
T14	969	0	0	0
T15	670	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T28	1044	0	0	0
T30	593	3	0	0
T31	76410	2	0	0
T35	0	20	0	0
T36	0	21	0	0
T37	0	8	0	0
T38	0	26	0	0
T39	0	6	0	0
T40	0	1	0	0
T50	0	2	0	0
T51	53782	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	1032	0	0	0
T60	850	0	0	0
T61	844	0	0	0
T83	0	4	0	0
T128	404	0	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24582144	1777684	0	0
T9	710855	599	0	0
T10	17295	0	0	0
T11	4362	1259	0	0
T12	1512	0	0	0
T24	0	133	0	0
T26	982	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	114615	0	0	0
T50	0	37	0	0
T51	53782	0	0	0
T56	0	687	0	0
T59	516	0	0	0
T60	1275	0	0	0
T61	1266	0	0	0
T66	0	248	0	0
T67	0	257	0	0
T68	0	36	0	0
T75	1004	0	0	0
T84	0	448	0	0
T93	0	364	0	0
T94	0	647284	0	0
T128	808	0	0	0
T129	0	1479	0	0
T130	0	420	0	0
T131	0	442	0	0
T132	0	430	0	0
T133	0	45394	0	0
T134	894	0	0	0