Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T44,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T44,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T44,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T44,T45
1	0	Covered	T5,T6,T7
1	1	Covered	T2,T44,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T44,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T44,T45
0	1	Covered	T2,T187,T188
1	0	Covered	T62,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T44,T45
1	-	Covered	T2,T187,T188

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T44,T45
DetectSt	168	Covered	T2,T44,T45
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T44,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T44,T45
DebounceSt->IdleSt	163	Covered	T70,T189,T190
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T44,T45
IdleSt->DebounceSt	148	Covered	T2,T44,T45
StableSt->IdleSt	206	Covered	T2,T44,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T44,T45
0	1	Covered	T2,T44,T45
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T44,T45
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T44,T45
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T44,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T70,T189,T190
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T44,T45
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T44,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T62,T187
StableSt	-	-	-	-	-	-	0	Covered	T2,T44,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	98	0	0
CntIncr_A	8194048	2808	0	0
CntNoWrap_A	8194048	7548807	0	0
DetectStDropOut_A	8194048	0	0	0
DetectedOut_A	8194048	3910	0	0
DetectedPulseOut_A	8194048	47	0	0
DisabledIdleSt_A	8194048	7508071	0	0
DisabledNoDetection_A	8194048	7510418	0	0
EnterDebounceSt_A	8194048	51	0	0
EnterDetectSt_A	8194048	47	0	0
EnterStableSt_A	8194048	47	0	0
PulseIsPulse_A	8194048	47	0	0
StayInStableSt	8194048	3839	0	0
gen_high_level_sva.HighLevelEvent_A	8194048	7551311	0	0
gen_not_sticky_sva.StableStDropOut_A	8194048	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	98	0	0
T2	1112	2	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T47	0	2	0	0
T50	0	4	0	0
T56	0	2	0	0
T62	0	2	0	0
T64	412	0	0	0
T70	0	3	0	0
T118	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	2808	0	0
T2	1112	99	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	86	0	0
T44	0	73	0	0
T45	0	52	0	0
T47	0	72	0	0
T50	0	108	0	0
T56	0	88	0	0
T62	0	28	0	0
T64	412	0	0	0
T70	0	171	0	0
T118	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548807	0	0
T1	509	108	0	0
T2	1112	709	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	3910	0	0
T2	1112	72	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	38	0	0
T44	0	41	0	0
T45	0	41	0	0
T47	0	40	0	0
T50	0	114	0	0
T56	0	185	0	0
T62	0	4	0	0
T64	412	0	0	0
T70	0	45	0	0
T118	0	221	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	47	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	2	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	1	0	0
T118	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7508071	0	0
T1	509	108	0	0
T2	1112	4	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7510418	0	0
T1	509	109	0	0
T2	1112	4	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	51	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	2	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	2	0	0
T118	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	47	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	2	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	1	0	0
T118	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	47	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	2	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	1	0	0
T118	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	47	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	2	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	1	0	0
T118	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	3839	0	0
T2	1112	71	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	36	0	0
T44	0	39	0	0
T45	0	39	0	0
T47	0	38	0	0
T50	0	110	0	0
T56	0	183	0	0
T62	0	3	0	0
T64	412	0	0	0
T70	0	43	0	0
T118	0	219	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	21	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T64	412	0	0	0
T141	0	1	0	0
T172	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T4,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Covered	T5,T6,T14
1	1	Covered	T2,T4,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T43
0	1	Covered	T195
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T43
0	1	Covered	T2,T4,T43
1	0	Covered	T62,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T43
1	-	Covered	T2,T4,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T8
DetectSt	168	Covered	T2,T4,T43
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T4,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T43
DebounceSt->IdleSt	163	Covered	T8,T141,T196
DetectSt->IdleSt	186	Covered	T195
DetectSt->StableSt	191	Covered	T2,T4,T43
IdleSt->DebounceSt	148	Covered	T2,T4,T8
StableSt->IdleSt	206	Covered	T2,T4,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T8
0	1	Covered	T2,T4,T8
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T43
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T141,T196
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T8
DetectSt	-	-	-	-	1	-	-	Covered	T195
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T4,T43
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	136	0	0
CntIncr_A	8194048	47832	0	0
CntNoWrap_A	8194048	7548769	0	0
DetectStDropOut_A	8194048	1	0	0
DetectedOut_A	8194048	49283	0	0
DetectedPulseOut_A	8194048	63	0	0
DisabledIdleSt_A	8194048	7442450	0	0
DisabledNoDetection_A	8194048	7444802	0	0
EnterDebounceSt_A	8194048	72	0	0
EnterDetectSt_A	8194048	64	0	0
EnterStableSt_A	8194048	63	0	0
PulseIsPulse_A	8194048	63	0	0
StayInStableSt	8194048	49190	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8194048	2982	0	0
gen_low_level_sva.LowLevelEvent_A	8194048	7551311	0	0
gen_not_sticky_sva.StableStDropOut_A	8194048	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	136	0	0
T2	1112	4	0	0
T3	19806	0	0	0
T4	724	2	0	0
T8	0	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T56	0	2	0	0
T64	412	0	0	0
T70	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	47832	0	0
T2	1112	198	0	0
T3	19806	0	0	0
T4	724	50	0	0
T8	0	58	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	86	0	0
T47	0	72	0	0
T48	0	66	0	0
T49	0	78	0	0
T50	0	97	0	0
T56	0	88	0	0
T64	412	0	0	0
T70	0	252	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548769	0	0
T1	509	108	0	0
T2	1112	707	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	1	0	0
T129	1824	0	0	0
T130	1788	0	0	0
T195	585	1	0	0
T197	30972	0	0	0
T198	436	0	0	0
T199	422	0	0	0
T200	59436	0	0	0
T201	423	0	0	0
T202	457	0	0	0
T203	807	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	49283	0	0
T2	1112	88	0	0
T3	19806	0	0	0
T4	724	91	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	130	0	0
T47	0	213	0	0
T48	0	154	0	0
T49	0	50	0	0
T50	0	430	0	0
T56	0	198	0	0
T62	0	4	0	0
T64	412	0	0	0
T70	0	334	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	63	0	0
T2	1112	2	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7442450	0	0
T1	509	108	0	0
T2	1112	4	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7444802	0	0
T1	509	109	0	0
T2	1112	4	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	72	0	0
T2	1112	2	0	0
T3	19806	0	0	0
T4	724	1	0	0
T8	0	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T64	412	0	0	0
T70	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	64	0	0
T2	1112	2	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	63	0	0
T2	1112	2	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	63	0	0
T2	1112	2	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	49190	0	0
T2	1112	85	0	0
T3	19806	0	0	0
T4	724	90	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	129	0	0
T47	0	212	0	0
T48	0	152	0	0
T49	0	48	0	0
T50	0	429	0	0
T56	0	197	0	0
T62	0	3	0	0
T64	412	0	0	0
T70	0	330	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	2982	0	0
T1	509	0	0	0
T2	1112	2	0	0
T4	0	1	0	0
T5	501	6	0	0
T6	502	3	0	0
T7	404	0	0	0
T14	969	4	0	0
T15	670	3	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	0	5	0	0
T20	0	3	0	0
T25	0	4	0	0
T65	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	31	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T43	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T64	412	0	0	0
T70	0	2	0	0
T178	0	1	0	0
T182	0	1	0	0
T192	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T2
1	1	Covered	T5,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T44,T49,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T44,T49,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T44,T49,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T44,T49,T50
1	0	Covered	T5,T6,T2
1	1	Covered	T44,T49,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T44,T49,T50
0	1	Covered	T186,T204,T205
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T44,T49,T50
0	1	Covered	T44,T49,T50
1	0	Covered	T62,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T44,T49,T50
1	-	Covered	T44,T49,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T44,T49,T50
DetectSt	168	Covered	T44,T49,T50
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T44,T49,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T44,T49,T50
DebounceSt->IdleSt	163	Covered	T206
DetectSt->IdleSt	186	Covered	T186,T204,T205
DetectSt->StableSt	191	Covered	T44,T49,T50
IdleSt->DebounceSt	148	Covered	T44,T49,T50
StableSt->IdleSt	206	Covered	T44,T49,T50

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T44,T49,T50
0	1	Covered	T44,T49,T50
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T44,T49,T50
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T44,T49,T50
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T44,T49,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T206
DebounceSt	-	0	0	-	-	-	-	Covered	T44,T49,T50
DetectSt	-	-	-	-	1	-	-	Covered	T186,T204,T205
DetectSt	-	-	-	-	0	1	-	Covered	T44,T49,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T44,T49,T50
StableSt	-	-	-	-	-	-	0	Covered	T44,T49,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	123	0	0
CntIncr_A	8194048	12798	0	0
CntNoWrap_A	8194048	7548782	0	0
DetectStDropOut_A	8194048	5	0	0
DetectedOut_A	8194048	32595	0	0
DetectedPulseOut_A	8194048	56	0	0
DisabledIdleSt_A	8194048	7459240	0	0
DisabledNoDetection_A	8194048	7461599	0	0
EnterDebounceSt_A	8194048	62	0	0
EnterDetectSt_A	8194048	61	0	0
EnterStableSt_A	8194048	56	0	0
PulseIsPulse_A	8194048	56	0	0
StayInStableSt	8194048	32514	0	0
gen_high_level_sva.HighLevelEvent_A	8194048	7551311	0	0
gen_not_sticky_sva.StableStDropOut_A	8194048	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	123	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T44	3072	4	0	0
T45	769	0	0	0
T49	0	4	0	0
T50	0	6	0	0
T52	666	0	0	0
T62	0	2	0	0
T72	491	0	0	0
T78	521	0	0	0
T150	0	2	0	0
T177	0	2	0	0
T178	0	2	0	0
T179	0	2	0	0
T180	430	0	0	0
T181	422	0	0	0
T203	0	4	0	0
T207	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	12798	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T44	3072	146	0	0
T45	769	0	0	0
T49	0	156	0	0
T50	0	205	0	0
T52	666	0	0	0
T62	0	28	0	0
T72	491	0	0	0
T78	521	0	0	0
T150	0	28	0	0
T177	0	9916	0	0
T178	0	83	0	0
T179	0	25	0	0
T180	430	0	0	0
T181	422	0	0	0
T203	0	72	0	0
T207	0	49	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548782	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	5	0	0
T146	0	1	0	0
T186	13027	1	0	0
T190	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T208	11543	0	0	0
T209	862	0	0	0
T210	7748	0	0	0
T211	1217	0	0	0
T212	953	0	0	0
T213	700	0	0	0
T214	522	0	0	0
T215	492	0	0	0
T216	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	32595	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T44	3072	100	0	0
T45	769	0	0	0
T49	0	236	0	0
T50	0	206	0	0
T52	666	0	0	0
T62	0	5	0	0
T72	491	0	0	0
T78	521	0	0	0
T150	0	44	0	0
T177	0	27968	0	0
T178	0	326	0	0
T179	0	23	0	0
T180	430	0	0	0
T181	422	0	0	0
T203	0	247	0	0
T207	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	56	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T44	3072	2	0	0
T45	769	0	0	0
T49	0	2	0	0
T50	0	3	0	0
T52	666	0	0	0
T62	0	1	0	0
T72	491	0	0	0
T78	521	0	0	0
T150	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	430	0	0	0
T181	422	0	0	0
T203	0	2	0	0
T207	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7459240	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7461599	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	62	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T44	3072	2	0	0
T45	769	0	0	0
T49	0	2	0	0
T50	0	3	0	0
T52	666	0	0	0
T62	0	1	0	0
T72	491	0	0	0
T78	521	0	0	0
T150	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	430	0	0	0
T181	422	0	0	0
T203	0	2	0	0
T207	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	61	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T44	3072	2	0	0
T45	769	0	0	0
T49	0	2	0	0
T50	0	3	0	0
T52	666	0	0	0
T62	0	1	0	0
T72	491	0	0	0
T78	521	0	0	0
T150	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	430	0	0	0
T181	422	0	0	0
T203	0	2	0	0
T207	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	56	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T44	3072	2	0	0
T45	769	0	0	0
T49	0	2	0	0
T50	0	3	0	0
T52	666	0	0	0
T62	0	1	0	0
T72	491	0	0	0
T78	521	0	0	0
T150	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	430	0	0	0
T181	422	0	0	0
T203	0	2	0	0
T207	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	56	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T44	3072	2	0	0
T45	769	0	0	0
T49	0	2	0	0
T50	0	3	0	0
T52	666	0	0	0
T62	0	1	0	0
T72	491	0	0	0
T78	521	0	0	0
T150	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	430	0	0	0
T181	422	0	0	0
T203	0	2	0	0
T207	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	32514	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T44	3072	97	0	0
T45	769	0	0	0
T49	0	233	0	0
T50	0	203	0	0
T52	666	0	0	0
T62	0	4	0	0
T72	491	0	0	0
T78	521	0	0	0
T150	0	42	0	0
T177	0	27967	0	0
T178	0	325	0	0
T179	0	22	0	0
T180	430	0	0	0
T181	422	0	0	0
T203	0	244	0	0
T207	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	29	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T44	3072	1	0	0
T45	769	0	0	0
T49	0	1	0	0
T50	0	3	0	0
T52	666	0	0	0
T72	491	0	0	0
T78	521	0	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	430	0	0	0
T181	422	0	0	0
T185	0	1	0	0
T191	0	1	0	0
T203	0	1	0	0
T207	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T2
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T2
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T8,T44,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T8,T44,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T8,T44,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T42,T44
1	0	Covered	T5,T6,T2
1	1	Covered	T8,T44,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T44,T45
0	1	Covered	T87,T217
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T44,T45
0	1	Covered	T44,T50,T218
1	0	Covered	T62,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T44,T45
1	-	Covered	T44,T50,T218

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T44,T45
DetectSt	168	Covered	T8,T44,T45
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T8,T44,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T44,T45
DebounceSt->IdleSt	163	Covered	T49,T172,T196
DetectSt->IdleSt	186	Covered	T87,T217
DetectSt->StableSt	191	Covered	T8,T44,T45
IdleSt->DebounceSt	148	Covered	T8,T44,T45
StableSt->IdleSt	206	Covered	T44,T50,T70

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T44,T45
0	1	Covered	T8,T44,T45
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T44,T45
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T44,T45
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T44,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T172,T196
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T44,T45
DetectSt	-	-	-	-	1	-	-	Covered	T87,T217
DetectSt	-	-	-	-	0	1	-	Covered	T8,T44,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T44,T50,T62
StableSt	-	-	-	-	-	-	0	Covered	T8,T44,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	79	0	0
CntIncr_A	8194048	12164	0	0
CntNoWrap_A	8194048	7548826	0	0
DetectStDropOut_A	8194048	2	0	0
DetectedOut_A	8194048	24355	0	0
DetectedPulseOut_A	8194048	36	0	0
DisabledIdleSt_A	8194048	7447937	0	0
DisabledNoDetection_A	8194048	7450292	0	0
EnterDebounceSt_A	8194048	41	0	0
EnterDetectSt_A	8194048	38	0	0
EnterStableSt_A	8194048	36	0	0
PulseIsPulse_A	8194048	36	0	0
StayInStableSt	8194048	24300	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8194048	6681	0	0
gen_low_level_sva.LowLevelEvent_A	8194048	7551311	0	0
gen_not_sticky_sva.StableStDropOut_A	8194048	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	79	0	0
T8	516	2	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T49	0	1	0	0
T50	0	4	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	2	0	0
T70	0	2	0	0
T87	0	2	0	0
T177	0	2	0	0
T218	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	12164	0	0
T8	516	58	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T44	0	73	0	0
T45	0	52	0	0
T49	0	78	0	0
T50	0	194	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	28	0	0
T70	0	81	0	0
T87	0	42	0	0
T177	0	9916	0	0
T218	0	112	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548826	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	2	0	0
T87	669	1	0	0
T217	0	1	0	0
T219	1575	0	0	0
T220	524	0	0	0
T221	31449	0	0	0
T222	40704	0	0	0
T223	1944	0	0	0
T224	528	0	0	0
T225	424	0	0	0
T226	495	0	0	0
T227	17675	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	24355	0	0
T8	516	45	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T44	0	134	0	0
T45	0	42	0	0
T50	0	76	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	5	0	0
T70	0	44	0	0
T177	0	21753	0	0
T178	0	46	0	0
T187	0	43	0	0
T218	0	262	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	36	0	0
T8	516	1	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	0	2	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	1	0	0
T70	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T187	0	1	0	0
T218	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7447937	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7450292	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	41	0	0
T8	516	1	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	1	0	0
T70	0	1	0	0
T87	0	1	0	0
T177	0	1	0	0
T218	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	38	0	0
T8	516	1	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	0	2	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	1	0	0
T70	0	1	0	0
T87	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T218	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	36	0	0
T8	516	1	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	0	2	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	1	0	0
T70	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T187	0	1	0	0
T218	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	36	0	0
T8	516	1	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	0	2	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	1	0	0
T70	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T187	0	1	0	0
T218	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	24300	0	0
T8	516	43	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T11	1454	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T31	38205	0	0	0
T44	0	133	0	0
T45	0	40	0	0
T50	0	73	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T62	0	4	0	0
T70	0	42	0	0
T177	0	21751	0	0
T178	0	44	0	0
T187	0	41	0	0
T218	0	259	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	6681	0	0
T1	509	0	0	0
T2	1112	1	0	0
T3	0	37	0	0
T5	501	7	0	0
T6	502	6	0	0
T7	404	0	0	0
T8	0	1	0	0
T14	969	0	0	0
T15	670	0	0	0
T16	402	0	0	0
T17	15312	30	0	0
T18	407	0	0	0
T20	0	3	0	0
T25	0	8	0	0
T27	0	4	0	0
T65	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	15	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T44	3072	1	0	0
T45	769	0	0	0
T50	0	1	0	0
T52	666	0	0	0
T72	491	0	0	0
T78	521	0	0	0
T141	0	1	0	0
T172	0	1	0	0
T180	430	0	0	0
T181	422	0	0	0
T184	0	2	0	0
T185	0	1	0	0
T188	0	1	0	0
T203	0	1	0	0
T209	0	1	0	0
T218	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T8,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T8,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T8,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T44
1	0	Covered	T5,T6,T1
1	1	Covered	T2,T8,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T44
0	1	Covered	T50,T107
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T44
0	1	Covered	T45,T50,T150
1	0	Covered	T62,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T44
1	-	Covered	T45,T50,T150

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T44
DetectSt	168	Covered	T2,T8,T44
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T8,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T44
DebounceSt->IdleSt	163	Covered	T2,T70,T218
DetectSt->IdleSt	186	Covered	T50,T107
DetectSt->StableSt	191	Covered	T2,T8,T44
IdleSt->DebounceSt	148	Covered	T2,T8,T44
StableSt->IdleSt	206	Covered	T44,T45,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T44
0	1	Covered	T2,T8,T44
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T44
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T44
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T70,T218
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T44
DetectSt	-	-	-	-	1	-	-	Covered	T50,T107
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T50,T150
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	153	0	0
CntIncr_A	8194048	10503	0	0
CntNoWrap_A	8194048	7548752	0	0
DetectStDropOut_A	8194048	2	0	0
DetectedOut_A	8194048	5828	0	0
DetectedPulseOut_A	8194048	70	0	0
DisabledIdleSt_A	8194048	7522420	0	0
DisabledNoDetection_A	8194048	7524768	0	0
EnterDebounceSt_A	8194048	83	0	0
EnterDetectSt_A	8194048	72	0	0
EnterStableSt_A	8194048	70	0	0
PulseIsPulse_A	8194048	70	0	0
StayInStableSt	8194048	5726	0	0
gen_high_level_sva.HighLevelEvent_A	8194048	7551311	0	0
gen_not_sticky_sva.StableStDropOut_A	8194048	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	153	0	0
T2	1112	3	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	2	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T47	0	2	0	0
T50	0	8	0	0
T56	0	2	0	0
T62	0	2	0	0
T64	412	0	0	0
T70	0	3	0	0
T150	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	10503	0	0
T2	1112	198	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	58	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	73	0	0
T45	0	52	0	0
T47	0	72	0	0
T50	0	216	0	0
T56	0	88	0	0
T62	0	28	0	0
T64	412	0	0	0
T70	0	180	0	0
T150	0	56	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548752	0	0
T1	509	108	0	0
T2	1112	708	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	2	0	0
T50	180438	1	0	0
T74	6354	0	0	0
T97	5168	0	0	0
T107	0	1	0	0
T147	509	0	0	0
T148	29272	0	0	0
T149	422	0	0	0
T150	732	0	0	0
T151	426	0	0	0
T152	21158	0	0	0
T153	8084	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	5828	0	0
T2	1112	38	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	46	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	382	0	0
T45	0	32	0	0
T47	0	124	0	0
T50	0	478	0	0
T56	0	339	0	0
T62	0	5	0	0
T64	412	0	0	0
T70	0	45	0	0
T150	0	225	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	70	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	3	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	1	0	0
T150	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7522420	0	0
T1	509	108	0	0
T2	1112	4	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7524768	0	0
T1	509	109	0	0
T2	1112	4	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	83	0	0
T2	1112	2	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	4	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	2	0	0
T150	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	72	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	4	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	1	0	0
T150	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	70	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	3	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	1	0	0
T150	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	70	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	3	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	1	0	0
T150	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	5726	0	0
T2	1112	36	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	44	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	380	0	0
T45	0	31	0	0
T47	0	122	0	0
T50	0	473	0	0
T56	0	337	0	0
T62	0	4	0	0
T64	412	0	0	0
T70	0	43	0	0
T150	0	222	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	36	0	0
T36	25826	0	0	0
T38	14442	0	0	0
T40	13386	0	0	0
T43	799	0	0	0
T45	769	1	0	0
T46	972	0	0	0
T50	0	1	0	0
T53	642	0	0	0
T87	0	1	0	0
T150	0	1	0	0
T188	0	1	0	0
T191	0	2	0	0
T192	0	2	0	0
T207	0	1	0	0
T218	0	1	0	0
T228	0	1	0	0
T229	869	0	0	0
T230	663	0	0	0
T231	421	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T45,T46,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T45,T46,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T45,T46,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T42,T45
1	0	Covered	T5,T6,T1
1	1	Covered	T45,T46,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T43
0	1	Covered	T182,T161
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T43
0	1	Covered	T46,T49,T50
1	0	Covered	T62,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T46,T43
1	-	Covered	T46,T49,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T45,T46,T43
DetectSt	168	Covered	T45,T46,T43
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T45,T46,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T45,T46,T43
DebounceSt->IdleSt	163	Covered	T186,T232
DetectSt->IdleSt	186	Covered	T182,T161
DetectSt->StableSt	191	Covered	T45,T46,T43
IdleSt->DebounceSt	148	Covered	T45,T46,T43
StableSt->IdleSt	206	Covered	T46,T49,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T45,T46,T43
0	1	Covered	T45,T46,T43
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T45,T46,T43
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T45,T46,T43
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T45,T46,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T186,T232
DebounceSt	-	0	0	-	-	-	-	Covered	T45,T46,T43
DetectSt	-	-	-	-	1	-	-	Covered	T182,T161
DetectSt	-	-	-	-	0	1	-	Covered	T45,T46,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T46,T49,T50
StableSt	-	-	-	-	-	-	0	Covered	T45,T46,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	90	0	0
CntIncr_A	8194048	46241	0	0
CntNoWrap_A	8194048	7548815	0	0
DetectStDropOut_A	8194048	2	0	0
DetectedOut_A	8194048	2642	0	0
DetectedPulseOut_A	8194048	42	0	0
DisabledIdleSt_A	8194048	7443975	0	0
DisabledNoDetection_A	8194048	7446326	0	0
EnterDebounceSt_A	8194048	46	0	0
EnterDetectSt_A	8194048	44	0	0
EnterStableSt_A	8194048	42	0	0
PulseIsPulse_A	8194048	42	0	0
StayInStableSt	8194048	2578	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8194048	6217	0	0
gen_low_level_sva.LowLevelEvent_A	8194048	7551311	0	0
gen_not_sticky_sva.StableStDropOut_A	8194048	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	90	0	0
T36	25826	0	0	0
T38	14442	0	0	0
T40	13386	0	0	0
T43	799	2	0	0
T45	769	2	0	0
T46	972	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	4	0	0
T53	642	0	0	0
T62	0	2	0	0
T70	0	2	0	0
T150	0	2	0	0
T207	0	2	0	0
T229	869	0	0	0
T230	663	0	0	0
T231	421	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	46241	0	0
T36	25826	0	0	0
T38	14442	0	0	0
T40	13386	0	0	0
T43	799	86	0	0
T45	769	52	0	0
T46	972	91	0	0
T48	0	66	0	0
T49	0	78	0	0
T50	0	108	0	0
T53	642	0	0	0
T62	0	28	0	0
T70	0	11	0	0
T150	0	28	0	0
T207	0	49	0	0
T229	869	0	0	0
T230	663	0	0	0
T231	421	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548815	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	2	0	0
T85	5924	0	0	0
T135	752	0	0	0
T161	0	1	0	0
T182	37512	1	0	0
T233	523	0	0	0
T234	524	0	0	0
T235	14022	0	0	0
T236	18428	0	0	0
T237	817	0	0	0
T238	403	0	0	0
T239	2729	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	2642	0	0
T36	25826	0	0	0
T38	14442	0	0	0
T40	13386	0	0	0
T43	799	255	0	0
T45	769	42	0	0
T46	972	44	0	0
T48	0	37	0	0
T49	0	54	0	0
T50	0	202	0	0
T53	642	0	0	0
T62	0	5	0	0
T70	0	60	0	0
T150	0	12	0	0
T207	0	98	0	0
T229	869	0	0	0
T230	663	0	0	0
T231	421	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	42	0	0
T36	25826	0	0	0
T38	14442	0	0	0
T40	13386	0	0	0
T43	799	1	0	0
T45	769	1	0	0
T46	972	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T53	642	0	0	0
T62	0	1	0	0
T70	0	1	0	0
T150	0	1	0	0
T207	0	1	0	0
T229	869	0	0	0
T230	663	0	0	0
T231	421	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7443975	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7446326	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	46	0	0
T36	25826	0	0	0
T38	14442	0	0	0
T40	13386	0	0	0
T43	799	1	0	0
T45	769	1	0	0
T46	972	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T53	642	0	0	0
T62	0	1	0	0
T70	0	1	0	0
T150	0	1	0	0
T207	0	1	0	0
T229	869	0	0	0
T230	663	0	0	0
T231	421	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	44	0	0
T36	25826	0	0	0
T38	14442	0	0	0
T40	13386	0	0	0
T43	799	1	0	0
T45	769	1	0	0
T46	972	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T53	642	0	0	0
T62	0	1	0	0
T70	0	1	0	0
T150	0	1	0	0
T207	0	1	0	0
T229	869	0	0	0
T230	663	0	0	0
T231	421	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	42	0	0
T36	25826	0	0	0
T38	14442	0	0	0
T40	13386	0	0	0
T43	799	1	0	0
T45	769	1	0	0
T46	972	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T53	642	0	0	0
T62	0	1	0	0
T70	0	1	0	0
T150	0	1	0	0
T207	0	1	0	0
T229	869	0	0	0
T230	663	0	0	0
T231	421	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	42	0	0
T36	25826	0	0	0
T38	14442	0	0	0
T40	13386	0	0	0
T43	799	1	0	0
T45	769	1	0	0
T46	972	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T53	642	0	0	0
T62	0	1	0	0
T70	0	1	0	0
T150	0	1	0	0
T207	0	1	0	0
T229	869	0	0	0
T230	663	0	0	0
T231	421	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	2578	0	0
T36	25826	0	0	0
T38	14442	0	0	0
T40	13386	0	0	0
T43	799	253	0	0
T45	769	40	0	0
T46	972	43	0	0
T48	0	35	0	0
T49	0	53	0	0
T50	0	200	0	0
T53	642	0	0	0
T62	0	4	0	0
T70	0	59	0	0
T150	0	11	0	0
T207	0	96	0	0
T229	869	0	0	0
T230	663	0	0	0
T231	421	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	6217	0	0
T1	509	1	0	0
T2	1112	1	0	0
T3	0	30	0	0
T4	0	1	0	0
T5	501	7	0	0
T6	502	5	0	0
T7	404	0	0	0
T14	969	0	0	0
T15	670	0	0	0
T16	402	0	0	0
T17	15312	35	0	0
T18	407	0	0	0
T20	0	3	0	0
T25	0	6	0	0
T27	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	18	0	0
T36	25826	0	0	0
T38	14442	0	0	0
T40	13386	0	0	0
T43	799	0	0	0
T46	972	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T53	642	0	0	0
T70	0	1	0	0
T81	5517	0	0	0
T107	0	1	0	0
T150	0	1	0	0
T172	0	1	0	0
T188	0	1	0	0
T203	0	1	0	0
T218	0	2	0	0
T229	869	0	0	0
T230	663	0	0	0
T231	421	0	0	0