Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T8,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T8,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T8,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T42
1	0	Covered	T5,T6,T1
1	1	Covered	T2,T8,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T42
0	1	Covered	T2,T44,T46
1	0	Covered	T62,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T42
1	-	Covered	T2,T44,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T42
DetectSt	168	Covered	T2,T8,T42
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T8,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T42
DebounceSt->IdleSt	163	Covered	T172,T173,T206
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T8,T42
IdleSt->DebounceSt	148	Covered	T2,T8,T42
StableSt->IdleSt	206	Covered	T2,T44,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T42
0	1	Covered	T2,T8,T42
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T42
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T42
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T172,T173,T206
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T44,T46
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	149	0	0
CntIncr_A	8194048	68010	0	0
CntNoWrap_A	8194048	7548756	0	0
DetectStDropOut_A	8194048	0	0	0
DetectedOut_A	8194048	8547	0	0
DetectedPulseOut_A	8194048	72	0	0
DisabledIdleSt_A	8194048	7371840	0	0
DisabledNoDetection_A	8194048	7374187	0	0
EnterDebounceSt_A	8194048	77	0	0
EnterDetectSt_A	8194048	72	0	0
EnterStableSt_A	8194048	72	0	0
PulseIsPulse_A	8194048	72	0	0
StayInStableSt	8194048	8441	0	0
gen_high_level_sva.HighLevelEvent_A	8194048	7551311	0	0
gen_not_sticky_sva.StableStDropOut_A	8194048	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	149	0	0
T2	1112	4	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	2	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	0	4	0	0
T47	0	4	0	0
T50	0	4	0	0
T56	0	6	0	0
T64	412	0	0	0
T118	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	68010	0	0
T2	1112	198	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	58	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	40	0	0
T43	0	86	0	0
T44	0	73	0	0
T46	0	182	0	0
T47	0	144	0	0
T50	0	108	0	0
T56	0	264	0	0
T64	412	0	0	0
T118	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548756	0	0
T1	509	108	0	0
T2	1112	707	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	8547	0	0
T2	1112	354	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	48	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	94	0	0
T43	0	38	0	0
T44	0	17	0	0
T46	0	203	0	0
T47	0	137	0	0
T50	0	385	0	0
T56	0	273	0	0
T64	412	0	0	0
T118	0	291	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	72	0	0
T2	1112	2	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T50	0	2	0	0
T56	0	3	0	0
T64	412	0	0	0
T118	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7371840	0	0
T1	509	108	0	0
T2	1112	4	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7374187	0	0
T1	509	109	0	0
T2	1112	4	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	77	0	0
T2	1112	2	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T50	0	2	0	0
T56	0	3	0	0
T64	412	0	0	0
T118	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	72	0	0
T2	1112	2	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T50	0	2	0	0
T56	0	3	0	0
T64	412	0	0	0
T118	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	72	0	0
T2	1112	2	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T50	0	2	0	0
T56	0	3	0	0
T64	412	0	0	0
T118	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	72	0	0
T2	1112	2	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T50	0	2	0	0
T56	0	3	0	0
T64	412	0	0	0
T118	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	8441	0	0
T2	1112	351	0	0
T3	19806	0	0	0
T4	724	0	0	0
T8	0	46	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	92	0	0
T43	0	36	0	0
T44	0	16	0	0
T46	0	200	0	0
T47	0	134	0	0
T50	0	382	0	0
T56	0	269	0	0
T64	412	0	0	0
T118	0	289	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	36	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	2	0	0
T64	412	0	0	0
T70	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T218	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T4,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T44
1	0	Covered	T5,T6,T1
1	1	Covered	T2,T4,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T44
0	1	Covered	T194
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T44
0	1	Covered	T2,T4,T45
1	0	Covered	T62,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T44
1	-	Covered	T2,T4,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T44
DetectSt	168	Covered	T2,T4,T44
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T4,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T44
DebounceSt->IdleSt	163	Covered	T56,T70,T172
DetectSt->IdleSt	186	Covered	T194
DetectSt->StableSt	191	Covered	T2,T4,T44
IdleSt->DebounceSt	148	Covered	T2,T4,T44
StableSt->IdleSt	206	Covered	T2,T4,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T44
0	1	Covered	T2,T4,T44
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T44
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T44
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T70,T240
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T44
DetectSt	-	-	-	-	1	-	-	Covered	T194
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T4,T45
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	81	0	0
CntIncr_A	8194048	22133	0	0
CntNoWrap_A	8194048	7548824	0	0
DetectStDropOut_A	8194048	1	0	0
DetectedOut_A	8194048	2487	0	0
DetectedPulseOut_A	8194048	38	0	0
DisabledIdleSt_A	8194048	7439787	0	0
DisabledNoDetection_A	8194048	7442137	0	0
EnterDebounceSt_A	8194048	44	0	0
EnterDetectSt_A	8194048	39	0	0
EnterStableSt_A	8194048	38	0	0
PulseIsPulse_A	8194048	38	0	0
StayInStableSt	8194048	2430	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8194048	6169	0	0
gen_low_level_sva.LowLevelEvent_A	8194048	7551311	0	0
gen_not_sticky_sva.StableStDropOut_A	8194048	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	81	0	0
T2	1112	2	0	0
T3	19806	0	0	0
T4	724	2	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	2	0	0
T45	0	4	0	0
T50	0	2	0	0
T56	0	3	0	0
T62	0	2	0	0
T64	412	0	0	0
T70	0	3	0	0
T150	0	2	0	0
T177	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	22133	0	0
T2	1112	99	0	0
T3	19806	0	0	0
T4	724	50	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	73	0	0
T45	0	104	0	0
T50	0	97	0	0
T56	0	176	0	0
T62	0	28	0	0
T64	412	0	0	0
T70	0	171	0	0
T150	0	28	0	0
T177	0	19832	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548824	0	0
T1	509	108	0	0
T2	1112	709	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	1	0	0
T107	34455	0	0	0
T194	60061	1	0	0
T241	764	0	0	0
T242	411	0	0	0
T243	422	0	0	0
T244	502	0	0	0
T245	6066	0	0	0
T246	1018	0	0	0
T247	1299	0	0	0
T248	8404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	2487	0	0
T2	1112	50	0	0
T3	19806	0	0	0
T4	724	121	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	41	0	0
T45	0	81	0	0
T50	0	159	0	0
T56	0	44	0	0
T62	0	4	0	0
T64	412	0	0	0
T70	0	142	0	0
T150	0	44	0	0
T177	0	84	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	38	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	1	0	0
T45	0	2	0	0
T50	0	1	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	1	0	0
T150	0	1	0	0
T177	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7439787	0	0
T1	509	108	0	0
T2	1112	4	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7442137	0	0
T1	509	109	0	0
T2	1112	4	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	44	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	1	0	0
T45	0	2	0	0
T50	0	1	0	0
T56	0	2	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	2	0	0
T150	0	1	0	0
T177	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	39	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	1	0	0
T45	0	2	0	0
T50	0	1	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	1	0	0
T150	0	1	0	0
T177	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	38	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	1	0	0
T45	0	2	0	0
T50	0	1	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	1	0	0
T150	0	1	0	0
T177	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	38	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	1	0	0
T45	0	2	0	0
T50	0	1	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	1	0	0
T150	0	1	0	0
T177	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	2430	0	0
T2	1112	49	0	0
T3	19806	0	0	0
T4	724	120	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	39	0	0
T45	0	78	0	0
T50	0	157	0	0
T56	0	43	0	0
T62	0	3	0	0
T64	412	0	0	0
T70	0	140	0	0
T150	0	42	0	0
T177	0	81	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	6169	0	0
T1	509	1	0	0
T2	1112	1	0	0
T3	0	28	0	0
T4	0	1	0	0
T5	501	4	0	0
T6	502	4	0	0
T7	404	0	0	0
T14	969	0	0	0
T15	670	0	0	0
T16	402	0	0	0
T17	15312	25	0	0
T18	407	0	0	0
T20	0	2	0	0
T25	0	9	0	0
T27	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	17	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T45	0	1	0	0
T56	0	1	0	0
T64	412	0	0	0
T162	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T177	0	1	0	0
T182	0	1	0	0
T249	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T42,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T4,T42,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T44,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T42,T44
1	0	Covered	T5,T6,T1
1	1	Covered	T4,T42,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T44,T45
0	1	Covered	T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T44,T45
0	1	Covered	T4,T44,T45
1	0	Covered	T62,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T44,T45
1	-	Covered	T4,T44,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T42,T44
DetectSt	168	Covered	T4,T44,T45
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T4,T44,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T44,T45
DebounceSt->IdleSt	163	Covered	T4,T42,T207
DetectSt->IdleSt	186	Covered	T88
DetectSt->StableSt	191	Covered	T4,T44,T45
IdleSt->DebounceSt	148	Covered	T4,T42,T44
StableSt->IdleSt	206	Covered	T4,T44,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T42,T44
0	1	Covered	T4,T42,T44
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T44,T45
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T42,T44
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T44,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T42,T207
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T42,T44
DetectSt	-	-	-	-	1	-	-	Covered	T88
DetectSt	-	-	-	-	0	1	-	Covered	T4,T44,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T44,T45
StableSt	-	-	-	-	-	-	0	Covered	T4,T44,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	153	0	0
CntIncr_A	8194048	63900	0	0
CntNoWrap_A	8194048	7548752	0	0
DetectStDropOut_A	8194048	1	0	0
DetectedOut_A	8194048	6147	0	0
DetectedPulseOut_A	8194048	72	0	0
DisabledIdleSt_A	8194048	7366867	0	0
DisabledNoDetection_A	8194048	7369213	0	0
EnterDebounceSt_A	8194048	81	0	0
EnterDetectSt_A	8194048	73	0	0
EnterStableSt_A	8194048	72	0	0
PulseIsPulse_A	8194048	72	0	0
StayInStableSt	8194048	6044	0	0
gen_high_level_sva.HighLevelEvent_A	8194048	7551311	0	0
gen_not_sticky_sva.StableStDropOut_A	8194048	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	153	0	0
T4	724	3	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T27	502	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T42	0	1	0	0
T44	0	4	0	0
T45	0	4	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	4	0	0
T50	0	2	0	0
T59	516	0	0	0
T64	412	0	0	0
T65	406	0	0	0
T150	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	63900	0	0
T4	724	100	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T27	502	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T42	0	40	0	0
T44	0	146	0	0
T45	0	104	0	0
T46	0	91	0	0
T47	0	72	0	0
T48	0	66	0	0
T49	0	156	0	0
T50	0	11	0	0
T59	516	0	0	0
T64	412	0	0	0
T65	406	0	0	0
T150	0	28	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548752	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	1	0	0
T84	5200	0	0	0
T88	88293	1	0	0
T187	559	0	0	0
T250	522	0	0	0
T251	100988	0	0	0
T252	506	0	0	0
T253	1998	0	0	0
T254	737	0	0	0
T255	16975	0	0	0
T256	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	6147	0	0
T4	724	28	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T27	502	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T44	0	216	0	0
T45	0	81	0	0
T46	0	164	0	0
T47	0	12	0	0
T48	0	37	0	0
T49	0	114	0	0
T50	0	72	0	0
T59	516	0	0	0
T64	412	0	0	0
T65	406	0	0	0
T70	0	154	0	0
T150	0	265	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	72	0	0
T4	724	1	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T27	502	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T59	516	0	0	0
T64	412	0	0	0
T65	406	0	0	0
T70	0	2	0	0
T150	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7366867	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7369213	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	81	0	0
T4	724	2	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T27	502	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T59	516	0	0	0
T64	412	0	0	0
T65	406	0	0	0
T150	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	73	0	0
T4	724	1	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T27	502	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T59	516	0	0	0
T64	412	0	0	0
T65	406	0	0	0
T70	0	2	0	0
T150	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	72	0	0
T4	724	1	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T27	502	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T59	516	0	0	0
T64	412	0	0	0
T65	406	0	0	0
T70	0	2	0	0
T150	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	72	0	0
T4	724	1	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T27	502	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T59	516	0	0	0
T64	412	0	0	0
T65	406	0	0	0
T70	0	2	0	0
T150	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	6044	0	0
T4	724	27	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T27	502	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T44	0	213	0	0
T45	0	78	0	0
T46	0	163	0	0
T47	0	11	0	0
T48	0	35	0	0
T49	0	111	0	0
T50	0	70	0	0
T59	516	0	0	0
T64	412	0	0	0
T65	406	0	0	0
T70	0	151	0	0
T150	0	263	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	39	0	0
T4	724	1	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T27	502	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T59	516	0	0	0
T64	412	0	0	0
T65	406	0	0	0
T70	0	1	0	0
T87	0	1	0	0
T177	0	1	0	0
T207	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T42,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T42,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T42,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T42,T43
1	0	Covered	T5,T6,T1
1	1	Covered	T2,T42,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T42,T43
0	1	Covered	T107
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T42,T43
0	1	Covered	T2,T56,T50
1	0	Covered	T62,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T42,T43
1	-	Covered	T2,T56,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T42,T43
DetectSt	168	Covered	T2,T42,T43
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T42,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T42,T43
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T107
DetectSt->StableSt	191	Covered	T2,T42,T43
IdleSt->DebounceSt	148	Covered	T2,T42,T43
StableSt->IdleSt	206	Covered	T2,T56,T50

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T42,T43
0	1	Covered	T2,T42,T43
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T42,T43
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T42,T43
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T42,T43
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T42,T43
DetectSt	-	-	-	-	1	-	-	Covered	T107
DetectSt	-	-	-	-	0	1	-	Covered	T2,T42,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T56,T50
StableSt	-	-	-	-	-	-	0	Covered	T2,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	94	0	0
CntIncr_A	8194048	2703	0	0
CntNoWrap_A	8194048	7548811	0	0
DetectStDropOut_A	8194048	1	0	0
DetectedOut_A	8194048	3664	0	0
DetectedPulseOut_A	8194048	46	0	0
DisabledIdleSt_A	8194048	7531212	0	0
DisabledNoDetection_A	8194048	7533566	0	0
EnterDebounceSt_A	8194048	47	0	0
EnterDetectSt_A	8194048	47	0	0
EnterStableSt_A	8194048	46	0	0
PulseIsPulse_A	8194048	46	0	0
StayInStableSt	8194048	3594	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8194048	6290	0	0
gen_low_level_sva.LowLevelEvent_A	8194048	7551311	0	0
gen_not_sticky_sva.StableStDropOut_A	8194048	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	94	0	0
T2	1112	2	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	2	0	0
T43	0	2	0	0
T47	0	2	0	0
T50	0	2	0	0
T56	0	6	0	0
T62	0	2	0	0
T64	412	0	0	0
T87	0	2	0	0
T187	0	2	0	0
T257	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	2703	0	0
T2	1112	99	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	40	0	0
T43	0	86	0	0
T47	0	72	0	0
T50	0	97	0	0
T56	0	264	0	0
T62	0	28	0	0
T64	412	0	0	0
T87	0	42	0	0
T187	0	13	0	0
T257	0	28	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548811	0	0
T1	509	108	0	0
T2	1112	709	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	1	0	0
T107	34455	1	0	0
T242	411	0	0	0
T243	422	0	0	0
T244	502	0	0	0
T245	6066	0	0	0
T246	1018	0	0	0
T247	1299	0	0	0
T248	8404	0	0	0
T258	1033	0	0	0
T259	524	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	3664	0	0
T2	1112	43	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	53	0	0
T43	0	125	0	0
T47	0	240	0	0
T50	0	39	0	0
T56	0	127	0	0
T62	0	4	0	0
T64	412	0	0	0
T87	0	39	0	0
T187	0	42	0	0
T257	0	170	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	46	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	3	0	0
T62	0	1	0	0
T64	412	0	0	0
T87	0	1	0	0
T187	0	1	0	0
T257	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7531212	0	0
T1	509	108	0	0
T2	1112	4	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7533566	0	0
T1	509	109	0	0
T2	1112	4	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	47	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	3	0	0
T62	0	1	0	0
T64	412	0	0	0
T87	0	1	0	0
T187	0	1	0	0
T257	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	47	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	3	0	0
T62	0	1	0	0
T64	412	0	0	0
T87	0	1	0	0
T187	0	1	0	0
T257	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	46	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	3	0	0
T62	0	1	0	0
T64	412	0	0	0
T87	0	1	0	0
T187	0	1	0	0
T257	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	46	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	3	0	0
T62	0	1	0	0
T64	412	0	0	0
T87	0	1	0	0
T187	0	1	0	0
T257	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	3594	0	0
T2	1112	42	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	51	0	0
T43	0	123	0	0
T47	0	238	0	0
T50	0	38	0	0
T56	0	123	0	0
T62	0	3	0	0
T64	412	0	0	0
T87	0	37	0	0
T187	0	40	0	0
T257	0	168	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	6290	0	0
T1	509	1	0	0
T2	1112	1	0	0
T3	0	26	0	0
T4	0	2	0	0
T5	501	7	0	0
T6	502	6	0	0
T7	404	0	0	0
T14	969	0	0	0
T15	670	0	0	0
T16	402	0	0	0
T17	15312	29	0	0
T18	407	0	0	0
T20	0	2	0	0
T25	0	5	0	0
T27	0	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	20	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	0	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T50	0	1	0	0
T56	0	2	0	0
T64	412	0	0	0
T107	0	1	0	0
T141	0	1	0	0
T161	0	1	0	0
T184	0	1	0	0
T186	0	1	0	0
T188	0	2	0	0
T192	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T2
1	1	Covered	T5,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T4,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T42
1	0	Covered	T5,T6,T17
1	1	Covered	T2,T4,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T44
0	1	Covered	T42,T196,T260
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T44
0	1	Covered	T4,T44,T56
1	0	Covered	T62,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T44
1	-	Covered	T4,T44,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T42
DetectSt	168	Covered	T2,T4,T42
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T4,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T42
DebounceSt->IdleSt	163	Covered	T2,T70,T261
DetectSt->IdleSt	186	Covered	T42,T196,T260
DetectSt->StableSt	191	Covered	T2,T4,T44
IdleSt->DebounceSt	148	Covered	T2,T4,T42
StableSt->IdleSt	206	Covered	T4,T44,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T42
0	1	Covered	T2,T4,T42
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T42
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T42
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T70,T261
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T42
DetectSt	-	-	-	-	1	-	-	Covered	T42,T196,T260
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T44,T56
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	133	0	0
CntIncr_A	8194048	23556	0	0
CntNoWrap_A	8194048	7548772	0	0
DetectStDropOut_A	8194048	3	0	0
DetectedOut_A	8194048	33657	0	0
DetectedPulseOut_A	8194048	61	0	0
DisabledIdleSt_A	8194048	7448564	0	0
DisabledNoDetection_A	8194048	7450920	0	0
EnterDebounceSt_A	8194048	69	0	0
EnterDetectSt_A	8194048	64	0	0
EnterStableSt_A	8194048	61	0	0
PulseIsPulse_A	8194048	61	0	0
StayInStableSt	8194048	33571	0	0
gen_high_level_sva.HighLevelEvent_A	8194048	7551311	0	0
gen_not_sticky_sva.StableStDropOut_A	8194048	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	133	0	0
T2	1112	3	0	0
T3	19806	0	0	0
T4	724	4	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	2	0	0
T44	0	4	0	0
T46	0	2	0	0
T56	0	4	0	0
T62	0	2	0	0
T64	412	0	0	0
T70	0	9	0	0
T87	0	4	0	0
T118	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	23556	0	0
T2	1112	198	0	0
T3	19806	0	0	0
T4	724	100	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	40	0	0
T44	0	146	0	0
T46	0	91	0	0
T56	0	176	0	0
T62	0	28	0	0
T64	412	0	0	0
T70	0	274	0	0
T87	0	84	0	0
T118	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548772	0	0
T1	509	108	0	0
T2	1112	708	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	3	0	0
T24	1804	0	0	0
T32	805	0	0	0
T35	11796	0	0	0
T42	543	1	0	0
T44	3072	0	0	0
T52	666	0	0	0
T72	491	0	0	0
T78	521	0	0	0
T180	430	0	0	0
T181	422	0	0	0
T196	0	1	0	0
T260	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	33657	0	0
T2	1112	38	0	0
T3	19806	0	0	0
T4	724	82	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	216	0	0
T46	0	38	0	0
T56	0	230	0	0
T62	0	5	0	0
T64	412	0	0	0
T70	0	89	0	0
T87	0	131	0	0
T118	0	1	0	0
T177	0	29227	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	61	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	2	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	2	0	0
T46	0	1	0	0
T56	0	2	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	4	0	0
T87	0	2	0	0
T118	0	1	0	0
T177	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7448564	0	0
T1	509	108	0	0
T2	1112	4	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7450920	0	0
T1	509	109	0	0
T2	1112	4	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	69	0	0
T2	1112	2	0	0
T3	19806	0	0	0
T4	724	2	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T56	0	2	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	5	0	0
T87	0	2	0	0
T118	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	64	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	2	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T56	0	2	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	4	0	0
T87	0	2	0	0
T118	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	61	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	2	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	2	0	0
T46	0	1	0	0
T56	0	2	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	4	0	0
T87	0	2	0	0
T118	0	1	0	0
T177	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	61	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	2	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	2	0	0
T46	0	1	0	0
T56	0	2	0	0
T62	0	1	0	0
T64	412	0	0	0
T70	0	4	0	0
T87	0	2	0	0
T118	0	1	0	0
T177	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	33571	0	0
T2	1112	36	0	0
T3	19806	0	0	0
T4	724	79	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T44	0	213	0	0
T46	0	36	0	0
T56	0	228	0	0
T62	0	4	0	0
T64	412	0	0	0
T70	0	85	0	0
T87	0	128	0	0
T177	0	29224	0	0
T257	0	113	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	34	0	0
T4	724	1	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	0	0	0
T27	502	0	0	0
T28	522	0	0	0
T30	593	0	0	0
T44	0	1	0	0
T56	0	2	0	0
T59	516	0	0	0
T64	412	0	0	0
T65	406	0	0	0
T70	0	4	0	0
T87	0	1	0	0
T118	0	1	0	0
T177	0	1	0	0
T179	0	1	0	0
T188	0	1	0	0
T257	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T2
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T2
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T4,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T4,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Covered	T5,T6,T17
1	1	Covered	T2,T4,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T42
0	1	Covered	T2,T4,T56
1	0	Covered	T62,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T42
1	-	Covered	T2,T4,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T42
DetectSt	168	Covered	T2,T4,T42
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T4,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T42
DebounceSt->IdleSt	163	Covered	T172
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T4,T42
IdleSt->DebounceSt	148	Covered	T2,T4,T42
StableSt->IdleSt	206	Covered	T2,T4,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T42
0	1	Covered	T2,T4,T42
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T42
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T42
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T172
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T4,T56
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	121	0	0
CntIncr_A	8194048	13358	0	0
CntNoWrap_A	8194048	7548784	0	0
DetectStDropOut_A	8194048	0	0	0
DetectedOut_A	8194048	14466	0	0
DetectedPulseOut_A	8194048	60	0	0
DisabledIdleSt_A	8194048	7349314	0	0
DisabledNoDetection_A	8194048	7351653	0	0
EnterDebounceSt_A	8194048	61	0	0
EnterDetectSt_A	8194048	60	0	0
EnterStableSt_A	8194048	60	0	0
PulseIsPulse_A	8194048	60	0	0
StayInStableSt	8194048	14375	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8194048	6970	0	0
gen_low_level_sva.LowLevelEvent_A	8194048	7551311	0	0
gen_not_sticky_sva.StableStDropOut_A	8194048	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	121	0	0
T2	1112	2	0	0
T3	19806	0	0	0
T4	724	2	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	2	0	0
T43	0	2	0	0
T47	0	2	0	0
T50	0	2	0	0
T56	0	4	0	0
T64	412	0	0	0
T70	0	10	0	0
T118	0	2	0	0
T150	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	13358	0	0
T2	1112	99	0	0
T3	19806	0	0	0
T4	724	50	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	40	0	0
T43	0	86	0	0
T47	0	72	0	0
T50	0	11	0	0
T56	0	176	0	0
T64	412	0	0	0
T70	0	274	0	0
T118	0	70	0	0
T150	0	28	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7548784	0	0
T1	509	108	0	0
T2	1112	709	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	14466	0	0
T2	1112	215	0	0
T3	19806	0	0	0
T4	724	30	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	52	0	0
T43	0	126	0	0
T47	0	40	0	0
T50	0	73	0	0
T56	0	99	0	0
T64	412	0	0	0
T70	0	231	0	0
T118	0	38	0	0
T150	0	83	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	60	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	2	0	0
T64	412	0	0	0
T70	0	5	0	0
T118	0	1	0	0
T150	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7349314	0	0
T1	509	108	0	0
T2	1112	4	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7351653	0	0
T1	509	109	0	0
T2	1112	4	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	61	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	2	0	0
T64	412	0	0	0
T70	0	5	0	0
T118	0	1	0	0
T150	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	60	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	2	0	0
T64	412	0	0	0
T70	0	5	0	0
T118	0	1	0	0
T150	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	60	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	2	0	0
T64	412	0	0	0
T70	0	5	0	0
T118	0	1	0	0
T150	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	60	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	2	0	0
T64	412	0	0	0
T70	0	5	0	0
T118	0	1	0	0
T150	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	14375	0	0
T2	1112	214	0	0
T3	19806	0	0	0
T4	724	29	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T42	0	50	0	0
T43	0	124	0	0
T47	0	38	0	0
T50	0	71	0	0
T56	0	96	0	0
T64	412	0	0	0
T70	0	223	0	0
T118	0	36	0	0
T150	0	81	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	6970	0	0
T1	509	0	0	0
T2	1112	1	0	0
T3	0	31	0	0
T4	0	1	0	0
T5	501	5	0	0
T6	502	3	0	0
T7	404	0	0	0
T9	0	15	0	0
T14	969	0	0	0
T15	670	0	0	0
T16	402	0	0	0
T17	15312	37	0	0
T18	407	0	0	0
T20	0	1	0	0
T25	0	7	0	0
T27	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	27	0	0
T2	1112	1	0	0
T3	19806	0	0	0
T4	724	1	0	0
T16	402	0	0	0
T17	15312	0	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T56	0	1	0	0
T64	412	0	0	0
T70	0	2	0	0
T177	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T257	0	1	0	0