Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T3,T10
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T17,T3,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T17,T3,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T17,T3,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T3,T10
1	0	Covered	T17,T3,T10
1	1	Covered	T17,T3,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T3,T10
0	1	Covered	T17,T81,T39
1	0	Covered	T17,T39,T62

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T35
0	1	Covered	T3,T10,T35
1	0	Covered	T63,T90

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T35
1	-	Covered	T3,T10,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T3,T10
DetectSt	168	Covered	T17,T3,T10
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T3,T10,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T3,T10
DebounceSt->IdleSt	163	Covered	T62,T235,T263
DetectSt->IdleSt	186	Covered	T17,T81,T39
DetectSt->StableSt	191	Covered	T3,T10,T35
IdleSt->DebounceSt	148	Covered	T17,T3,T10
StableSt->IdleSt	206	Covered	T3,T10,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T17,T3,T10
0	1	Covered	T17,T3,T10
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T3,T10
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T17,T3,T10
IdleSt	0	-	-	-	-	-	-	Covered	T17,T3,T10
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T3,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T62,T235,T263
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T3,T10
DetectSt	-	-	-	-	1	-	-	Covered	T17,T81,T39
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T35
DetectSt	-	-	-	-	0	0	-	Covered	T17,T3,T10
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T35
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T35
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	2908	0	0
CntIncr_A	8194048	114097	0	0
CntNoWrap_A	8194048	7545997	0	0
DetectStDropOut_A	8194048	332	0	0
DetectedOut_A	8194048	89170	0	0
DetectedPulseOut_A	8194048	870	0	0
DisabledIdleSt_A	8194048	7023369	0	0
DisabledNoDetection_A	8194048	7025559	0	0
EnterDebounceSt_A	8194048	1475	0	0
EnterDetectSt_A	8194048	1434	0	0
EnterStableSt_A	8194048	870	0	0
PulseIsPulse_A	8194048	870	0	0
StayInStableSt	8194048	88175	0	0
gen_high_event_sva.HighLevelEvent_A	8194048	7551311	0	0
gen_high_level_sva.HighLevelEvent_A	8194048	7551311	0	0
gen_not_sticky_sva.StableStDropOut_A	8194048	741	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	2908	0	0
T3	19806	12	0	0
T4	724	0	0	0
T10	0	18	0	0
T17	15312	60	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T27	502	0	0	0
T35	0	50	0	0
T36	0	54	0	0
T37	0	24	0	0
T38	0	48	0	0
T39	0	8	0	0
T64	412	0	0	0
T65	406	0	0	0
T81	0	50	0	0
T82	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	114097	0	0
T3	19806	282	0	0
T4	724	0	0	0
T10	0	324	0	0
T17	15312	1523	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T27	502	0	0	0
T35	0	975	0	0
T36	0	1539	0	0
T37	0	840	0	0
T38	0	1968	0	0
T39	0	251	0	0
T64	412	0	0	0
T65	406	0	0	0
T81	0	1448	0	0
T82	0	1032	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7545997	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14811	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	332	0	0
T3	19806	0	0	0
T4	724	0	0	0
T17	15312	11	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T27	502	0	0	0
T39	0	2	0	0
T64	412	0	0	0
T65	406	0	0	0
T81	0	25	0	0
T97	0	11	0	0
T100	0	14	0	0
T101	0	27	0	0
T103	0	22	0	0
T104	0	6	0	0
T263	0	1	0	0
T283	0	18	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	89170	0	0
T3	19806	217	0	0
T4	724	0	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	533	0	0
T25	496	0	0	0
T27	502	0	0	0
T30	593	0	0	0
T35	0	1413	0	0
T36	0	4221	0	0
T37	0	1393	0	0
T38	0	3005	0	0
T64	412	0	0	0
T65	406	0	0	0
T82	0	1238	0	0
T152	0	3821	0	0
T153	0	119	0	0
T267	0	822	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	870	0	0
T3	19806	6	0	0
T4	724	0	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	9	0	0
T25	496	0	0	0
T27	502	0	0	0
T30	593	0	0	0
T35	0	25	0	0
T36	0	27	0	0
T37	0	12	0	0
T38	0	24	0	0
T64	412	0	0	0
T65	406	0	0	0
T82	0	12	0	0
T152	0	24	0	0
T153	0	14	0	0
T267	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7023369	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	12151	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7025559	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	12155	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	1475	0	0
T3	19806	6	0	0
T4	724	0	0	0
T10	0	9	0	0
T17	15312	30	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T27	502	0	0	0
T35	0	25	0	0
T36	0	27	0	0
T37	0	12	0	0
T38	0	24	0	0
T39	0	4	0	0
T64	412	0	0	0
T65	406	0	0	0
T81	0	25	0	0
T82	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	1434	0	0
T3	19806	6	0	0
T4	724	0	0	0
T10	0	9	0	0
T17	15312	30	0	0
T18	407	0	0	0
T19	816	0	0	0
T20	422	0	0	0
T25	496	0	0	0
T27	502	0	0	0
T35	0	25	0	0
T36	0	27	0	0
T37	0	12	0	0
T38	0	24	0	0
T39	0	4	0	0
T64	412	0	0	0
T65	406	0	0	0
T81	0	25	0	0
T82	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	870	0	0
T3	19806	6	0	0
T4	724	0	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	9	0	0
T25	496	0	0	0
T27	502	0	0	0
T30	593	0	0	0
T35	0	25	0	0
T36	0	27	0	0
T37	0	12	0	0
T38	0	24	0	0
T64	412	0	0	0
T65	406	0	0	0
T82	0	12	0	0
T152	0	24	0	0
T153	0	14	0	0
T267	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	870	0	0
T3	19806	6	0	0
T4	724	0	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	9	0	0
T25	496	0	0	0
T27	502	0	0	0
T30	593	0	0	0
T35	0	25	0	0
T36	0	27	0	0
T37	0	12	0	0
T38	0	24	0	0
T64	412	0	0	0
T65	406	0	0	0
T82	0	12	0	0
T152	0	24	0	0
T153	0	14	0	0
T267	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	88175	0	0
T3	19806	210	0	0
T4	724	0	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	523	0	0
T25	496	0	0	0
T27	502	0	0	0
T30	593	0	0	0
T35	0	1388	0	0
T36	0	4189	0	0
T37	0	1374	0	0
T38	0	2979	0	0
T64	412	0	0	0
T65	406	0	0	0
T82	0	1223	0	0
T152	0	3794	0	0
T153	0	105	0	0
T267	0	804	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	741	0	0
T3	19806	5	0	0
T4	724	0	0	0
T8	516	0	0	0
T9	710855	0	0	0
T10	17295	8	0	0
T25	496	0	0	0
T27	502	0	0	0
T30	593	0	0	0
T35	0	25	0	0
T36	0	22	0	0
T37	0	5	0	0
T38	0	22	0	0
T64	412	0	0	0
T65	406	0	0	0
T82	0	9	0	0
T152	0	21	0	0
T153	0	14	0	0
T267	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T3,T10
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T3,T10
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T51,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T10,T51,T38

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T51,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T51
1	0	Covered	T17,T3,T10
1	1	Covered	T10,T51,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T51,T38
0	1	Covered	T83,T48,T275
1	0	Covered	T62,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T51,T38
0	1	Covered	T51,T38,T36
1	0	Covered	T62,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T51,T38
1	-	Covered	T51,T38,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T51,T38
DetectSt	168	Covered	T10,T51,T38
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T10,T51,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T51,T38
DebounceSt->IdleSt	163	Covered	T83,T48,T275
DetectSt->IdleSt	186	Covered	T83,T48,T275
DetectSt->StableSt	191	Covered	T10,T51,T38
IdleSt->DebounceSt	148	Covered	T10,T51,T38
StableSt->IdleSt	206	Covered	T10,T51,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T51,T38
0	1	Covered	T10,T51,T38
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T51,T38
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T51,T38
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T51,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T83,T48,T275
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T51,T38
DetectSt	-	-	-	-	1	-	-	Covered	T83,T48,T275
DetectSt	-	-	-	-	0	1	-	Covered	T10,T51,T38
DetectSt	-	-	-	-	0	0	-	Covered	T10,T51,T38
StableSt	-	-	-	-	-	-	1	Covered	T51,T38,T36
StableSt	-	-	-	-	-	-	0	Covered	T10,T51,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8194048	941	0	0
CntIncr_A	8194048	52868	0	0
CntNoWrap_A	8194048	7547964	0	0
DetectStDropOut_A	8194048	75	0	0
DetectedOut_A	8194048	16578	0	0
DetectedPulseOut_A	8194048	361	0	0
DisabledIdleSt_A	8194048	7139730	0	0
DisabledNoDetection_A	8194048	7141335	0	0
EnterDebounceSt_A	8194048	503	0	0
EnterDetectSt_A	8194048	441	0	0
EnterStableSt_A	8194048	361	0	0
PulseIsPulse_A	8194048	361	0	0
StayInStableSt	8194048	16180	0	0
gen_high_level_sva.HighLevelEvent_A	8194048	7551311	0	0
gen_not_sticky_sva.StableStDropOut_A	8194048	322	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	941	0	0
T10	17295	2	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T31	38205	0	0	0
T36	0	8	0	0
T37	0	6	0	0
T38	0	2	0	0
T40	0	6	0	0
T48	0	5	0	0
T51	26891	2	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T80	0	26	0	0
T83	0	9	0	0
T128	404	0	0	0
T275	0	27	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	52868	0	0
T10	17295	45	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T31	38205	0	0	0
T36	0	240	0	0
T37	0	138	0	0
T38	0	70	0	0
T40	0	513	0	0
T48	0	439	0	0
T51	26891	68	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T80	0	1404	0	0
T83	0	569	0	0
T128	404	0	0	0
T275	0	2166	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7547964	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	75	0	0
T37	22253	0	0	0
T39	14898	0	0	0
T41	0	7	0	0
T48	0	1	0	0
T56	0	1	0	0
T66	1895	0	0	0
T67	1560	0	0	0
T73	497	0	0	0
T79	502	0	0	0
T83	14090	4	0	0
T102	0	2	0	0
T265	426	0	0	0
T266	583	0	0	0
T269	0	12	0	0
T275	0	13	0	0
T278	0	4	0	0
T282	402	0	0	0
T284	0	3	0	0
T285	0	12	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	16578	0	0
T10	17295	68	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T31	38205	0	0	0
T36	0	995	0	0
T37	0	231	0	0
T38	0	162	0	0
T40	0	49	0	0
T41	0	82	0	0
T51	26891	4	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T80	0	951	0	0
T114	0	35	0	0
T128	404	0	0	0
T276	0	339	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	361	0	0
T10	17295	1	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T31	38205	0	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T40	0	3	0	0
T41	0	1	0	0
T51	26891	1	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T80	0	13	0	0
T114	0	4	0	0
T128	404	0	0	0
T276	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7139730	0	0
T1	509	108	0	0
T2	1112	711	0	0
T5	501	100	0	0
T6	502	101	0	0
T7	404	3	0	0
T14	969	568	0	0
T15	670	269	0	0
T16	402	1	0	0
T17	15312	14871	0	0
T18	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7141335	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	503	0	0
T10	17295	1	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T31	38205	0	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T40	0	3	0	0
T48	0	4	0	0
T51	26891	1	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T80	0	13	0	0
T83	0	5	0	0
T128	404	0	0	0
T275	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	441	0	0
T10	17295	1	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T31	38205	0	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T40	0	3	0	0
T48	0	2	0	0
T51	26891	1	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T80	0	13	0	0
T83	0	4	0	0
T128	404	0	0	0
T275	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	361	0	0
T10	17295	1	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T31	38205	0	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T40	0	3	0	0
T41	0	1	0	0
T51	26891	1	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T80	0	13	0	0
T114	0	4	0	0
T128	404	0	0	0
T276	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	361	0	0
T10	17295	1	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T31	38205	0	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T40	0	3	0	0
T41	0	1	0	0
T51	26891	1	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T80	0	13	0	0
T114	0	4	0	0
T128	404	0	0	0
T276	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	16180	0	0
T10	17295	66	0	0
T11	1454	0	0	0
T12	504	0	0	0
T28	522	0	0	0
T31	38205	0	0	0
T36	0	988	0	0
T37	0	228	0	0
T38	0	161	0	0
T40	0	46	0	0
T41	0	81	0	0
T51	26891	3	0	0
T59	516	0	0	0
T60	425	0	0	0
T61	422	0	0	0
T80	0	938	0	0
T114	0	31	0	0
T128	404	0	0	0
T276	0	333	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	7551311	0	0
T1	509	109	0	0
T2	1112	712	0	0
T5	501	101	0	0
T6	502	102	0	0
T7	404	4	0	0
T14	969	569	0	0
T15	670	270	0	0
T16	402	2	0	0
T17	15312	14876	0	0
T18	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8194048	322	0	0
T13	512	0	0	0
T26	491	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T40	0	3	0	0
T41	0	1	0	0
T51	26891	1	0	0
T71	502	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T77	502	0	0	0
T80	0	13	0	0
T82	0	3	0	0
T114	0	4	0	0
T128	404	0	0	0
T134	447	0	0	0
T274	422	0	0	0
T276	0	6	0	0