Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T10,T11
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T10,T11
0	1	Covered	T11,T85,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T10,T11
0	1	Covered	T4,T10,T11
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T10,T11
1	-	Covered	T4,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T10,T11
DetectSt	168	Covered	T4,T10,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T4,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T10,T11
DebounceSt->IdleSt	163	Covered	T4,T10,T33
DetectSt->IdleSt	186	Covered	T11,T85,T91
DetectSt->StableSt	191	Covered	T4,T10,T11
IdleSt->DebounceSt	148	Covered	T4,T10,T11
StableSt->IdleSt	206	Covered	T4,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T10,T11
0	1	Covered	T4,T10,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T10,T33
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T11,T85,T91
DetectSt	-	-	-	-	0	1	-	Covered	T4,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T4,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	290	0	0
CntIncr_A	8367630	179141	0	0
CntNoWrap_A	8367630	7688305	0	0
DetectStDropOut_A	8367630	3	0	0
DetectedOut_A	8367630	877	0	0
DetectedPulseOut_A	8367630	129	0	0
DisabledIdleSt_A	8367630	7502646	0	0
DisabledNoDetection_A	8367630	7505067	0	0
EnterDebounceSt_A	8367630	162	0	0
EnterDetectSt_A	8367630	132	0	0
EnterStableSt_A	8367630	129	0	0
PulseIsPulse_A	8367630	129	0	0
StayInStableSt	8367630	747	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8367630	7343	0	0
gen_low_level_sva.LowLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	128	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	290	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	3	0	0
T5	506	0	0	0
T6	7683	0	0	0
T10	0	7	0	0
T11	0	6	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	179141	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	53	0	0
T5	506	0	0	0
T6	7683	0	0	0
T10	0	519	0	0
T11	0	231	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	50	0	0
T34	0	1964	0	0
T40	0	94	0	0
T41	0	22	0	0
T43	0	87	0	0
T44	0	26	0	0
T45	0	15	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7688305	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	4512	0	0
T4	669	265	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	3	0	0
T11	9861	1	0	0
T12	2246	0	0	0
T28	27116	0	0	0
T33	54983	0	0	0
T39	8094	0	0	0
T40	747	0	0	0
T53	1286	0	0	0
T54	1004	0	0	0
T60	522	0	0	0
T85	0	1	0	0
T91	0	1	0	0
T94	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	877	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	11	0	0
T5	506	0	0	0
T6	7683	0	0	0
T10	0	16	0	0
T11	0	8	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	2	0	0
T34	0	8	0	0
T40	0	6	0	0
T43	0	8	0	0
T44	0	6	0	0
T45	0	6	0	0
T101	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	129	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	1	0	0
T5	506	0	0	0
T6	7683	0	0	0
T10	0	3	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T101	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7502646	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	4512	0	0
T4	669	121	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7505067	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	121	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	162	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	2	0	0
T5	506	0	0	0
T6	7683	0	0	0
T10	0	5	0	0
T11	0	3	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	3	0	0
T34	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	132	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	1	0	0
T5	506	0	0	0
T6	7683	0	0	0
T10	0	3	0	0
T11	0	3	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T101	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	129	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	1	0	0
T5	506	0	0	0
T6	7683	0	0	0
T10	0	3	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T101	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	129	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	1	0	0
T5	506	0	0	0
T6	7683	0	0	0
T10	0	3	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T101	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	747	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	10	0	0
T5	506	0	0	0
T6	7683	0	0	0
T10	0	13	0	0
T11	0	5	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	1	0	0
T34	0	7	0	0
T40	0	5	0	0
T43	0	7	0	0
T44	0	5	0	0
T45	0	5	0	0
T102	0	7	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7343	0	0
T1	134786	26	0	0
T2	37113	42	0	0
T3	13606	52	0	0
T4	669	3	0	0
T5	506	5	0	0
T6	0	30	0	0
T13	522	4	0	0
T14	421	3	0	0
T15	522	6	0	0
T16	430	2	0	0
T17	689	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	128	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	1	0	0
T5	506	0	0	0
T6	7683	0	0	0
T10	0	3	0	0
T11	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T101	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T12,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T33
0	1	Covered	T33,T71,T77
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T33
0	1	Unreachable
1	0	Covered	T1,T12,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T11
DetectSt	168	Covered	T1,T12,T33
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T12,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T33
DebounceSt->IdleSt	163	Covered	T10,T11,T53
DetectSt->IdleSt	186	Covered	T33,T71,T77
DetectSt->StableSt	191	Covered	T1,T12,T33
IdleSt->DebounceSt	148	Covered	T1,T10,T11
StableSt->IdleSt	206	Covered	T1,T12,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T11
0	1	Covered	T1,T10,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T33
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T11,T53
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T33,T71,T77
DetectSt	-	-	-	-	0	1	-	Covered	T1,T12,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T12,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T12,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	197	0	0
CntIncr_A	8367630	289941	0	0
CntNoWrap_A	8367630	7688398	0	0
DetectStDropOut_A	8367630	14	0	0
DetectedOut_A	8367630	7260	0	0
DetectedPulseOut_A	8367630	44	0	0
DisabledIdleSt_A	8367630	6076101	0	0
DisabledNoDetection_A	8367630	6078573	0	0
EnterDebounceSt_A	8367630	139	0	0
EnterDetectSt_A	8367630	58	0	0
EnterStableSt_A	8367630	44	0	0
PulseIsPulse_A	8367630	44	0	0
StayInStableSt	8367630	7216	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8367630	7343	0	0
gen_low_level_sva.LowLevelEvent_A	8367630	7691069	0	0
gen_sticky_sva.StableStDropOut_A	8367630	896212	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	197	0	0
T1	134786	2	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	2	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	9	0	0
T38	0	2	0	0
T41	0	2	0	0
T53	0	3	0	0
T55	0	5	0	0
T63	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	289941	0	0
T1	134786	99	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	192	0	0
T11	0	108	0	0
T12	0	27	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	47306	0	0
T38	0	138	0	0
T41	0	62	0	0
T53	0	111	0	0
T55	0	460	0	0
T63	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7688398	0	0
T1	134786	129562	0	0
T2	37113	36684	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	14	0	0
T33	54983	3	0	0
T40	747	0	0	0
T41	6914	0	0	0
T71	0	1	0	0
T77	0	1	0	0
T111	0	3	0	0
T112	0	2	0	0
T113	0	2	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	422	0	0	0
T117	882	0	0	0
T118	555	0	0	0
T119	426	0	0	0
T120	422	0	0	0
T121	422	0	0	0
T122	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7260	0	0
T1	134786	193	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T12	0	114	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	1	0	0
T63	0	246	0	0
T71	0	91	0	0
T77	0	1	0	0
T105	0	439	0	0
T106	0	27	0	0
T109	0	143	0	0
T110	0	454	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	44	0	0
T1	134786	1	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T12	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	1	0	0
T63	0	2	0	0
T71	0	1	0	0
T77	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T109	0	1	0	0
T110	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	6076101	0	0
T1	134786	9318	0	0
T2	37113	36684	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	6078573	0	0
T1	134786	9335	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	139	0	0
T1	134786	1	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	2	0	0
T11	0	4	0	0
T12	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	5	0	0
T38	0	2	0	0
T41	0	2	0	0
T53	0	3	0	0
T55	0	5	0	0
T63	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	58	0	0
T1	134786	1	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T12	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	4	0	0
T63	0	2	0	0
T71	0	2	0	0
T77	0	2	0	0
T105	0	1	0	0
T106	0	1	0	0
T109	0	1	0	0
T110	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	44	0	0
T1	134786	1	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T12	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	1	0	0
T63	0	2	0	0
T71	0	1	0	0
T77	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T109	0	1	0	0
T110	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	44	0	0
T1	134786	1	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T12	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	1	0	0
T63	0	2	0	0
T71	0	1	0	0
T77	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T109	0	1	0	0
T110	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7216	0	0
T1	134786	192	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T12	0	113	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T63	0	244	0	0
T71	0	90	0	0
T72	0	173	0	0
T105	0	438	0	0
T106	0	26	0	0
T109	0	142	0	0
T110	0	452	0	0
T123	0	113	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7343	0	0
T1	134786	26	0	0
T2	37113	42	0	0
T3	13606	52	0	0
T4	669	3	0	0
T5	506	5	0	0
T6	0	30	0	0
T13	522	4	0	0
T14	421	3	0	0
T15	522	6	0	0
T16	430	2	0	0
T17	689	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	896212	0	0
T1	134786	119945	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T12	0	195	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	140	0	0
T63	0	532	0	0
T71	0	98	0	0
T77	0	93	0	0
T105	0	269	0	0
T106	0	47	0	0
T109	0	455	0	0
T110	0	429	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T1,T12,T76
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Unreachable
1	0	Covered	T10,T11,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T11
DetectSt	168	Covered	T1,T10,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T10,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T11
DebounceSt->IdleSt	163	Covered	T1,T33,T41
DetectSt->IdleSt	186	Covered	T1,T12,T76
DetectSt->StableSt	191	Covered	T10,T11,T12
IdleSt->DebounceSt	148	Covered	T1,T10,T11
StableSt->IdleSt	206	Covered	T10,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T11
0	1	Covered	T1,T10,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T33,T63
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T1,T12,T76
DetectSt	-	-	-	-	0	1	-	Covered	T10,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T11,T12
StableSt	-	-	-	-	-	-	0	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	186	0	0
CntIncr_A	8367630	241120	0	0
CntNoWrap_A	8367630	7688409	0	0
DetectStDropOut_A	8367630	15	0	0
DetectedOut_A	8367630	116016	0	0
DetectedPulseOut_A	8367630	50	0	0
DisabledIdleSt_A	8367630	6076101	0	0
DisabledNoDetection_A	8367630	6078573	0	0
EnterDebounceSt_A	8367630	121	0	0
EnterDetectSt_A	8367630	65	0	0
EnterStableSt_A	8367630	50	0	0
PulseIsPulse_A	8367630	50	0	0
StayInStableSt	8367630	115966	0	0
gen_high_level_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_sticky_sva.StableStDropOut_A	8367630	772401	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	186	0	0
T1	134786	3	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	4	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	3	0	0
T38	0	2	0	0
T41	0	2	0	0
T53	0	4	0	0
T55	0	4	0	0
T63	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	241120	0	0
T1	134786	126	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	31	0	0
T11	0	67	0	0
T12	0	100	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	150	0	0
T38	0	66	0	0
T41	0	62	0	0
T53	0	44	0	0
T55	0	186	0	0
T63	0	640	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7688409	0	0
T1	134786	129561	0	0
T2	37113	36684	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	15	0	0
T1	134786	1	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T12	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T76	0	4	0	0
T104	0	2	0	0
T111	0	3	0	0
T112	0	2	0	0
T114	0	1	0	0
T124	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	116016	0	0
T10	11956	73	0	0
T11	9861	223	0	0
T12	2246	156	0	0
T23	4716	0	0	0
T33	0	207	0	0
T39	8094	0	0	0
T53	1286	85	0	0
T54	1004	0	0	0
T55	0	660	0	0
T60	522	0	0	0
T94	502	0	0	0
T103	428	0	0	0
T104	0	91	0	0
T106	0	45	0	0
T107	0	64823	0	0
T108	0	531	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	50	0	0
T10	11956	1	0	0
T11	9861	1	0	0
T12	2246	1	0	0
T23	4716	0	0	0
T33	0	1	0	0
T39	8094	0	0	0
T53	1286	2	0	0
T54	1004	0	0	0
T55	0	2	0	0
T60	522	0	0	0
T94	502	0	0	0
T103	428	0	0	0
T104	0	2	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	6076101	0	0
T1	134786	9318	0	0
T2	37113	36684	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	6078573	0	0
T1	134786	9335	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	121	0	0
T1	134786	2	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	2	0	0
T38	0	2	0	0
T41	0	2	0	0
T53	0	2	0	0
T55	0	2	0	0
T63	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	65	0	0
T1	134786	1	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	1	0	0
T53	0	2	0	0
T55	0	2	0	0
T76	0	4	0	0
T104	0	4	0	0
T106	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	50	0	0
T10	11956	1	0	0
T11	9861	1	0	0
T12	2246	1	0	0
T23	4716	0	0	0
T33	0	1	0	0
T39	8094	0	0	0
T53	1286	2	0	0
T54	1004	0	0	0
T55	0	2	0	0
T60	522	0	0	0
T94	502	0	0	0
T103	428	0	0	0
T104	0	2	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	50	0	0
T10	11956	1	0	0
T11	9861	1	0	0
T12	2246	1	0	0
T23	4716	0	0	0
T33	0	1	0	0
T39	8094	0	0	0
T53	1286	2	0	0
T54	1004	0	0	0
T55	0	2	0	0
T60	522	0	0	0
T94	502	0	0	0
T103	428	0	0	0
T104	0	2	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	115966	0	0
T10	11956	72	0	0
T11	9861	222	0	0
T12	2246	155	0	0
T23	4716	0	0	0
T33	0	206	0	0
T39	8094	0	0	0
T53	1286	83	0	0
T54	1004	0	0	0
T55	0	658	0	0
T60	522	0	0	0
T94	502	0	0	0
T103	428	0	0	0
T104	0	89	0	0
T106	0	44	0	0
T107	0	64822	0	0
T108	0	530	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	772401	0	0
T10	11956	329	0	0
T11	9861	227	0	0
T12	2246	66	0	0
T23	4716	0	0	0
T33	0	325	0	0
T39	8094	0	0	0
T53	1286	324	0	0
T54	1004	0	0	0
T55	0	139	0	0
T60	522	0	0	0
T94	502	0	0	0
T103	428	0	0	0
T104	0	787	0	0
T106	0	30	0	0
T107	0	451	0	0
T108	0	234784	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T11
0	1	Covered	T71,T72,T73
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T11
0	1	Unreachable
1	0	Covered	T1,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T11
DetectSt	168	Covered	T1,T10,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T11
DebounceSt->IdleSt	163	Covered	T53,T33,T41
DetectSt->IdleSt	186	Covered	T71,T72,T73
DetectSt->StableSt	191	Covered	T1,T10,T11
IdleSt->DebounceSt	148	Covered	T1,T10,T11
StableSt->IdleSt	206	Covered	T1,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T11
0	1	Covered	T1,T10,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T53,T33,T55
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T71,T72,T73
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	187	0	0
CntIncr_A	8367630	604169	0	0
CntNoWrap_A	8367630	7688408	0	0
DetectStDropOut_A	8367630	13	0	0
DetectedOut_A	8367630	554652	0	0
DetectedPulseOut_A	8367630	48	0	0
DisabledIdleSt_A	8367630	6076101	0	0
DisabledNoDetection_A	8367630	6078573	0	0
EnterDebounceSt_A	8367630	126	0	0
EnterDetectSt_A	8367630	61	0	0
EnterStableSt_A	8367630	48	0	0
PulseIsPulse_A	8367630	48	0	0
StayInStableSt	8367630	554604	0	0
gen_high_event_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_high_level_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_sticky_sva.StableStDropOut_A	8367630	360266	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	187	0	0
T1	134786	2	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	5	0	0
T38	0	2	0	0
T41	0	2	0	0
T53	0	5	0	0
T55	0	5	0	0
T63	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	604169	0	0
T1	134786	41392	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	67	0	0
T11	0	78	0	0
T12	0	26	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	298	0	0
T38	0	68	0	0
T41	0	64	0	0
T53	0	240	0	0
T55	0	105	0	0
T63	0	408	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7688408	0	0
T1	134786	129562	0	0
T2	37113	36684	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	13	0	0
T71	723	4	0	0
T72	0	1	0	0
T73	0	3	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	2	0	0
T129	526	0	0	0
T130	402	0	0	0
T131	2728	0	0	0
T132	525	0	0	0
T133	655	0	0	0
T134	8028	0	0	0
T135	526	0	0	0
T136	421	0	0	0
T137	432	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	554652	0	0
T1	134786	78811	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	188	0	0
T11	0	322	0	0
T12	0	156	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T38	0	162	0	0
T104	0	437	0	0
T105	0	622	0	0
T106	0	5	0	0
T107	0	402	0	0
T108	0	57588	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	48	0	0
T1	134786	1	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T38	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	6076101	0	0
T1	134786	9318	0	0
T2	37113	36684	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	6078573	0	0
T1	134786	9335	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	126	0	0
T1	134786	1	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T33	0	5	0	0
T38	0	1	0	0
T41	0	2	0	0
T53	0	5	0	0
T55	0	5	0	0
T63	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	61	0	0
T1	134786	1	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T38	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	48	0	0
T1	134786	1	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T38	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	48	0	0
T1	134786	1	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T38	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	554604	0	0
T1	134786	78810	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	187	0	0
T11	0	321	0	0
T12	0	155	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T38	0	161	0	0
T104	0	435	0	0
T105	0	621	0	0
T106	0	4	0	0
T107	0	401	0	0
T108	0	57587	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	360266	0	0
T1	134786	36	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	191	0	0
T11	0	121	0	0
T12	0	156	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T38	0	151	0	0
T104	0	729	0	0
T105	0	91	0	0
T106	0	137	0	0
T107	0	84335	0	0
T108	0	169468	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T41,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T41,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T34,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T41
1	0	Covered	T1,T4,T5
1	1	Covered	T3,T41,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T34,T38
0	1	Covered	T36,T138
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T34,T38
0	1	Covered	T3,T34,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T34,T38
1	-	Covered	T3,T34,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T41,T34
DetectSt	168	Covered	T3,T34,T36
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T34,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T34,T36
DebounceSt->IdleSt	163	Covered	T41,T36,T139
DetectSt->IdleSt	186	Covered	T36,T138
DetectSt->StableSt	191	Covered	T3,T34,T38
IdleSt->DebounceSt	148	Covered	T3,T41,T34
StableSt->IdleSt	206	Covered	T3,T34,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T41,T34
0	1	Covered	T3,T41,T34
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T34,T36
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T41,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T34,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T41,T34
DetectSt	-	-	-	-	1	-	-	Covered	T36,T138
DetectSt	-	-	-	-	0	1	-	Covered	T3,T34,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T34,T38
StableSt	-	-	-	-	-	-	0	Covered	T3,T34,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	72	0	0
CntIncr_A	8367630	22192	0	0
CntNoWrap_A	8367630	7688523	0	0
DetectStDropOut_A	8367630	2	0	0
DetectedOut_A	8367630	39094	0	0
DetectedPulseOut_A	8367630	32	0	0
DisabledIdleSt_A	8367630	7558690	0	0
DisabledNoDetection_A	8367630	7561109	0	0
EnterDebounceSt_A	8367630	39	0	0
EnterDetectSt_A	8367630	34	0	0
EnterStableSt_A	8367630	32	0	0
PulseIsPulse_A	8367630	32	0	0
StayInStableSt	8367630	39045	0	0
gen_high_level_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	72	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T34	0	2	0	0
T36	0	3	0	0
T38	0	6	0	0
T41	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T74	0	4	0	0
T140	0	4	0	0
T141	0	2	0	0
T142	0	2	0	0
T143	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	22192	0	0
T3	13606	63	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T34	0	70	0	0
T36	0	92	0	0
T38	0	214	0	0
T41	0	29	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T74	0	114	0	0
T139	0	4986	0	0
T140	0	26	0	0
T141	0	99	0	0
T142	0	65	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7688523	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	4510	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	2	0	0
T36	829	1	0	0
T37	29817	0	0	0
T58	496	0	0	0
T59	490	0	0	0
T95	2966	0	0	0
T96	422	0	0	0
T101	625	0	0	0
T102	699	0	0	0
T138	0	1	0	0
T144	501	0	0	0
T145	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	39094	0	0
T3	13606	41	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T34	0	40	0	0
T38	0	496	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T74	0	235	0	0
T75	0	167	0	0
T140	0	73	0	0
T141	0	60	0	0
T142	0	42	0	0
T143	0	40	0	0
T146	0	219	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	32	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T34	0	1	0	0
T38	0	3	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T74	0	2	0	0
T75	0	2	0	0
T140	0	2	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T146	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7558690	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	3947	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7561109	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	3972	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	39	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T38	0	3	0	0
T41	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T74	0	2	0	0
T139	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0
T142	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	34	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T38	0	3	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T74	0	2	0	0
T75	0	2	0	0
T140	0	2	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	32	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T34	0	1	0	0
T38	0	3	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T74	0	2	0	0
T75	0	2	0	0
T140	0	2	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T146	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	32	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T34	0	1	0	0
T38	0	3	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T74	0	2	0	0
T75	0	2	0	0
T140	0	2	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T146	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	39045	0	0
T3	13606	40	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T34	0	39	0	0
T38	0	491	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T74	0	232	0	0
T75	0	163	0	0
T140	0	71	0	0
T141	0	58	0	0
T142	0	41	0	0
T143	0	38	0	0
T146	0	218	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	15	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T74	0	1	0	0
T138	0	1	0	0
T140	0	2	0	0
T142	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T10,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T10,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T10,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T33
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T10,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T33
0	1	Covered	T10,T61,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T33
1	-	Covered	T10,T61,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T33
DetectSt	168	Covered	T3,T10,T33
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T10,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T33
DebounceSt->IdleSt	163	Covered	T3,T41,T34
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T10,T33
IdleSt->DebounceSt	148	Covered	T3,T10,T33
StableSt->IdleSt	206	Covered	T3,T10,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T10,T33
0	1	Covered	T3,T10,T33
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T33
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T34,T140
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T61,T36
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	139	0	0
CntIncr_A	8367630	65411	0	0
CntNoWrap_A	8367630	7688456	0	0
DetectStDropOut_A	8367630	0	0	0
DetectedOut_A	8367630	6183	0	0
DetectedPulseOut_A	8367630	66	0	0
DisabledIdleSt_A	8367630	7455144	0	0
DisabledNoDetection_A	8367630	7457562	0	0
EnterDebounceSt_A	8367630	74	0	0
EnterDetectSt_A	8367630	66	0	0
EnterStableSt_A	8367630	66	0	0
PulseIsPulse_A	8367630	66	0	0
StayInStableSt	8367630	6085	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8367630	2824	0	0
gen_low_level_sva.LowLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	139	0	0
T3	13606	3	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	4	0	0
T33	0	2	0	0
T34	0	3	0	0
T36	0	6	0	0
T37	0	2	0	0
T38	0	2	0	0
T41	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	2	0	0
T149	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	65411	0	0
T3	13606	126	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	112	0	0
T33	0	56	0	0
T34	0	140	0	0
T36	0	138	0	0
T37	0	44	0	0
T38	0	26	0	0
T41	0	30	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	30	0	0
T149	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7688456	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	4509	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	6183	0	0
T3	13606	156	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	142	0	0
T33	0	133	0	0
T34	0	54	0	0
T36	0	122	0	0
T37	0	113	0	0
T38	0	119	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	54	0	0
T140	0	90	0	0
T149	0	99	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	66	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	1	0	0
T140	0	2	0	0
T149	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7455144	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	3947	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7457562	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	3972	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	74	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	1	0	0
T149	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	66	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	1	0	0
T140	0	2	0	0
T149	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	66	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	1	0	0
T140	0	2	0	0
T149	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	66	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	1	0	0
T140	0	2	0	0
T149	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	6085	0	0
T3	13606	154	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	140	0	0
T33	0	131	0	0
T34	0	52	0	0
T36	0	118	0	0
T37	0	111	0	0
T38	0	118	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	53	0	0
T140	0	87	0	0
T149	0	97	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	2824	0	0
T1	134786	21	0	0
T2	37113	0	0	0
T3	13606	44	0	0
T4	669	0	0	0
T5	506	4	0	0
T7	0	18	0	0
T13	522	6	0	0
T14	421	4	0	0
T15	522	4	0	0
T16	430	1	0	0
T17	689	0	0	0
T46	0	2	0	0
T47	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	34	0	0
T10	11956	2	0	0
T11	9861	0	0	0
T12	2246	0	0	0
T23	4716	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	8094	0	0	0
T53	1286	0	0	0
T54	1004	0	0	0
T60	522	0	0	0
T61	0	1	0	0
T68	0	1	0	0
T72	0	2	0	0
T75	0	2	0	0
T94	502	0	0	0
T103	428	0	0	0
T140	0	1	0	0
T146	0	1	0	0
T150	0	1	0	0