Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.09	100.00	95.01		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	89.26	93.48	85.71		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	90.61	95.65	85.71		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	90.61	95.65	85.71		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	90.61	95.65	85.71		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	90.61	95.65	85.71		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	90.69	95.65	85.71		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	96.66	97.83	90.48		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
90.69	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
89.26	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
96.66	97.83

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
90.61	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
90.61	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
90.61	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
90.61	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T37,T64,T65
1	0	Covered	T41,T66

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T66,T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
90.69	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
89.26	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
96.66	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T3,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T3,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T3,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T3,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T3,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T3,T8
0	1	Covered	T11,T36,T68
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T3,T8
0	1	Covered	T4,T3,T8
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T3,T8
1	-	Covered	T4,T3,T8

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T23
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T23
1	0	Covered	T2,T6,T39
1	1	Covered	T2,T6,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T39
0	1	Covered	T23,T39,T41
1	0	Covered	T39,T41,T29

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T39
0	1	Covered	T2,T6,T39
1	0	Covered	T41,T69,T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T39
1	-	Covered	T2,T6,T39

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T11
0	1	Covered	T71,T72,T73
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T11
0	1	Unreachable
1	0	Covered	T1,T10,T11

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
90.61	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
90.61	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
90.61	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
90.61	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T3,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T36,T74,T75
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T8
1	-	Covered	T3,T7,T8

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T1,T12,T76
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Unreachable
1	0	Covered	T10,T11,T12

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T12,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T33
0	1	Covered	T33,T71,T77
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T33
0	1	Unreachable
1	0	Covered	T1,T12,T33

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T3,T8
DetectSt	168	Covered	T4,T3,T8
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T4,T3,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T3,T8
DebounceSt->IdleSt	163	Covered	T4,T3,T10
DetectSt->IdleSt	186	Covered	T1,T11,T12
DetectSt->StableSt	191	Covered	T4,T3,T8
IdleSt->DebounceSt	148	Covered	T4,T3,T8
StableSt->IdleSt	206	Covered	T4,T3,T8

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
90.69	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.26	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
96.66	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
90.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
90.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
90.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
90.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T3,T8
0	1	Covered	T4,T3,T8
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T3,T8
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T3,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T3,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T3,T10
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T3,T8
DetectSt	-	-	-	-	1	-	-	Covered	T1,T11,T12
DetectSt	-	-	-	-	0	1	-	Covered	T4,T3,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T4,T3,T8
StableSt	-	-	-	-	-	-	0	Covered	T4,T3,T8
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T53,T33
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T6
DetectSt	-	-	-	-	1	-	-	Covered	T23,T39,T41
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T6
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T39
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T6
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T6
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	217558380	18539	0	0
CntIncr_A	217558380	2947824	0	0
CntNoWrap_A	217558380	199884931	0	0
DetectStDropOut_A	217558380	2130	0	0
DetectedOut_A	217558380	1916387	0	0
DetectedPulseOut_A	217558380	6121	0	0
DisabledIdleSt_A	217558380	187047212	0	0
DisabledNoDetection_A	217558380	187106871	0	0
EnterDebounceSt_A	217558380	9600	0	0
EnterDetectSt_A	217558380	8962	0	0
EnterStableSt_A	217558380	6121	0	0
PulseIsPulse_A	217558380	6121	0	0
StayInStableSt	217558380	1909274	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	75308670	54574	0	0
gen_high_event_sva.HighLevelEvent_A	41838150	38455345	0	0
gen_high_level_sva.HighLevelEvent_A	142249710	130748173	0	0
gen_low_level_sva.LowLevelEvent_A	75308670	69219621	0	0
gen_not_sticky_sva.StableStDropOut_A	192455490	4935	0	0
gen_sticky_sva.StableStDropOut_A	25102890	2028879	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217558380	18539	0	0
T1	943502	4	0	0
T2	445356	33	0	0
T3	353756	2	0	0
T4	5352	3	0	0
T5	4048	0	0	0
T6	145977	26	0	0
T7	75150	0	0	0
T8	27524	0	0	0
T10	0	9	0	0
T11	0	8	0	0
T13	4176	0	0	0
T14	3368	0	0	0
T15	6264	0	0	0
T16	5160	0	0	0
T17	8268	0	0	0
T23	0	30	0	0
T28	0	24	0	0
T29	0	38	0	0
T30	0	30	0	0
T31	0	30	0	0
T33	0	6	0	0
T34	0	2	0	0
T39	0	26	0	0
T40	0	2	0	0
T41	0	25	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	7596	0	0	0
T47	7704	0	0	0
T48	9828	0	0	0
T49	5908	0	0	0
T50	8456	0	0	0
T51	9576	0	0	0
T78	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217558380	2947824	0	0
T1	943502	181	0	0
T2	445356	952	0	0
T3	353756	25	0	0
T4	5352	53	0	0
T5	4048	0	0	0
T6	145977	819	0	0
T7	75150	0	0	0
T8	27524	0	0	0
T10	0	544	0	0
T11	0	256	0	0
T13	4176	0	0	0
T14	3368	0	0	0
T15	6264	0	0	0
T16	5160	0	0	0
T17	8268	0	0	0
T23	0	989	0	0
T28	0	986	0	0
T29	0	956	0	0
T30	0	720	0	0
T31	0	780	0	0
T33	0	75	0	0
T34	0	1964	0	0
T39	0	559	0	0
T40	0	94	0	0
T41	0	764	0	0
T43	0	87	0	0
T44	0	26	0	0
T45	0	15	0	0
T46	7596	0	0	0
T47	7704	0	0	0
T48	9828	0	0	0
T49	5908	0	0	0
T50	8456	0	0	0
T51	9576	0	0	0
T78	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217558380	199884931	0	0
T1	3504436	3368645	0	0
T2	964938	953613	0	0
T3	353756	117249	0	0
T4	17394	6965	0	0
T5	13156	2730	0	0
T13	13572	3146	0	0
T14	10946	520	0	0
T15	13572	3146	0	0
T16	11180	754	0	0
T17	17914	7488	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217558380	2130	0	0
T11	19722	1	0	0
T12	4492	0	0	0
T23	4716	7	0	0
T28	54232	0	0	0
T33	54983	0	0	0
T37	29817	1	0	0
T38	324527	0	0	0
T39	16188	0	0	0
T40	747	0	0	0
T41	0	1	0	0
T53	2572	0	0	0
T54	2008	0	0	0
T59	490	0	0	0
T60	1044	0	0	0
T62	9037	0	0	0
T66	0	1	0	0
T72	0	3	0	0
T79	0	10	0	0
T80	0	14	0	0
T81	0	11	0	0
T82	0	4	0	0
T83	0	8	0	0
T84	0	11	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	2	0	0
T88	0	2	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	0	2	0	0
T94	1004	0	0	0
T95	2966	0	0	0
T96	422	0	0	0
T97	1063	0	0	0
T98	857	0	0	0
T99	526	0	0	0
T100	761	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217558380	1916387	0	0
T1	673930	35	0	0
T2	371130	2218	0	0
T3	326544	3	0	0
T4	4014	11	0	0
T5	3036	0	0	0
T6	145977	137	0	0
T7	75150	0	0	0
T8	27524	0	0	0
T10	11956	19	0	0
T11	0	12	0	0
T13	3132	0	0	0
T14	2526	0	0	0
T15	5220	0	0	0
T16	4300	0	0	0
T17	6890	0	0	0
T23	4716	0	0	0
T28	0	1205	0	0
T29	0	962	0	0
T30	0	808	0	0
T31	0	1598	0	0
T33	0	5	0	0
T34	0	8	0	0
T39	0	474	0	0
T40	0	6	0	0
T41	0	493	0	0
T43	0	8	0	0
T44	0	6	0	0
T45	0	6	0	0
T46	7596	0	0	0
T47	7704	0	0	0
T48	9828	0	0	0
T49	5908	0	0	0
T50	8456	0	0	0
T51	9576	0	0	0
T78	0	3	0	0
T101	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217558380	6121	0	0
T1	673930	2	0	0
T2	371130	16	0	0
T3	326544	1	0	0
T4	4014	1	0	0
T5	3036	0	0	0
T6	145977	13	0	0
T7	75150	0	0	0
T8	27524	0	0	0
T10	11956	4	0	0
T11	0	3	0	0
T13	3132	0	0	0
T14	2526	0	0	0
T15	5220	0	0	0
T16	4300	0	0	0
T17	6890	0	0	0
T23	4716	0	0	0
T28	0	12	0	0
T29	0	19	0	0
T30	0	15	0	0
T31	0	15	0	0
T33	0	2	0	0
T34	0	1	0	0
T39	0	13	0	0
T40	0	1	0	0
T41	0	6	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	7596	0	0	0
T47	7704	0	0	0
T48	9828	0	0	0
T49	5908	0	0	0
T50	8456	0	0	0
T51	9576	0	0	0
T78	0	1	0	0
T101	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217558380	187047212	0	0
T1	3504436	3003952	0	0
T2	964938	922012	0	0
T3	353756	105731	0	0
T4	17394	6821	0	0
T5	13156	2730	0	0
T13	13572	3146	0	0
T14	10946	520	0	0
T15	13572	3146	0	0
T16	11180	754	0	0
T17	17914	7488	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217558380	187106871	0	0
T1	3504436	3004385	0	0
T2	964938	922322	0	0
T3	353756	106385	0	0
T4	17394	6846	0	0
T5	13156	2756	0	0
T13	13572	3172	0	0
T14	10946	546	0	0
T15	13572	3172	0	0
T16	11180	780	0	0
T17	17914	7514	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217558380	9600	0	0
T1	943502	2	0	0
T2	445356	17	0	0
T3	353756	1	0	0
T4	5352	2	0	0
T5	4048	0	0	0
T6	145977	13	0	0
T7	75150	0	0	0
T8	27524	0	0	0
T10	0	6	0	0
T11	0	4	0	0
T13	4176	0	0	0
T14	3368	0	0	0
T15	6264	0	0	0
T16	5160	0	0	0
T17	8268	0	0	0
T23	0	23	0	0
T28	0	12	0	0
T29	0	19	0	0
T30	0	15	0	0
T31	0	15	0	0
T33	0	4	0	0
T34	0	1	0	0
T39	0	13	0	0
T40	0	1	0	0
T41	0	15	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	7596	0	0	0
T47	7704	0	0	0
T48	9828	0	0	0
T49	5908	0	0	0
T50	8456	0	0	0
T51	9576	0	0	0
T78	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217558380	8962	0	0
T1	943502	2	0	0
T2	445356	16	0	0
T3	353756	1	0	0
T4	5352	1	0	0
T5	4048	0	0	0
T6	145977	13	0	0
T7	75150	0	0	0
T8	27524	0	0	0
T10	0	4	0	0
T11	0	4	0	0
T13	4176	0	0	0
T14	3368	0	0	0
T15	6264	0	0	0
T16	5160	0	0	0
T17	8268	0	0	0
T23	0	7	0	0
T28	0	12	0	0
T29	0	19	0	0
T30	0	15	0	0
T33	0	2	0	0
T34	0	1	0	0
T39	0	13	0	0
T40	0	1	0	0
T41	0	10	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	7596	0	0	0
T47	7704	0	0	0
T48	9828	0	0	0
T49	5908	0	0	0
T50	8456	0	0	0
T51	9576	0	0	0
T78	0	1	0	0
T101	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217558380	6121	0	0
T1	673930	2	0	0
T2	371130	16	0	0
T3	326544	1	0	0
T4	4014	1	0	0
T5	3036	0	0	0
T6	145977	13	0	0
T7	75150	0	0	0
T8	27524	0	0	0
T10	11956	4	0	0
T11	0	3	0	0
T13	3132	0	0	0
T14	2526	0	0	0
T15	5220	0	0	0
T16	4300	0	0	0
T17	6890	0	0	0
T23	4716	0	0	0
T28	0	12	0	0
T29	0	19	0	0
T30	0	15	0	0
T31	0	15	0	0
T33	0	2	0	0
T34	0	1	0	0
T39	0	13	0	0
T40	0	1	0	0
T41	0	6	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	7596	0	0	0
T47	7704	0	0	0
T48	9828	0	0	0
T49	5908	0	0	0
T50	8456	0	0	0
T51	9576	0	0	0
T78	0	1	0	0
T101	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217558380	6121	0	0
T1	673930	2	0	0
T2	371130	16	0	0
T3	326544	1	0	0
T4	4014	1	0	0
T5	3036	0	0	0
T6	145977	13	0	0
T7	75150	0	0	0
T8	27524	0	0	0
T10	11956	4	0	0
T11	0	3	0	0
T13	3132	0	0	0
T14	2526	0	0	0
T15	5220	0	0	0
T16	4300	0	0	0
T17	6890	0	0	0
T23	4716	0	0	0
T28	0	12	0	0
T29	0	19	0	0
T30	0	15	0	0
T31	0	15	0	0
T33	0	2	0	0
T34	0	1	0	0
T39	0	13	0	0
T40	0	1	0	0
T41	0	6	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	7596	0	0	0
T47	7704	0	0	0
T48	9828	0	0	0
T49	5908	0	0	0
T50	8456	0	0	0
T51	9576	0	0	0
T78	0	1	0	0
T101	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	217558380	1909274	0	0
T1	673930	33	0	0
T2	371130	2194	0	0
T3	326544	2	0	0
T4	4014	10	0	0
T5	3036	0	0	0
T6	145977	124	0	0
T7	75150	0	0	0
T8	27524	0	0	0
T10	11956	15	0	0
T11	0	8	0	0
T13	3132	0	0	0
T14	2526	0	0	0
T15	5220	0	0	0
T16	4300	0	0	0
T17	6890	0	0	0
T23	4716	0	0	0
T28	0	1190	0	0
T29	0	941	0	0
T30	0	792	0	0
T31	0	1581	0	0
T33	0	3	0	0
T34	0	7	0	0
T39	0	461	0	0
T40	0	5	0	0
T41	0	487	0	0
T43	0	7	0	0
T44	0	5	0	0
T45	0	5	0	0
T46	7596	0	0	0
T47	7704	0	0	0
T48	9828	0	0	0
T49	5908	0	0	0
T50	8456	0	0	0
T51	9576	0	0	0
T78	0	2	0	0
T102	0	7	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75308670	54574	0	0
T1	1213074	236	0	0
T2	334017	251	0	0
T3	122454	441	0	0
T4	6021	9	0	0
T5	4554	45	0	0
T6	0	200	0	0
T7	0	38	0	0
T13	4698	45	0	0
T14	3789	25	0	0
T15	4698	46	0	0
T16	3870	27	0	0
T17	6201	4	0	0
T46	0	12	0	0
T47	0	4	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41838150	38455345	0	0
T1	673930	647905	0	0
T2	185565	183495	0	0
T3	68030	22690	0	0
T4	3345	1345	0	0
T5	2530	530	0	0
T13	2610	610	0	0
T14	2105	105	0	0
T15	2610	610	0	0
T16	2150	150	0	0
T17	3445	1445	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142249710	130748173	0	0
T1	2291362	2202877	0	0
T2	630921	623883	0	0
T3	231302	77146	0	0
T4	11373	4573	0	0
T5	8602	1802	0	0
T13	8874	2074	0	0
T14	7157	357	0	0
T15	8874	2074	0	0
T16	7310	510	0	0
T17	11713	4913	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75308670	69219621	0	0
T1	1213074	1166229	0	0
T2	334017	330291	0	0
T3	122454	40842	0	0
T4	6021	2421	0	0
T5	4554	954	0	0
T13	4698	1098	0	0
T14	3789	189	0	0
T15	4698	1098	0	0
T16	3870	270	0	0
T17	6201	2601	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192455490	4935	0	0
T1	539144	2	0	0
T2	334017	8	0	0
T3	122454	1	0	0
T4	3345	1	0	0
T5	2530	0	0	0
T6	38415	13	0	0
T7	16700	0	0	0
T10	11956	4	0	0
T11	9861	2	0	0
T12	2246	0	0	0
T13	2610	0	0	0
T14	2105	0	0	0
T15	4698	0	0	0
T16	3870	0	0	0
T17	6201	0	0	0
T23	4716	0	0	0
T28	0	9	0	0
T29	0	17	0	0
T30	0	15	0	0
T33	0	2	0	0
T34	0	1	0	0
T39	0	13	0	0
T40	0	1	0	0
T41	0	5	0	0
T42	0	4	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	1688	0	0	0
T47	1712	0	0	0
T48	2184	0	0	0
T60	522	0	0	0
T78	0	1	0	0
T101	0	1	0	0
T103	428	0	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25102890	2028879	0	0
T1	269572	119981	0	0
T2	74226	0	0	0
T3	27212	0	0	0
T4	1338	0	0	0
T5	1012	0	0	0
T10	11956	520	0	0
T11	9861	348	0	0
T12	2246	417	0	0
T13	1044	0	0	0
T14	842	0	0	0
T15	1044	0	0	0
T16	860	0	0	0
T17	1378	0	0	0
T23	4716	0	0	0
T33	0	465	0	0
T38	0	151	0	0
T39	8094	0	0	0
T53	1286	324	0	0
T54	1004	0	0	0
T55	0	139	0	0
T60	522	0	0	0
T63	0	532	0	0
T71	0	98	0	0
T77	0	93	0	0
T94	502	0	0	0
T103	428	0	0	0
T104	0	1516	0	0
T105	0	360	0	0
T106	0	214	0	0
T107	0	84786	0	0
T108	0	404252	0	0
T109	0	455	0	0
T110	0	429	0	0