Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Covered	T1,T4,T5
1	1	Covered	T3,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T3,T10,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T9
1	-	Covered	T3,T10,T37

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T9
DetectSt	168	Covered	T3,T8,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T9
DebounceSt->IdleSt	163	Covered	T41,T32,T151
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T8,T9
IdleSt->DebounceSt	148	Covered	T3,T8,T9
StableSt->IdleSt	206	Covered	T3,T8,T10

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T9
0	1	Covered	T3,T8,T9
0	0	Excluded	T1,T4,T5	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T151
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T9
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T37
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	92	0	0
CntIncr_A	8367630	47871	0	0
CntNoWrap_A	8367630	7688503	0	0
DetectStDropOut_A	8367630	0	0	0
DetectedOut_A	8367630	3486	0	0
DetectedPulseOut_A	8367630	44	0	0
DisabledIdleSt_A	8367630	7562750	0	0
DisabledNoDetection_A	8367630	7565169	0	0
EnterDebounceSt_A	8367630	48	0	0
EnterDetectSt_A	8367630	44	0	0
EnterStableSt_A	8367630	44	0	0
PulseIsPulse_A	8367630	44	0	0
StayInStableSt	8367630	3417	0	0
gen_high_level_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	19	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8367630	92
T3	13606	4
T6	7683	0
T7	4175	0
T8	1966	2
T9	0	2
T10	0	2
T32	0	1
T33	0	2
T34	0	2
T37	0	4
T38	0	4
T41	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0

CntIncr_A

Name	Attempts	Real Successes
Total	8367630	47871
T3	13606	158
T6	7683	0
T7	4175	0
T8	1966	31
T9	0	40
T10	0	86
T32	0	59
T33	0	56
T34	0	70
T37	0	88
T38	0	188
T41	0	28
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	8367630	7688503
T1	134786	129564
T2	37113	36684
T3	13606	4508
T4	669	268
T5	506	105
T13	522	121
T14	421	20
T15	522	121
T16	430	29
T17	689	288

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	8367630	3486
T3	13606	530
T6	7683	0
T7	4175	0
T8	1966	132
T9	0	43
T10	0	182
T33	0	47
T34	0	38
T37	0	29
T38	0	87
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T74	0	138
T152	0	41

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8367630	44
T3	13606	2
T6	7683	0
T7	4175	0
T8	1966	1
T9	0	1
T10	0	1
T33	0	1
T34	0	1
T37	0	2
T38	0	2
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T74	0	2
T152	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8367630	7562750
T1	134786	129564
T2	37113	36684
T3	13606	3421
T4	669	268
T5	506	105
T13	522	121
T14	421	20
T15	522	121
T16	430	29
T17	689	288

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8367630	7565169
T1	134786	129581
T2	37113	36699
T3	13606	3445
T4	669	269
T5	506	106
T13	522	122
T14	421	21
T15	522	122
T16	430	30
T17	689	289

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8367630	48
T3	13606	2
T6	7683	0
T7	4175	0
T8	1966	1
T9	0	1
T10	0	1
T32	0	1
T33	0	1
T34	0	1
T37	0	2
T38	0	2
T41	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8367630	44
T3	13606	2
T6	7683	0
T7	4175	0
T8	1966	1
T9	0	1
T10	0	1
T33	0	1
T34	0	1
T37	0	2
T38	0	2
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T74	0	2
T152	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	8367630	44
T3	13606	2
T6	7683	0
T7	4175	0
T8	1966	1
T9	0	1
T10	0	1
T33	0	1
T34	0	1
T37	0	2
T38	0	2
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T74	0	2
T152	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8367630	44
T3	13606	2
T6	7683	0
T7	4175	0
T8	1966	1
T9	0	1
T10	0	1
T33	0	1
T34	0	1
T37	0	2
T38	0	2
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T74	0	2
T152	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	8367630	3417
T3	13606	527
T6	7683	0
T7	4175	0
T8	1966	130
T9	0	41
T10	0	181
T33	0	45
T34	0	36
T37	0	27
T38	0	84
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T74	0	135
T152	0	39

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	8367630	7691069
T1	134786	129581
T2	37113	36699
T3	13606	4538
T4	669	269
T5	506	106
T13	522	122
T14	421	21
T15	522	122
T16	430	30
T17	689	289

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8367630	19
T3	13606	1
T6	7683	0
T7	4175	0
T8	1966	0
T10	0	1
T37	0	2
T38	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T74	0	1
T86	0	1
T138	0	1
T153	0	2
T154	0	2
T155	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T68,T156,T157
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T3,T8,T9
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T9
1	-	Covered	T3,T8,T9

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T9
DetectSt	168	Covered	T3,T8,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T9
DebounceSt->IdleSt	163	Covered	T41,T61,T74
DetectSt->IdleSt	186	Covered	T68,T156,T157
DetectSt->StableSt	191	Covered	T3,T8,T9
IdleSt->DebounceSt	148	Covered	T3,T8,T9
StableSt->IdleSt	206	Covered	T3,T8,T9

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T9
0	1	Covered	T3,T8,T9
0	0	Excluded	T1,T4,T5	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T61,T74,T138
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T68,T156,T157
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	135	0	0
CntIncr_A	8367630	45279	0	0
CntNoWrap_A	8367630	7688460	0	0
DetectStDropOut_A	8367630	4	0	0
DetectedOut_A	8367630	144656	0	0
DetectedPulseOut_A	8367630	59	0	0
DisabledIdleSt_A	8367630	7488545	0	0
DisabledNoDetection_A	8367630	7490959	0	0
EnterDebounceSt_A	8367630	72	0	0
EnterDetectSt_A	8367630	63	0	0
EnterStableSt_A	8367630	59	0	0
PulseIsPulse_A	8367630	59	0	0
StayInStableSt	8367630	144574	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8367630	3176	0	0
gen_low_level_sva.LowLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	36	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8367630	135
T3	13606	8
T6	7683	0
T7	4175	0
T8	1966	2
T9	0	2
T34	0	2
T38	0	4
T41	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	3
T97	0	2
T105	0	2
T149	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	8367630	45279
T3	13606	288
T6	7683	0
T7	4175	0
T8	1966	31
T9	0	40
T34	0	50
T38	0	188
T41	0	30
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	60
T97	0	93
T105	0	65
T149	0	74

CntNoWrap_A

Name	Attempts	Real Successes
Total	8367630	7688460
T1	134786	129564
T2	37113	36684
T3	13606	4504
T4	669	268
T5	506	105
T13	522	121
T14	421	20
T15	522	121
T16	430	29
T17	689	288

DetectStDropOut_A

Name	Attempts	Real Successes
Total	8367630	4
T68	738	1
T75	54871	0
T113	0	1
T156	1462	1
T157	0	1
T158	5070	0
T159	749	0
T160	10948	0
T161	522	0
T162	403	0
T163	663	0
T164	34439	0

DetectedOut_A

Name	Attempts	Real Successes
Total	8367630	144656
T3	13606	186
T6	7683	0
T7	4175	0
T8	1966	28
T9	0	31
T34	0	88
T38	0	110
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	43
T97	0	419
T105	0	355
T131	0	39
T149	0	38

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8367630	59
T3	13606	4
T6	7683	0
T7	4175	0
T8	1966	1
T9	0	1
T34	0	1
T38	0	2
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	1
T97	0	1
T105	0	1
T131	0	1
T149	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8367630	7488545
T1	134786	129564
T2	37113	36684
T3	13606	3469
T4	669	268
T5	506	105
T13	522	121
T14	421	20
T15	522	121
T16	430	29
T17	689	288

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8367630	7490959
T1	134786	129581
T2	37113	36699
T3	13606	3493
T4	669	269
T5	506	106
T13	522	122
T14	421	21
T15	522	122
T16	430	30
T17	689	289

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8367630	72
T3	13606	4
T6	7683	0
T7	4175	0
T8	1966	1
T9	0	1
T34	0	1
T38	0	2
T41	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	2
T97	0	1
T105	0	1
T149	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8367630	63
T3	13606	4
T6	7683	0
T7	4175	0
T8	1966	1
T9	0	1
T34	0	1
T38	0	2
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	1
T97	0	1
T105	0	1
T131	0	1
T149	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	8367630	59
T3	13606	4
T6	7683	0
T7	4175	0
T8	1966	1
T9	0	1
T34	0	1
T38	0	2
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	1
T97	0	1
T105	0	1
T131	0	1
T149	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8367630	59
T3	13606	4
T6	7683	0
T7	4175	0
T8	1966	1
T9	0	1
T34	0	1
T38	0	2
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	1
T97	0	1
T105	0	1
T131	0	1
T149	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	8367630	144574
T3	13606	180
T6	7683	0
T7	4175	0
T8	1966	27
T9	0	30
T34	0	86
T38	0	108
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	42
T97	0	418
T105	0	353
T131	0	37
T149	0	36

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	8367630	3176
T1	134786	30
T2	37113	0
T3	13606	54
T4	669	0
T5	506	7
T7	0	20
T13	522	6
T14	421	2
T15	522	5
T16	430	4
T17	689	4
T46	0	2

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	8367630	7691069
T1	134786	129581
T2	37113	36699
T3	13606	4538
T4	669	269
T5	506	106
T13	522	122
T14	421	21
T15	522	122
T16	430	30
T17	689	289

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8367630	36
T3	13606	2
T6	7683	0
T7	4175	0
T8	1966	1
T9	0	1
T38	0	2
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	1
T68	0	1
T74	0	1
T97	0	1
T139	0	1
T165	0	2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T8
1	-	Covered	T3,T7,T8

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T8
DetectSt	168	Covered	T3,T7,T8
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T8
DebounceSt->IdleSt	163	Covered	T3,T41,T38
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T7,T8
IdleSt->DebounceSt	148	Covered	T3,T7,T8
StableSt->IdleSt	206	Covered	T3,T7,T8

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
0	0	Excluded	T1,T4,T5	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T38,T141
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T8
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T8
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	173	0	0
CntIncr_A	8367630	53930	0	0
CntNoWrap_A	8367630	7688422	0	0
DetectStDropOut_A	8367630	0	0	0
DetectedOut_A	8367630	58826	0	0
DetectedPulseOut_A	8367630	83	0	0
DisabledIdleSt_A	8367630	7477455	0	0
DisabledNoDetection_A	8367630	7479859	0	0
EnterDebounceSt_A	8367630	91	0	0
EnterDetectSt_A	8367630	83	0	0
EnterStableSt_A	8367630	83	0	0
PulseIsPulse_A	8367630	83	0	0
StayInStableSt	8367630	58707	0	0
gen_high_level_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	47	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8367630	173
T3	13606	10
T6	7683	0
T7	4175	2
T8	1966	2
T10	0	6
T33	0	2
T34	0	2
T35	0	2
T41	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	4
T149	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	8367630	53930
T3	13606	424
T6	7683	0
T7	4175	42
T8	1966	31
T10	0	198
T33	0	56
T34	0	50
T35	0	55
T41	0	29
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	60
T149	0	74

CntNoWrap_A

Name	Attempts	Real Successes
Total	8367630	7688422
T1	134786	129564
T2	37113	36684
T3	13606	4502
T4	669	268
T5	506	105
T13	522	121
T14	421	20
T15	522	121
T16	430	29
T17	689	288

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	8367630	58826
T3	13606	306
T6	7683	0
T7	4175	8
T8	1966	59
T10	0	225
T33	0	47
T34	0	20
T35	0	41
T36	0	86
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	217
T149	0	98

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8367630	83
T3	13606	4
T6	7683	0
T7	4175	1
T8	1966	1
T10	0	3
T33	0	1
T34	0	1
T35	0	1
T36	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	2
T149	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8367630	7477455
T1	134786	129564
T2	37113	36684
T3	13606	2856
T4	669	268
T5	506	105
T13	522	121
T14	421	20
T15	522	121
T16	430	29
T17	689	288

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8367630	7479859
T1	134786	129581
T2	37113	36699
T3	13606	2879
T4	669	269
T5	506	106
T13	522	122
T14	421	21
T15	522	122
T16	430	30
T17	689	289

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8367630	91
T3	13606	6
T6	7683	0
T7	4175	1
T8	1966	1
T10	0	3
T33	0	1
T34	0	1
T35	0	1
T41	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	2
T149	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8367630	83
T3	13606	4
T6	7683	0
T7	4175	1
T8	1966	1
T10	0	3
T33	0	1
T34	0	1
T35	0	1
T36	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	2
T149	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	8367630	83
T3	13606	4
T6	7683	0
T7	4175	1
T8	1966	1
T10	0	3
T33	0	1
T34	0	1
T35	0	1
T36	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	2
T149	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8367630	83
T3	13606	4
T6	7683	0
T7	4175	1
T8	1966	1
T10	0	3
T33	0	1
T34	0	1
T35	0	1
T36	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	2
T149	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	8367630	58707
T3	13606	302
T6	7683	0
T7	4175	7
T8	1966	58
T10	0	220
T33	0	45
T34	0	19
T35	0	39
T36	0	85
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	214
T149	0	96

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	8367630	7691069
T1	134786	129581
T2	37113	36699
T3	13606	4538
T4	669	269
T5	506	106
T13	522	122
T14	421	21
T15	522	122
T16	430	30
T17	689	289

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8367630	47
T3	13606	4
T6	7683	0
T7	4175	1
T8	1966	1
T10	0	1
T34	0	1
T36	0	1
T38	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	1
T151	0	1
T166	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T41,T61

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T41,T61

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T33
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T41,T61

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T36,T37
0	1	Covered	T167
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T36,T37
0	1	Covered	T37,T38,T140
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T36,T37
1	-	Covered	T37,T38,T140

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T41,T61
DetectSt	168	Covered	T3,T36,T37
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T36,T37
DebounceSt->IdleSt	163	Covered	T41,T61,T66
DetectSt->IdleSt	186	Covered	T167
DetectSt->StableSt	191	Covered	T3,T36,T37
IdleSt->DebounceSt	148	Covered	T3,T41,T61
StableSt->IdleSt	206	Covered	T3,T37,T38

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T41,T61
0	1	Covered	T3,T41,T61
0	0	Excluded	T1,T4,T5	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T3,T36,T37
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T41,T61
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T61,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T41,T61
DetectSt	-	-	-	-	1	-	-	Covered	T167
DetectSt	-	-	-	-	0	1	-	Covered	T3,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T38,T140
StableSt	-	-	-	-	-	-	0	Covered	T3,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	100	0	0
CntIncr_A	8367630	146618	0	0
CntNoWrap_A	8367630	7688495	0	0
DetectStDropOut_A	8367630	1	0	0
DetectedOut_A	8367630	117612	0	0
DetectedPulseOut_A	8367630	47	0	0
DisabledIdleSt_A	8367630	7176049	0	0
DisabledNoDetection_A	8367630	7178463	0	0
EnterDebounceSt_A	8367630	52	0	0
EnterDetectSt_A	8367630	48	0	0
EnterStableSt_A	8367630	47	0	0
PulseIsPulse_A	8367630	47	0	0
StayInStableSt	8367630	117539	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8367630	6903	0	0
gen_low_level_sva.LowLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	21	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8367630	100
T3	13606	2
T6	7683	0
T7	4175	0
T8	1966	0
T36	0	2
T37	0	2
T38	0	6
T41	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	1
T66	0	1
T97	0	2
T140	0	4
T142	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	8367630	146618
T3	13606	81
T6	7683	0
T7	4175	0
T8	1966	0
T36	0	46
T37	0	44
T38	0	146
T41	0	28
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	30
T66	0	28
T97	0	93
T140	0	26
T142	0	65

CntNoWrap_A

Name	Attempts	Real Successes
Total	8367630	7688495
T1	134786	129564
T2	37113	36684
T3	13606	4510
T4	669	268
T5	506	105
T13	522	121
T14	421	20
T15	522	121
T16	430	29
T17	689	288

DetectStDropOut_A

Name	Attempts	Real Successes
Total	8367630	1
T167	1180	1
T169	21647	0
T170	525	0
T171	8858	0
T172	9065	0
T173	451	0
T174	4802	0
T175	471	0
T176	2939	0
T177	427	0

DetectedOut_A

Name	Attempts	Real Successes
Total	8367630	117612
T3	13606	248
T6	7683	0
T7	4175	0
T8	1966	0
T36	0	86
T37	0	28
T38	0	371
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T68	0	6
T75	0	123
T97	0	47
T140	0	90
T142	0	205
T152	0	41

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8367630	47
T3	13606	1
T6	7683	0
T7	4175	0
T8	1966	0
T36	0	1
T37	0	1
T38	0	3
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T68	0	2
T75	0	3
T97	0	1
T140	0	2
T142	0	1
T152	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8367630	7176049
T1	134786	129564
T2	37113	36684
T3	13606	4034
T4	669	268
T5	506	105
T13	522	121
T14	421	20
T15	522	121
T16	430	29
T17	689	288

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8367630	7178463
T1	134786	129581
T2	37113	36699
T3	13606	4059
T4	669	269
T5	506	106
T13	522	122
T14	421	21
T15	522	122
T16	430	30
T17	689	289

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8367630	52
T3	13606	1
T6	7683	0
T7	4175	0
T8	1966	0
T36	0	1
T37	0	1
T38	0	3
T41	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T61	0	1
T66	0	1
T97	0	1
T140	0	2
T142	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8367630	48
T3	13606	1
T6	7683	0
T7	4175	0
T8	1966	0
T36	0	1
T37	0	1
T38	0	3
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T68	0	2
T75	0	3
T97	0	1
T140	0	2
T142	0	1
T152	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	8367630	47
T3	13606	1
T6	7683	0
T7	4175	0
T8	1966	0
T36	0	1
T37	0	1
T38	0	3
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T68	0	2
T75	0	3
T97	0	1
T140	0	2
T142	0	1
T152	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8367630	47
T3	13606	1
T6	7683	0
T7	4175	0
T8	1966	0
T36	0	1
T37	0	1
T38	0	3
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T68	0	2
T75	0	3
T97	0	1
T140	0	2
T142	0	1
T152	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	8367630	117539
T3	13606	246
T6	7683	0
T7	4175	0
T8	1966	0
T36	0	84
T37	0	27
T38	0	367
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T68	0	4
T75	0	119
T97	0	45
T140	0	87
T142	0	203
T152	0	39

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	8367630	6903
T1	134786	28
T2	37113	30
T3	13606	53
T4	669	0
T5	506	3
T6	0	32
T13	522	6
T14	421	3
T15	522	6
T16	430	4
T17	689	0
T46	0	1

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	8367630	7691069
T1	134786	129581
T2	37113	36699
T3	13606	4538
T4	669	269
T5	506	106
T13	522	122
T14	421	21
T15	522	122
T16	430	30
T17	689	289

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8367630	21
T37	29817	1
T38	324527	2
T59	490	0
T62	9037	0
T68	0	2
T75	0	2
T86	0	1
T95	2966	0
T96	422	0
T97	1063	0
T98	857	0
T99	526	0
T100	761	0
T138	0	1
T140	0	1
T147	0	1
T154	0	1
T178	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T9
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T9
0	1	Covered	T74,T75,T156
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T9
0	1	Covered	T3,T32,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T9
1	-	Covered	T3,T32,T37

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T9
DetectSt	168	Covered	T3,T7,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T9
DebounceSt->IdleSt	163	Covered	T41,T38,T97
DetectSt->IdleSt	186	Covered	T74,T75,T156
DetectSt->StableSt	191	Covered	T3,T7,T9
IdleSt->DebounceSt	148	Covered	T3,T7,T9
StableSt->IdleSt	206	Covered	T3,T7,T32

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T9
0	1	Covered	T3,T7,T9
0	0	Excluded	T1,T4,T5	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T9
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T97,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T74,T75,T156
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T32,T37
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	146	0	0
CntIncr_A	8367630	93616	0	0
CntNoWrap_A	8367630	7688449	0	0
DetectStDropOut_A	8367630	4	0	0
DetectedOut_A	8367630	105160	0	0
DetectedPulseOut_A	8367630	63	0	0
DisabledIdleSt_A	8367630	7413981	0	0
DisabledNoDetection_A	8367630	7416394	0	0
EnterDebounceSt_A	8367630	80	0	0
EnterDetectSt_A	8367630	67	0	0
EnterStableSt_A	8367630	63	0	0
PulseIsPulse_A	8367630	63	0	0
StayInStableSt	8367630	105068	0	0
gen_high_level_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	34	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8367630	146
T3	13606	2
T6	7683	0
T7	4175	2
T8	1966	0
T9	0	2
T32	0	4
T34	0	4
T37	0	4
T38	0	3
T41	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T97	0	3
T149	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	8367630	93616
T3	13606	81
T6	7683	0
T7	4175	42
T8	1966	0
T9	0	40
T32	0	118
T34	0	120
T37	0	88
T38	0	52
T41	0	29
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T97	0	186
T149	0	74

CntNoWrap_A

Name	Attempts	Real Successes
Total	8367630	7688449
T1	134786	129564
T2	37113	36684
T3	13606	4510
T4	669	268
T5	506	105
T13	522	121
T14	421	20
T15	522	121
T16	430	29
T17	689	288

DetectStDropOut_A

Name	Attempts	Real Successes
Total	8367630	4
T74	1878	1
T75	0	1
T156	0	1
T179	0	1
T180	13800	0
T181	522	0
T182	405	0
T183	409	0
T184	407	0
T185	491	0
T186	404	0
T187	21440	0
T188	497	0

DetectedOut_A

Name	Attempts	Real Successes
Total	8367630	105160
T3	13606	125
T6	7683	0
T7	4175	87
T8	1966	0
T9	0	43
T32	0	94
T34	0	143
T37	0	79
T38	0	119
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T97	0	103
T140	0	75
T149	0	38

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8367630	63
T3	13606	1
T6	7683	0
T7	4175	1
T8	1966	0
T9	0	1
T32	0	2
T34	0	2
T37	0	2
T38	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T97	0	1
T140	0	2
T149	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8367630	7413981
T1	134786	129564
T2	37113	36684
T3	13606	3469
T4	669	268
T5	506	105
T13	522	121
T14	421	20
T15	522	121
T16	430	29
T17	689	288

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8367630	7416394
T1	134786	129581
T2	37113	36699
T3	13606	3493
T4	669	269
T5	506	106
T13	522	122
T14	421	21
T15	522	122
T16	430	30
T17	689	289

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8367630	80
T3	13606	1
T6	7683	0
T7	4175	1
T8	1966	0
T9	0	1
T32	0	2
T34	0	2
T37	0	2
T38	0	2
T41	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T97	0	2
T149	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8367630	67
T3	13606	1
T6	7683	0
T7	4175	1
T8	1966	0
T9	0	1
T32	0	2
T34	0	2
T37	0	2
T38	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T97	0	1
T140	0	2
T149	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	8367630	63
T3	13606	1
T6	7683	0
T7	4175	1
T8	1966	0
T9	0	1
T32	0	2
T34	0	2
T37	0	2
T38	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T97	0	1
T140	0	2
T149	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8367630	63
T3	13606	1
T6	7683	0
T7	4175	1
T8	1966	0
T9	0	1
T32	0	2
T34	0	2
T37	0	2
T38	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T97	0	1
T140	0	2
T149	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	8367630	105068
T3	13606	124
T6	7683	0
T7	4175	85
T8	1966	0
T9	0	41
T32	0	92
T34	0	139
T37	0	77
T38	0	118
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T97	0	101
T140	0	73
T149	0	36

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	8367630	7691069
T1	134786	129581
T2	37113	36699
T3	13606	4538
T4	669	269
T5	506	106
T13	522	122
T14	421	21
T15	522	122
T16	430	30
T17	689	289

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8367630	34
T3	13606	1
T6	7683	0
T7	4175	0
T8	1966	0
T32	0	2
T37	0	2
T38	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T72	0	2
T140	0	2
T142	0	1
T146	0	1
T165	0	1
T189	0	2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T41,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T41,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T32,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T9
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T41,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T32,T35
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T32,T35
0	1	Covered	T3,T32,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T32,T35
1	-	Covered	T3,T32,T37

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T41,T32
DetectSt	168	Covered	T3,T32,T35
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T32,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T32,T35
DebounceSt->IdleSt	163	Covered	T41,T66,T178
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T32,T35
IdleSt->DebounceSt	148	Covered	T3,T41,T32
StableSt->IdleSt	206	Covered	T3,T32,T37

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T41,T32
0	1	Covered	T3,T41,T32
0	0	Excluded	T1,T4,T5	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T3,T32,T35
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T41,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T32,T35
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T41,T32
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T32,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T32,T37
StableSt	-	-	-	-	-	-	0	Covered	T3,T32,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	88	0	0
CntIncr_A	8367630	39663	0	0
CntNoWrap_A	8367630	7688507	0	0
DetectStDropOut_A	8367630	0	0	0
DetectedOut_A	8367630	18414	0	0
DetectedPulseOut_A	8367630	43	0	0
DisabledIdleSt_A	8367630	7144998	0	0
DisabledNoDetection_A	8367630	7147413	0	0
EnterDebounceSt_A	8367630	46	0	0
EnterDetectSt_A	8367630	43	0	0
EnterStableSt_A	8367630	43	0	0
PulseIsPulse_A	8367630	43	0	0
StayInStableSt	8367630	18347	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8367630	6578	0	0
gen_low_level_sva.LowLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	19	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8367630	88
T3	13606	2
T6	7683	0
T7	4175	0
T8	1966	0
T32	0	4
T35	0	2
T37	0	4
T38	0	2
T41	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T66	0	1
T74	0	4
T142	0	2
T165	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	8367630	39663
T3	13606	77
T6	7683	0
T7	4175	0
T8	1966	0
T32	0	118
T35	0	55
T37	0	88
T38	0	94
T41	0	29
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T66	0	29
T74	0	114
T142	0	65
T165	0	20

CntNoWrap_A

Name	Attempts	Real Successes
Total	8367630	7688507
T1	134786	129564
T2	37113	36684
T3	13606	4510
T4	669	268
T5	506	105
T13	522	121
T14	421	20
T15	522	121
T16	430	29
T17	689	288

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	8367630	18414
T3	13606	403
T6	7683	0
T7	4175	0
T8	1966	0
T32	0	232
T35	0	54
T37	0	200
T38	0	483
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T74	0	121
T75	0	67
T138	0	276
T142	0	43
T165	0	144

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8367630	43
T3	13606	1
T6	7683	0
T7	4175	0
T8	1966	0
T32	0	2
T35	0	1
T37	0	2
T38	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T74	0	2
T75	0	1
T138	0	2
T142	0	1
T165	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8367630	7144998
T1	134786	129564
T2	37113	36684
T3	13606	3899
T4	669	268
T5	506	105
T13	522	121
T14	421	20
T15	522	121
T16	430	29
T17	689	288

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8367630	7147413
T1	134786	129581
T2	37113	36699
T3	13606	3924
T4	669	269
T5	506	106
T13	522	122
T14	421	21
T15	522	122
T16	430	30
T17	689	289

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8367630	46
T3	13606	1
T6	7683	0
T7	4175	0
T8	1966	0
T32	0	2
T35	0	1
T37	0	2
T38	0	1
T41	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T66	0	1
T74	0	2
T142	0	1
T165	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8367630	43
T3	13606	1
T6	7683	0
T7	4175	0
T8	1966	0
T32	0	2
T35	0	1
T37	0	2
T38	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T74	0	2
T75	0	1
T138	0	2
T142	0	1
T165	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	8367630	43
T3	13606	1
T6	7683	0
T7	4175	0
T8	1966	0
T32	0	2
T35	0	1
T37	0	2
T38	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T74	0	2
T75	0	1
T138	0	2
T142	0	1
T165	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8367630	43
T3	13606	1
T6	7683	0
T7	4175	0
T8	1966	0
T32	0	2
T35	0	1
T37	0	2
T38	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T74	0	2
T75	0	1
T138	0	2
T142	0	1
T165	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	8367630	18347
T3	13606	402
T6	7683	0
T7	4175	0
T8	1966	0
T32	0	229
T35	0	52
T37	0	197
T38	0	481
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T74	0	119
T75	0	66
T138	0	273
T142	0	41
T165	0	142

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	8367630	6578
T1	134786	29
T2	37113	30
T3	13606	44
T4	669	0
T5	506	6
T6	0	30
T13	522	6
T14	421	1
T15	522	4
T16	430	3
T17	689	0
T46	0	4

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	8367630	7691069
T1	134786	129581
T2	37113	36699
T3	13606	4538
T4	669	269
T5	506	106
T13	522	122
T14	421	21
T15	522	122
T16	430	30
T17	689	289

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8367630	19
T3	13606	1
T6	7683	0
T7	4175	0
T8	1966	0
T32	0	1
T37	0	1
T46	422	0
T47	428	0
T48	546	0
T49	422	0
T50	604	0
T51	684	0
T74	0	2
T75	0	1
T86	0	1
T138	0	1
T147	0	1
T154	0	1
T190	0	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr