Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T7,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T7,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T7,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T10
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T10
0	1	Covered	T3,T10,T33
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T10
1	-	Covered	T3,T10,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T10
DetectSt	168	Covered	T3,T7,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T7,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T10
DebounceSt->IdleSt	163	Covered	T41,T61,T141
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T7,T10
IdleSt->DebounceSt	148	Covered	T3,T7,T10
StableSt->IdleSt	206	Covered	T3,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T10
0	1	Covered	T3,T7,T10
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T61,T141,T146
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T10
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T33
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	141	0	0
CntIncr_A	8367630	72773	0	0
CntNoWrap_A	8367630	7688454	0	0
DetectStDropOut_A	8367630	0	0	0
DetectedOut_A	8367630	7965	0	0
DetectedPulseOut_A	8367630	67	0	0
DisabledIdleSt_A	8367630	7522176	0	0
DisabledNoDetection_A	8367630	7524593	0	0
EnterDebounceSt_A	8367630	75	0	0
EnterDetectSt_A	8367630	67	0	0
EnterStableSt_A	8367630	67	0	0
PulseIsPulse_A	8367630	67	0	0
StayInStableSt	8367630	7871	0	0
gen_high_level_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	141	0	0
T3	13606	4	0	0
T6	7683	0	0	0
T7	4175	2	0	0
T8	1966	0	0	0
T10	0	4	0	0
T33	0	2	0	0
T34	0	2	0	0
T36	0	4	0	0
T41	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	3	0	0
T97	0	4	0	0
T166	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	72773	0	0
T3	13606	126	0	0
T6	7683	0	0	0
T7	4175	42	0	0
T8	1966	0	0	0
T10	0	52	0	0
T33	0	56	0	0
T34	0	70	0	0
T36	0	92	0	0
T41	0	29	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	60	0	0
T97	0	186	0	0
T166	0	122	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7688454	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	4508	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7965	0	0
T3	13606	158	0	0
T6	7683	0	0	0
T7	4175	38	0	0
T8	1966	0	0	0
T10	0	26	0	0
T33	0	128	0	0
T34	0	57	0	0
T36	0	279	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	15	0	0
T97	0	189	0	0
T151	0	221	0	0
T166	0	89	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	67	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	0	0	0
T10	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	1	0	0
T97	0	2	0	0
T151	0	1	0	0
T166	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7522176	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	3947	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7524593	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	3972	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	75	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	0	0	0
T10	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T41	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	2	0	0
T97	0	2	0	0
T166	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	67	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	0	0	0
T10	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	1	0	0
T97	0	2	0	0
T151	0	1	0	0
T166	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	67	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	0	0	0
T10	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	1	0	0
T97	0	2	0	0
T151	0	1	0	0
T166	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	67	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	0	0	0
T10	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	1	0	0
T97	0	2	0	0
T151	0	1	0	0
T166	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7871	0	0
T3	13606	156	0	0
T6	7683	0	0	0
T7	4175	36	0	0
T8	1966	0	0	0
T10	0	24	0	0
T33	0	127	0	0
T34	0	56	0	0
T36	0	276	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	14	0	0
T97	0	187	0	0
T151	0	219	0	0
T166	0	86	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	40	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T61	0	1	0	0
T97	0	2	0	0
T105	0	2	0	0
T140	0	1	0	0
T166	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T33,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T33,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T33,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T33
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T33,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T33,T34
0	1	Covered	T36,T154,T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T33,T34
0	1	Covered	T3,T105,T68
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T33,T34
1	-	Covered	T3,T105,T68

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T33,T41
DetectSt	168	Covered	T3,T33,T34
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T33,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T33,T34
DebounceSt->IdleSt	163	Covered	T41,T139,T66
DetectSt->IdleSt	186	Covered	T36,T154,T86
DetectSt->StableSt	191	Covered	T3,T33,T34
IdleSt->DebounceSt	148	Covered	T3,T33,T41
StableSt->IdleSt	206	Covered	T3,T33,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T33,T41
0	1	Covered	T3,T33,T41
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T33,T34
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T33,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T33,T34
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T33,T41
DetectSt	-	-	-	-	1	-	-	Covered	T36,T154,T86
DetectSt	-	-	-	-	0	1	-	Covered	T3,T33,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T105,T68
StableSt	-	-	-	-	-	-	0	Covered	T3,T33,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	90	0	0
CntIncr_A	8367630	144533	0	0
CntNoWrap_A	8367630	7688505	0	0
DetectStDropOut_A	8367630	3	0	0
DetectedOut_A	8367630	84800	0	0
DetectedPulseOut_A	8367630	41	0	0
DisabledIdleSt_A	8367630	7162279	0	0
DisabledNoDetection_A	8367630	7164688	0	0
EnterDebounceSt_A	8367630	47	0	0
EnterDetectSt_A	8367630	44	0	0
EnterStableSt_A	8367630	41	0	0
PulseIsPulse_A	8367630	41	0	0
StayInStableSt	8367630	84742	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8367630	6491	0	0
gen_low_level_sva.LowLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	90	0	0
T3	13606	8	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T36	0	2	0	0
T41	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T66	0	1	0	0
T68	0	2	0	0
T105	0	4	0	0
T140	0	2	0	0
T141	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	144533	0	0
T3	13606	280	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T33	0	56	0	0
T34	0	70	0	0
T36	0	46	0	0
T41	0	28	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T66	0	29	0	0
T105	0	130	0	0
T139	0	4987	0	0
T140	0	13	0	0
T141	0	99	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7688505	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	4504	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	3	0	0
T36	829	1	0	0
T37	29817	0	0	0
T58	496	0	0	0
T59	490	0	0	0
T86	0	1	0	0
T95	2966	0	0	0
T96	422	0	0	0
T101	625	0	0	0
T102	699	0	0	0
T144	501	0	0	0
T145	404	0	0	0
T154	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	84800	0	0
T3	13606	234	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T33	0	46	0	0
T34	0	38	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T68	0	43	0	0
T75	0	136	0	0
T105	0	87	0	0
T140	0	46	0	0
T141	0	332	0	0
T152	0	42	0	0
T163	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	41	0	0
T3	13606	4	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T68	0	1	0	0
T75	0	1	0	0
T105	0	2	0	0
T140	0	1	0	0
T141	0	1	0	0
T152	0	1	0	0
T163	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7162279	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	3334	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7164688	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	3358	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	47	0	0
T3	13606	4	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T41	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T66	0	1	0	0
T105	0	2	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	44	0	0
T3	13606	4	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T68	0	1	0	0
T75	0	1	0	0
T105	0	2	0	0
T140	0	1	0	0
T141	0	1	0	0
T163	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	41	0	0
T3	13606	4	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T68	0	1	0	0
T75	0	1	0	0
T105	0	2	0	0
T140	0	1	0	0
T141	0	1	0	0
T152	0	1	0	0
T163	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	41	0	0
T3	13606	4	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T68	0	1	0	0
T75	0	1	0	0
T105	0	2	0	0
T140	0	1	0	0
T141	0	1	0	0
T152	0	1	0	0
T163	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	84742	0	0
T3	13606	229	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T33	0	44	0	0
T34	0	36	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T68	0	42	0	0
T75	0	134	0	0
T105	0	84	0	0
T140	0	44	0	0
T141	0	330	0	0
T152	0	40	0	0
T163	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	6491	0	0
T1	134786	23	0	0
T2	37113	34	0	0
T3	13606	47	0	0
T4	669	0	0	0
T5	506	6	0	0
T6	0	30	0	0
T13	522	4	0	0
T14	421	2	0	0
T15	522	3	0	0
T16	430	3	0	0
T17	689	0	0	0
T46	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	24	0	0
T3	13606	3	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T68	0	1	0	0
T72	0	2	0	0
T105	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T154	0	1	0	0
T163	0	1	0	0
T191	0	2	0	0
T192	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T36,T168
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T7,T8,T33
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T8
1	-	Covered	T7,T8,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T8
DetectSt	168	Covered	T3,T7,T8
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T8
DebounceSt->IdleSt	163	Covered	T41,T34,T66
DetectSt->IdleSt	186	Covered	T36,T168
DetectSt->StableSt	191	Covered	T3,T7,T8
IdleSt->DebounceSt	148	Covered	T3,T7,T8
StableSt->IdleSt	206	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T68,T154
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T36,T168
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T33
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	174	0	0
CntIncr_A	8367630	38397	0	0
CntNoWrap_A	8367630	7688421	0	0
DetectStDropOut_A	8367630	2	0	0
DetectedOut_A	8367630	40081	0	0
DetectedPulseOut_A	8367630	81	0	0
DisabledIdleSt_A	8367630	7450737	0	0
DisabledNoDetection_A	8367630	7453146	0	0
EnterDebounceSt_A	8367630	91	0	0
EnterDetectSt_A	8367630	83	0	0
EnterStableSt_A	8367630	81	0	0
PulseIsPulse_A	8367630	81	0	0
StayInStableSt	8367630	39963	0	0
gen_high_level_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	44	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	174	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	2	0	0
T8	1966	4	0	0
T9	0	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	4	0	0
T37	0	4	0	0
T38	0	8	0	0
T41	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	38397	0	0
T3	13606	81	0	0
T6	7683	0	0	0
T7	4175	42	0	0
T8	1966	62	0	0
T9	0	40	0	0
T33	0	56	0	0
T34	0	70	0	0
T36	0	92	0	0
T37	0	88	0	0
T38	0	240	0	0
T41	0	29	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7688421	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	4510	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	2	0	0
T36	829	1	0	0
T37	29817	0	0	0
T58	496	0	0	0
T59	490	0	0	0
T95	2966	0	0	0
T96	422	0	0	0
T101	625	0	0	0
T102	699	0	0	0
T144	501	0	0	0
T145	404	0	0	0
T168	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	40081	0	0
T3	13606	41	0	0
T6	7683	0	0	0
T7	4175	8	0	0
T8	1966	83	0	0
T9	0	116	0	0
T33	0	127	0	0
T36	0	106	0	0
T37	0	298	0	0
T38	0	263	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T97	0	271	0	0
T105	0	127	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	81	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	2	0	0
T9	0	1	0	0
T33	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	4	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T97	0	2	0	0
T105	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7450737	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	4034	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7453146	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4059	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	91	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	2	0	0
T9	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T41	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	83	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	2	0	0
T9	0	1	0	0
T33	0	1	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T97	0	2	0	0
T105	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	81	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	2	0	0
T9	0	1	0	0
T33	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	4	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T97	0	2	0	0
T105	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	81	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	2	0	0
T9	0	1	0	0
T33	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	4	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T97	0	2	0	0
T105	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	39963	0	0
T3	13606	39	0	0
T6	7683	0	0	0
T7	4175	7	0	0
T8	1966	80	0	0
T9	0	114	0	0
T33	0	126	0	0
T36	0	105	0	0
T37	0	295	0	0
T38	0	257	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T97	0	268	0	0
T105	0	125	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	44	0	0
T7	4175	1	0	0
T8	1966	1	0	0
T9	565	0	0	0
T22	495	0	0	0
T33	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T52	409	0	0	0
T68	0	1	0	0
T74	0	1	0	0
T97	0	1	0	0
T141	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T7,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T7,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T7,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T10
0	1	Covered	T138,T113
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T10
0	1	Covered	T3,T38,T140
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T10
1	-	Covered	T3,T38,T140

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T10
DetectSt	168	Covered	T3,T7,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T7,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T10
DebounceSt->IdleSt	163	Covered	T41,T66,T113
DetectSt->IdleSt	186	Covered	T138,T113
DetectSt->StableSt	191	Covered	T3,T7,T10
IdleSt->DebounceSt	148	Covered	T3,T7,T10
StableSt->IdleSt	206	Covered	T3,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T10
0	1	Covered	T3,T7,T10
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T113
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T10
DetectSt	-	-	-	-	1	-	-	Covered	T138,T113
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T38,T140
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	97	0	0
CntIncr_A	8367630	17888	0	0
CntNoWrap_A	8367630	7688498	0	0
DetectStDropOut_A	8367630	2	0	0
DetectedOut_A	8367630	25263	0	0
DetectedPulseOut_A	8367630	45	0	0
DisabledIdleSt_A	8367630	7473364	0	0
DisabledNoDetection_A	8367630	7475784	0	0
EnterDebounceSt_A	8367630	50	0	0
EnterDetectSt_A	8367630	47	0	0
EnterStableSt_A	8367630	45	0	0
PulseIsPulse_A	8367630	45	0	0
StayInStableSt	8367630	25195	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8367630	6573	0	0
gen_low_level_sva.LowLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	97	0	0
T3	13606	4	0	0
T6	7683	0	0	0
T7	4175	2	0	0
T8	1966	0	0	0
T10	0	2	0	0
T38	0	2	0	0
T41	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T66	0	1	0	0
T75	0	2	0	0
T140	0	4	0	0
T141	0	2	0	0
T165	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	17888	0	0
T3	13606	126	0	0
T6	7683	0	0	0
T7	4175	42	0	0
T8	1966	0	0	0
T10	0	86	0	0
T38	0	94	0	0
T41	0	29	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T66	0	30	0	0
T75	0	75	0	0
T140	0	26	0	0
T141	0	99	0	0
T165	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7688498	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	4508	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	2	0	0
T73	1509	0	0	0
T113	0	1	0	0
T138	1038	1	0	0
T150	748	0	0	0
T189	938	0	0	0
T193	402	0	0	0
T194	433	0	0	0
T195	14197	0	0	0
T196	426	0	0	0
T197	410	0	0	0
T198	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	25263	0	0
T3	13606	145	0	0
T6	7683	0	0	0
T7	4175	37	0	0
T8	1966	0	0	0
T10	0	43	0	0
T38	0	480	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T72	0	115	0	0
T75	0	167	0	0
T140	0	109	0	0
T141	0	193	0	0
T152	0	42	0	0
T165	0	85	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	45	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	0	0	0
T10	0	1	0	0
T38	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T72	0	2	0	0
T75	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0
T152	0	1	0	0
T165	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7473364	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	3947	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7475784	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	3972	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	50	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	0	0	0
T10	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T66	0	1	0	0
T75	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0
T165	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	47	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	0	0	0
T10	0	1	0	0
T38	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T72	0	2	0	0
T75	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0
T152	0	1	0	0
T165	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	45	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	0	0	0
T10	0	1	0	0
T38	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T72	0	2	0	0
T75	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0
T152	0	1	0	0
T165	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	45	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	0	0	0
T10	0	1	0	0
T38	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T72	0	2	0	0
T75	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0
T152	0	1	0	0
T165	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	25195	0	0
T3	13606	142	0	0
T6	7683	0	0	0
T7	4175	35	0	0
T8	1966	0	0	0
T10	0	41	0	0
T38	0	479	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T72	0	113	0	0
T75	0	166	0	0
T140	0	106	0	0
T141	0	191	0	0
T152	0	40	0	0
T165	0	82	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	6573	0	0
T1	134786	27	0	0
T2	37113	31	0	0
T3	13606	43	0	0
T4	669	0	0	0
T5	506	4	0	0
T6	0	18	0	0
T13	522	5	0	0
T14	421	4	0	0
T15	522	6	0	0
T16	430	6	0	0
T17	689	0	0	0
T46	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	22	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T38	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T72	0	2	0	0
T75	0	1	0	0
T86	0	2	0	0
T140	0	1	0	0
T147	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T3,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T3,T8,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T8
1	-	Covered	T3,T8,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T8
DetectSt	168	Covered	T3,T7,T8
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T8
DebounceSt->IdleSt	163	Covered	T41,T131,T139
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T7,T8
IdleSt->DebounceSt	148	Covered	T3,T7,T8
StableSt->IdleSt	206	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T131,T153,T199
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T8
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T35
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	137	0	0
CntIncr_A	8367630	138335	0	0
CntNoWrap_A	8367630	7688458	0	0
DetectStDropOut_A	8367630	0	0	0
DetectedOut_A	8367630	103788	0	0
DetectedPulseOut_A	8367630	64	0	0
DisabledIdleSt_A	8367630	7312234	0	0
DisabledNoDetection_A	8367630	7314653	0	0
EnterDebounceSt_A	8367630	74	0	0
EnterDetectSt_A	8367630	64	0	0
EnterStableSt_A	8367630	64	0	0
PulseIsPulse_A	8367630	64	0	0
StayInStableSt	8367630	103689	0	0
gen_high_level_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	137	0	0
T3	13606	6	0	0
T6	7683	0	0	0
T7	4175	2	0	0
T8	1966	2	0	0
T9	0	2	0	0
T35	0	4	0	0
T36	0	6	0	0
T38	0	4	0	0
T41	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T97	0	2	0	0
T149	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	138335	0	0
T3	13606	235	0	0
T6	7683	0	0	0
T7	4175	42	0	0
T8	1966	31	0	0
T9	0	40	0	0
T35	0	110	0	0
T36	0	138	0	0
T38	0	52	0	0
T41	0	28	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T97	0	93	0	0
T149	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7688458	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	4506	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	103788	0	0
T3	13606	309	0	0
T6	7683	0	0	0
T7	4175	37	0	0
T8	1966	29	0	0
T9	0	115	0	0
T35	0	139	0	0
T36	0	122	0	0
T38	0	121	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T97	0	436	0	0
T105	0	244	0	0
T149	0	98	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	64	0	0
T3	13606	3	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	1	0	0
T9	0	1	0	0
T35	0	2	0	0
T36	0	3	0	0
T38	0	2	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T97	0	1	0	0
T105	0	1	0	0
T149	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7312234	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	3421	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7314653	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	3445	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	74	0	0
T3	13606	3	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	1	0	0
T9	0	1	0	0
T35	0	2	0	0
T36	0	3	0	0
T38	0	2	0	0
T41	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T97	0	1	0	0
T149	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	64	0	0
T3	13606	3	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	1	0	0
T9	0	1	0	0
T35	0	2	0	0
T36	0	3	0	0
T38	0	2	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T97	0	1	0	0
T105	0	1	0	0
T149	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	64	0	0
T3	13606	3	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	1	0	0
T9	0	1	0	0
T35	0	2	0	0
T36	0	3	0	0
T38	0	2	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T97	0	1	0	0
T105	0	1	0	0
T149	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	64	0	0
T3	13606	3	0	0
T6	7683	0	0	0
T7	4175	1	0	0
T8	1966	1	0	0
T9	0	1	0	0
T35	0	2	0	0
T36	0	3	0	0
T38	0	2	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T97	0	1	0	0
T105	0	1	0	0
T149	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	103689	0	0
T3	13606	304	0	0
T6	7683	0	0	0
T7	4175	35	0	0
T8	1966	28	0	0
T9	0	113	0	0
T35	0	136	0	0
T36	0	118	0	0
T38	0	118	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T97	0	434	0	0
T105	0	243	0	0
T149	0	96	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	29	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T72	0	2	0	0
T105	0	1	0	0
T139	0	1	0	0
T153	0	3	0	0
T165	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T10,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T10,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T10,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T10
1	0	Covered	T1,T4,T5
1	1	Covered	T3,T10,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T32
0	1	Covered	T36
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T32
0	1	Covered	T3,T10,T32
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T32
1	-	Covered	T3,T10,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T41
DetectSt	168	Covered	T3,T10,T32
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T10,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T32
DebounceSt->IdleSt	163	Covered	T41,T35,T36
DetectSt->IdleSt	186	Covered	T36
DetectSt->StableSt	191	Covered	T3,T10,T32
IdleSt->DebounceSt	148	Covered	T3,T10,T41
StableSt->IdleSt	206	Covered	T3,T10,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T10,T41
0	1	Covered	T3,T10,T41
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T32
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T36,T151
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T41
DetectSt	-	-	-	-	1	-	-	Covered	T36
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T32
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	108	0	0
CntIncr_A	8367630	82282	0	0
CntNoWrap_A	8367630	7688487	0	0
DetectStDropOut_A	8367630	1	0	0
DetectedOut_A	8367630	84729	0	0
DetectedPulseOut_A	8367630	50	0	0
DisabledIdleSt_A	8367630	7173731	0	0
DisabledNoDetection_A	8367630	7176138	0	0
EnterDebounceSt_A	8367630	58	0	0
EnterDetectSt_A	8367630	51	0	0
EnterStableSt_A	8367630	50	0	0
PulseIsPulse_A	8367630	50	0	0
StayInStableSt	8367630	84658	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8367630	7343	0	0
gen_low_level_sva.LowLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	108	0	0
T3	13606	4	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	2	0	0
T32	0	4	0	0
T35	0	1	0	0
T36	0	3	0	0
T37	0	4	0	0
T38	0	2	0	0
T41	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T151	0	1	0	0
T166	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	82282	0	0
T3	13606	126	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	26	0	0
T32	0	118	0	0
T35	0	55	0	0
T36	0	92	0	0
T37	0	88	0	0
T38	0	26	0	0
T41	0	28	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T151	0	43	0	0
T166	0	61	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7688487	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	4508	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	1	0	0
T36	829	1	0	0
T37	29817	0	0	0
T58	496	0	0	0
T59	490	0	0	0
T95	2966	0	0	0
T96	422	0	0	0
T101	625	0	0	0
T102	699	0	0	0
T144	501	0	0	0
T145	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	84729	0	0
T3	13606	78	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	21	0	0
T32	0	198	0	0
T37	0	126	0	0
T38	0	58	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T68	0	205	0	0
T74	0	79	0	0
T105	0	44	0	0
T165	0	83	0	0
T166	0	274	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	50	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	1	0	0
T32	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T68	0	2	0	0
T74	0	2	0	0
T105	0	1	0	0
T165	0	2	0	0
T166	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7173731	0	0
T1	134786	129564	0	0
T2	37113	36684	0	0
T3	13606	3947	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7176138	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	3972	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	58	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	1	0	0
T32	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T151	0	1	0	0
T166	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	51	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	1	0	0
T32	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T74	0	2	0	0
T105	0	1	0	0
T165	0	2	0	0
T166	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	50	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	1	0	0
T32	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T68	0	2	0	0
T74	0	2	0	0
T105	0	1	0	0
T165	0	2	0	0
T166	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	50	0	0
T3	13606	2	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	1	0	0
T32	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T68	0	2	0	0
T74	0	2	0	0
T105	0	1	0	0
T165	0	2	0	0
T166	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	84658	0	0
T3	13606	75	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	20	0	0
T32	0	195	0	0
T37	0	123	0	0
T38	0	57	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T68	0	202	0	0
T74	0	76	0	0
T105	0	42	0	0
T165	0	80	0	0
T166	0	272	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7343	0	0
T1	134786	26	0	0
T2	37113	42	0	0
T3	13606	52	0	0
T4	669	3	0	0
T5	506	5	0	0
T6	0	30	0	0
T13	522	4	0	0
T14	421	3	0	0
T15	522	6	0	0
T16	430	2	0	0
T17	689	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	29	0	0
T3	13606	1	0	0
T6	7683	0	0	0
T7	4175	0	0	0
T8	1966	0	0	0
T10	0	1	0	0
T32	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T49	422	0	0	0
T50	604	0	0	0
T51	684	0	0	0
T68	0	1	0	0
T72	0	2	0	0
T74	0	1	0	0
T146	0	1	0	0
T165	0	1	0	0