Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T23
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T23
1	0	Covered	T2,T6,T39
1	1	Covered	T2,T6,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T39
0	1	Covered	T23,T41,T79
1	0	Covered	T41,T79,T200

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T39
0	1	Covered	T2,T6,T39
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T39
1	-	Covered	T2,T6,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T23
DetectSt	168	Covered	T2,T6,T23
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T6,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T23
DebounceSt->IdleSt	163	Covered	T23,T41,T66
DetectSt->IdleSt	186	Covered	T23,T41,T79
DetectSt->StableSt	191	Covered	T2,T6,T39
IdleSt->DebounceSt	148	Covered	T2,T6,T23
StableSt->IdleSt	206	Covered	T2,T6,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T6,T23
0	1	Covered	T2,T6,T23
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T23
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T23
IdleSt	0	-	-	-	-	-	-	Covered	T2,T6,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T41,T66
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T23
DetectSt	-	-	-	-	1	-	-	Covered	T23,T41,T79
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T39
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T39
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T39
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T39
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	3219	0	0
CntIncr_A	8367630	112767	0	0
CntNoWrap_A	8367630	7685376	0	0
DetectStDropOut_A	8367630	413	0	0
DetectedOut_A	8367630	90807	0	0
DetectedPulseOut_A	8367630	1037	0	0
DisabledIdleSt_A	8367630	7193951	0	0
DisabledNoDetection_A	8367630	7196201	0	0
EnterDebounceSt_A	8367630	1622	0	0
EnterDetectSt_A	8367630	1599	0	0
EnterStableSt_A	8367630	1037	0	0
PulseIsPulse_A	8367630	1037	0	0
StayInStableSt	8367630	89642	0	0
gen_high_event_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_high_level_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	900	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	3219	0	0
T2	37113	28	0	0
T3	13606	0	0	0
T6	7683	26	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T23	0	30	0	0
T28	0	20	0	0
T29	0	36	0	0
T30	0	30	0	0
T31	0	30	0	0
T39	0	26	0	0
T41	0	16	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	112767	0	0
T2	37113	798	0	0
T3	13606	0	0	0
T6	7683	819	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T23	0	989	0	0
T28	0	860	0	0
T29	0	882	0	0
T30	0	720	0	0
T31	0	780	0	0
T39	0	559	0	0
T41	0	512	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	708	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7685376	0	0
T1	134786	129564	0	0
T2	37113	36656	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	413	0	0
T11	9861	0	0	0
T12	2246	0	0	0
T23	4716	7	0	0
T28	27116	0	0	0
T39	8094	0	0	0
T41	0	1	0	0
T53	1286	0	0	0
T54	1004	0	0	0
T60	522	0	0	0
T66	0	1	0	0
T79	0	10	0	0
T80	0	14	0	0
T81	0	11	0	0
T82	0	4	0	0
T83	0	8	0	0
T94	502	0	0	0
T103	428	0	0	0
T158	0	23	0	0
T201	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	90807	0	0
T2	37113	2108	0	0
T3	13606	0	0	0
T6	7683	137	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	1038	0	0
T29	0	915	0	0
T30	0	808	0	0
T31	0	1598	0	0
T39	0	474	0	0
T41	0	397	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	2039	0	0
T202	0	2000	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	1037	0	0
T2	37113	14	0	0
T3	13606	0	0	0
T6	7683	13	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	10	0	0
T29	0	18	0	0
T30	0	15	0	0
T31	0	15	0	0
T39	0	13	0	0
T41	0	5	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	12	0	0
T202	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7193951	0	0
T1	134786	129564	0	0
T2	37113	31268	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7196201	0	0
T1	134786	129581	0	0
T2	37113	31275	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	1622	0	0
T2	37113	14	0	0
T3	13606	0	0	0
T6	7683	13	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T23	0	23	0	0
T28	0	10	0	0
T29	0	18	0	0
T30	0	15	0	0
T31	0	15	0	0
T39	0	13	0	0
T41	0	9	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	1599	0	0
T2	37113	14	0	0
T3	13606	0	0	0
T6	7683	13	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T23	0	7	0	0
T28	0	10	0	0
T29	0	18	0	0
T30	0	15	0	0
T31	0	15	0	0
T39	0	13	0	0
T41	0	7	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	1037	0	0
T2	37113	14	0	0
T3	13606	0	0	0
T6	7683	13	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	10	0	0
T29	0	18	0	0
T30	0	15	0	0
T31	0	15	0	0
T39	0	13	0	0
T41	0	5	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	12	0	0
T202	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	1037	0	0
T2	37113	14	0	0
T3	13606	0	0	0
T6	7683	13	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	10	0	0
T29	0	18	0	0
T30	0	15	0	0
T31	0	15	0	0
T39	0	13	0	0
T41	0	5	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	12	0	0
T202	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	89642	0	0
T2	37113	2087	0	0
T3	13606	0	0	0
T6	7683	124	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	1025	0	0
T29	0	896	0	0
T30	0	792	0	0
T31	0	1581	0	0
T39	0	461	0	0
T41	0	392	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	2027	0	0
T202	0	1971	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	900	0	0
T2	37113	7	0	0
T3	13606	0	0	0
T6	7683	13	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	7	0	0
T29	0	17	0	0
T30	0	14	0	0
T31	0	13	0	0
T39	0	13	0	0
T41	0	5	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	12	0	0
T202	0	21	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T37,T72,T84
1	0	Covered	T41,T66

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T41

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T2,T41,T203
DetectSt->IdleSt	186	Covered	T41,T37,T66
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T203,T37
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T41,T37,T66
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	978	0	0
CntIncr_A	8367630	48310	0	0
CntNoWrap_A	8367630	7687617	0	0
DetectStDropOut_A	8367630	40	0	0
DetectedOut_A	8367630	19921	0	0
DetectedPulseOut_A	8367630	407	0	0
DisabledIdleSt_A	8367630	7271094	0	0
DisabledNoDetection_A	8367630	7272791	0	0
EnterDebounceSt_A	8367630	528	0	0
EnterDetectSt_A	8367630	452	0	0
EnterStableSt_A	8367630	407	0	0
PulseIsPulse_A	8367630	407	0	0
StayInStableSt	8367630	19478	0	0
gen_high_level_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	367	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	978	0	0
T1	134786	4	0	0
T2	37113	5	0	0
T3	13606	2	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	2	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	4	0	0
T29	0	2	0	0
T33	0	2	0	0
T41	0	8	0	0
T78	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	48310	0	0
T1	134786	181	0	0
T2	37113	154	0	0
T3	13606	25	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	25	0	0
T11	0	25	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	126	0	0
T29	0	74	0	0
T33	0	25	0	0
T41	0	230	0	0
T78	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7687617	0	0
T1	134786	129560	0	0
T2	37113	36679	0	0
T3	13606	4510	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	40	0	0
T37	29817	1	0	0
T38	324527	0	0	0
T59	490	0	0	0
T62	9037	0	0	0
T72	0	3	0	0
T84	0	11	0	0
T86	0	1	0	0
T87	0	2	0	0
T88	0	2	0	0
T89	0	1	0	0
T90	0	1	0	0
T92	0	2	0	0
T93	0	2	0	0
T95	2966	0	0	0
T96	422	0	0	0
T97	1063	0	0	0
T98	857	0	0	0
T99	526	0	0	0
T100	761	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	19921	0	0
T1	134786	35	0	0
T2	37113	110	0	0
T3	13606	3	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	3	0	0
T11	0	4	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	167	0	0
T29	0	47	0	0
T33	0	3	0	0
T41	0	96	0	0
T78	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	407	0	0
T1	134786	2	0	0
T2	37113	2	0	0
T3	13606	1	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T33	0	1	0	0
T41	0	1	0	0
T78	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7271094	0	0
T1	134786	128509	0	0
T2	37113	34583	0	0
T3	13606	4427	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7272791	0	0
T1	134786	128523	0	0
T2	37113	34591	0	0
T3	13606	4452	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	528	0	0
T1	134786	2	0	0
T2	37113	3	0	0
T3	13606	1	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T33	0	1	0	0
T41	0	5	0	0
T78	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	452	0	0
T1	134786	2	0	0
T2	37113	2	0	0
T3	13606	1	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T33	0	1	0	0
T41	0	3	0	0
T78	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	407	0	0
T1	134786	2	0	0
T2	37113	2	0	0
T3	13606	1	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T33	0	1	0	0
T41	0	1	0	0
T78	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	407	0	0
T1	134786	2	0	0
T2	37113	2	0	0
T3	13606	1	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T33	0	1	0	0
T41	0	1	0	0
T78	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	19478	0	0
T1	134786	33	0	0
T2	37113	107	0	0
T3	13606	2	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	2	0	0
T11	0	3	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	165	0	0
T29	0	45	0	0
T33	0	2	0	0
T41	0	95	0	0
T78	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	367	0	0
T1	134786	2	0	0
T2	37113	1	0	0
T3	13606	1	0	0
T4	669	0	0	0
T5	506	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	2	0	0
T30	0	1	0	0
T33	0	1	0	0
T42	0	4	0	0
T78	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T23
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T23
1	0	Covered	T2,T6,T39
1	1	Covered	T2,T6,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T39
0	1	Covered	T23,T39,T30
1	0	Covered	T39,T30,T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T28
0	1	Covered	T2,T6,T28
1	0	Covered	T204

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T28
1	-	Covered	T2,T6,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T23
DetectSt	168	Covered	T2,T6,T23
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T6,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T23
DebounceSt->IdleSt	163	Covered	T23,T41,T66
DetectSt->IdleSt	186	Covered	T23,T39,T30
DetectSt->StableSt	191	Covered	T2,T6,T28
IdleSt->DebounceSt	148	Covered	T2,T6,T23
StableSt->IdleSt	206	Covered	T2,T6,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T6,T23
0	1	Covered	T2,T6,T23
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T23
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T23
IdleSt	0	-	-	-	-	-	-	Covered	T2,T6,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T41,T66
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T23
DetectSt	-	-	-	-	1	-	-	Covered	T23,T39,T30
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T28
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T39
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T28
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T28
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	2931	0	0
CntIncr_A	8367630	101927	0	0
CntNoWrap_A	8367630	7685664	0	0
DetectStDropOut_A	8367630	422	0	0
DetectedOut_A	8367630	73775	0	0
DetectedPulseOut_A	8367630	887	0	0
DisabledIdleSt_A	8367630	7204119	0	0
DisabledNoDetection_A	8367630	7206378	0	0
EnterDebounceSt_A	8367630	1483	0	0
EnterDetectSt_A	8367630	1449	0	0
EnterStableSt_A	8367630	887	0	0
PulseIsPulse_A	8367630	887	0	0
StayInStableSt	8367630	72768	0	0
gen_high_event_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_high_level_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	742	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	2931	0	0
T2	37113	40	0	0
T3	13606	0	0	0
T6	7683	12	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T23	0	26	0	0
T28	0	54	0	0
T29	0	52	0	0
T30	0	50	0	0
T31	0	22	0	0
T39	0	28	0	0
T41	0	14	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	58	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	101927	0	0
T2	37113	980	0	0
T3	13606	0	0	0
T6	7683	360	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T23	0	1032	0	0
T28	0	1971	0	0
T29	0	1794	0	0
T30	0	2266	0	0
T31	0	803	0	0
T39	0	1086	0	0
T41	0	319	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	2581	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7685664	0	0
T1	134786	129564	0	0
T2	37113	36644	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	422	0	0
T11	9861	0	0	0
T12	2246	0	0	0
T23	4716	2	0	0
T28	27116	0	0	0
T30	0	3	0	0
T39	8094	2	0	0
T53	1286	0	0	0
T54	1004	0	0	0
T60	522	0	0	0
T66	0	1	0	0
T69	0	21	0	0
T80	0	8	0	0
T81	0	14	0	0
T82	0	4	0	0
T83	0	21	0	0
T94	502	0	0	0
T103	428	0	0	0
T205	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	73775	0	0
T2	37113	2625	0	0
T3	13606	0	0	0
T6	7683	78	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T27	0	1298	0	0
T28	0	3834	0	0
T29	0	358	0	0
T31	0	386	0	0
T41	0	421	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	237	0	0
T79	0	715	0	0
T202	0	357	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	887	0	0
T2	37113	20	0	0
T3	13606	0	0	0
T6	7683	6	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T27	0	16	0	0
T28	0	27	0	0
T29	0	26	0	0
T31	0	11	0	0
T41	0	5	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	29	0	0
T79	0	15	0	0
T202	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7204119	0	0
T1	134786	129564	0	0
T2	37113	30957	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7206378	0	0
T1	134786	129581	0	0
T2	37113	30959	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	1483	0	0
T2	37113	20	0	0
T3	13606	0	0	0
T6	7683	6	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T23	0	24	0	0
T28	0	27	0	0
T29	0	26	0	0
T30	0	25	0	0
T31	0	11	0	0
T39	0	14	0	0
T41	0	9	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	29	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	1449	0	0
T2	37113	20	0	0
T3	13606	0	0	0
T6	7683	6	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T23	0	2	0	0
T28	0	27	0	0
T29	0	26	0	0
T30	0	25	0	0
T31	0	11	0	0
T39	0	14	0	0
T41	0	5	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	29	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	887	0	0
T2	37113	20	0	0
T3	13606	0	0	0
T6	7683	6	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T27	0	16	0	0
T28	0	27	0	0
T29	0	26	0	0
T31	0	11	0	0
T41	0	5	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	29	0	0
T79	0	15	0	0
T202	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	887	0	0
T2	37113	20	0	0
T3	13606	0	0	0
T6	7683	6	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T27	0	16	0	0
T28	0	27	0	0
T29	0	26	0	0
T31	0	11	0	0
T41	0	5	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	29	0	0
T79	0	15	0	0
T202	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	72768	0	0
T2	37113	2593	0	0
T3	13606	0	0	0
T6	7683	72	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T27	0	1279	0	0
T28	0	3799	0	0
T29	0	331	0	0
T31	0	374	0	0
T41	0	416	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	208	0	0
T79	0	700	0	0
T202	0	351	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	742	0	0
T2	37113	8	0	0
T3	13606	0	0	0
T6	7683	6	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T27	0	13	0	0
T28	0	19	0	0
T29	0	25	0	0
T31	0	10	0	0
T41	0	5	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	29	0	0
T79	0	15	0	0
T202	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T2,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T28
0	1	Covered	T64,T65,T77
1	0	Covered	T41,T66

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T28
0	1	Covered	T1,T2,T28
1	0	Covered	T41,T66,T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T28
1	-	Covered	T1,T2,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T28
DetectSt	168	Covered	T1,T2,T28
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T2,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T28
DebounceSt->IdleSt	163	Covered	T41,T64,T26
DetectSt->IdleSt	186	Covered	T41,T64,T65
DetectSt->StableSt	191	Covered	T1,T2,T28
IdleSt->DebounceSt	148	Covered	T1,T2,T28
StableSt->IdleSt	206	Covered	T1,T2,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T28
0	1	Covered	T1,T2,T28
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T28
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T28
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T64,T26,T134
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T28
DetectSt	-	-	-	-	1	-	-	Covered	T41,T64,T65
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T28
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T28
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T28
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	864	0	0
CntIncr_A	8367630	47347	0	0
CntNoWrap_A	8367630	7687731	0	0
DetectStDropOut_A	8367630	63	0	0
DetectedOut_A	8367630	16722	0	0
DetectedPulseOut_A	8367630	342	0	0
DisabledIdleSt_A	8367630	7304684	0	0
DisabledNoDetection_A	8367630	7306469	0	0
EnterDebounceSt_A	8367630	455	0	0
EnterDetectSt_A	8367630	409	0	0
EnterStableSt_A	8367630	342	0	0
PulseIsPulse_A	8367630	342	0	0
StayInStableSt	8367630	16353	0	0
gen_high_level_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	310	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	864	0	0
T1	134786	2	0	0
T2	37113	10	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	4	0	0
T29	0	2	0	0
T31	0	2	0	0
T35	0	2	0	0
T41	0	8	0	0
T42	0	4	0	0
T203	0	10	0	0
T206	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	47347	0	0
T1	134786	183	0	0
T2	37113	200	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	152	0	0
T29	0	72	0	0
T31	0	65	0	0
T35	0	116	0	0
T41	0	257	0	0
T42	0	152	0	0
T203	0	660	0	0
T206	0	405	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7687731	0	0
T1	134786	129562	0	0
T2	37113	36674	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	63	0	0
T64	13393	1	0	0
T65	34429	2	0	0
T77	0	5	0	0
T207	0	10	0	0
T208	0	3	0	0
T209	0	4	0	0
T210	0	1	0	0
T211	0	6	0	0
T212	0	6	0	0
T213	0	12	0	0
T214	495	0	0	0
T215	588	0	0	0
T216	425	0	0	0
T217	407	0	0	0
T218	492	0	0	0
T219	452	0	0	0
T220	1308	0	0	0
T221	874	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	16722	0	0
T1	134786	6	0	0
T2	37113	402	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	141	0	0
T29	0	49	0	0
T31	0	30	0	0
T35	0	60	0	0
T41	0	96	0	0
T42	0	147	0	0
T203	0	375	0	0
T206	0	112	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	342	0	0
T1	134786	1	0	0
T2	37113	5	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T31	0	1	0	0
T35	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T203	0	5	0	0
T206	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7304684	0	0
T1	134786	128591	0	0
T2	37113	34071	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7306469	0	0
T1	134786	128606	0	0
T2	37113	34074	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	455	0	0
T1	134786	1	0	0
T2	37113	5	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T31	0	1	0	0
T35	0	1	0	0
T41	0	5	0	0
T42	0	2	0	0
T203	0	5	0	0
T206	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	409	0	0
T1	134786	1	0	0
T2	37113	5	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T31	0	1	0	0
T35	0	1	0	0
T41	0	3	0	0
T42	0	2	0	0
T203	0	5	0	0
T206	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	342	0	0
T1	134786	1	0	0
T2	37113	5	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T31	0	1	0	0
T35	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T203	0	5	0	0
T206	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	342	0	0
T1	134786	1	0	0
T2	37113	5	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T31	0	1	0	0
T35	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T203	0	5	0	0
T206	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	16353	0	0
T1	134786	5	0	0
T2	37113	397	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	138	0	0
T29	0	48	0	0
T31	0	29	0	0
T35	0	59	0	0
T41	0	95	0	0
T42	0	145	0	0
T203	0	370	0	0
T206	0	109	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	310	0	0
T1	134786	1	0	0
T2	37113	5	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	1	0	0
T35	0	1	0	0
T42	0	2	0	0
T202	0	1	0	0
T203	0	5	0	0
T206	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T23
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T23
1	0	Covered	T2,T6,T39
1	1	Covered	T2,T6,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T39
0	1	Covered	T23,T41,T80
1	0	Covered	T41,T29,T202

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T39
0	1	Covered	T2,T6,T39
1	0	Covered	T41

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T39
1	-	Covered	T2,T6,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T23
DetectSt	168	Covered	T2,T6,T23
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T6,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T23
DebounceSt->IdleSt	163	Covered	T23,T41,T66
DetectSt->IdleSt	186	Covered	T23,T41,T29
DetectSt->StableSt	191	Covered	T2,T6,T39
IdleSt->DebounceSt	148	Covered	T2,T6,T23
StableSt->IdleSt	206	Covered	T2,T6,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T6,T23
0	1	Covered	T2,T6,T23
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T23
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T23
IdleSt	0	-	-	-	-	-	-	Covered	T2,T6,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T41,T66
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T23
DetectSt	-	-	-	-	1	-	-	Covered	T23,T41,T29
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T39
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T39
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T39
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T39
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	2905	0	0
CntIncr_A	8367630	100836	0	0
CntNoWrap_A	8367630	7685690	0	0
DetectStDropOut_A	8367630	439	0	0
DetectedOut_A	8367630	68478	0	0
DetectedPulseOut_A	8367630	779	0	0
DisabledIdleSt_A	8367630	7210251	0	0
DisabledNoDetection_A	8367630	7212517	0	0
EnterDebounceSt_A	8367630	1467	0	0
EnterDetectSt_A	8367630	1439	0	0
EnterStableSt_A	8367630	779	0	0
PulseIsPulse_A	8367630	779	0	0
StayInStableSt	8367630	67586	0	0
gen_high_event_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_high_level_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	665	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	2905	0	0
T2	37113	40	0	0
T3	13606	0	0	0
T6	7683	36	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T23	0	24	0	0
T28	0	54	0	0
T29	0	28	0	0
T30	0	48	0	0
T31	0	16	0	0
T39	0	34	0	0
T41	0	16	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	44	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	100836	0	0
T2	37113	880	0	0
T3	13606	0	0	0
T6	7683	1224	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T23	0	903	0	0
T28	0	1890	0	0
T29	0	986	0	0
T30	0	1368	0	0
T31	0	456	0	0
T39	0	1275	0	0
T41	0	379	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	1804	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7685690	0	0
T1	134786	129564	0	0
T2	37113	36644	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	439	0	0
T11	9861	0	0	0
T12	2246	0	0	0
T23	4716	3	0	0
T28	27116	0	0	0
T39	8094	0	0	0
T41	0	1	0	0
T53	1286	0	0	0
T54	1004	0	0	0
T60	522	0	0	0
T66	0	1	0	0
T67	0	8	0	0
T69	0	21	0	0
T80	0	26	0	0
T81	0	14	0	0
T82	0	10	0	0
T94	502	0	0	0
T103	428	0	0	0
T200	0	12	0	0
T222	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	68478	0	0
T2	37113	2725	0	0
T3	13606	0	0	0
T6	7683	1370	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T27	0	393	0	0
T28	0	3915	0	0
T30	0	1802	0	0
T31	0	334	0	0
T39	0	224	0	0
T41	0	396	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	330	0	0
T79	0	304	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	779	0	0
T2	37113	20	0	0
T3	13606	0	0	0
T6	7683	18	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T27	0	4	0	0
T28	0	27	0	0
T30	0	24	0	0
T31	0	8	0	0
T39	0	17	0	0
T41	0	5	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	22	0	0
T79	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7210251	0	0
T1	134786	129564	0	0
T2	37113	30957	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7212517	0	0
T1	134786	129581	0	0
T2	37113	30959	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	1467	0	0
T2	37113	20	0	0
T3	13606	0	0	0
T6	7683	18	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T23	0	21	0	0
T28	0	27	0	0
T29	0	14	0	0
T30	0	24	0	0
T31	0	8	0	0
T39	0	17	0	0
T41	0	9	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	1439	0	0
T2	37113	20	0	0
T3	13606	0	0	0
T6	7683	18	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T23	0	3	0	0
T28	0	27	0	0
T29	0	14	0	0
T30	0	24	0	0
T31	0	8	0	0
T39	0	17	0	0
T41	0	7	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	22	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	779	0	0
T2	37113	20	0	0
T3	13606	0	0	0
T6	7683	18	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T27	0	4	0	0
T28	0	27	0	0
T30	0	24	0	0
T31	0	8	0	0
T39	0	17	0	0
T41	0	5	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	22	0	0
T79	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	779	0	0
T2	37113	20	0	0
T3	13606	0	0	0
T6	7683	18	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T27	0	4	0	0
T28	0	27	0	0
T30	0	24	0	0
T31	0	8	0	0
T39	0	17	0	0
T41	0	5	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	22	0	0
T79	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	67586	0	0
T2	37113	2693	0	0
T3	13606	0	0	0
T6	7683	1352	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T27	0	389	0	0
T28	0	3880	0	0
T30	0	1774	0	0
T31	0	326	0	0
T39	0	207	0	0
T41	0	391	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	308	0	0
T79	0	294	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	665	0	0
T2	37113	8	0	0
T3	13606	0	0	0
T6	7683	18	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T27	0	4	0	0
T28	0	19	0	0
T30	0	20	0	0
T31	0	8	0	0
T39	0	17	0	0
T41	0	4	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	22	0	0
T79	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T2,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T65,T26,T187
1	0	Covered	T41,T66

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T6
1	-	Covered	T1,T2,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T6
DetectSt	168	Covered	T1,T2,T6
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T6
DebounceSt->IdleSt	163	Covered	T41,T64,T65
DetectSt->IdleSt	186	Covered	T41,T65,T26
DetectSt->StableSt	191	Covered	T1,T2,T6
IdleSt->DebounceSt	148	Covered	T1,T2,T6
StableSt->IdleSt	206	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T64,T65,T223
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T6
DetectSt	-	-	-	-	1	-	-	Covered	T41,T65,T26
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T6
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T6
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T6
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	919	0	0
CntIncr_A	8367630	52521	0	0
CntNoWrap_A	8367630	7687676	0	0
DetectStDropOut_A	8367630	118	0	0
DetectedOut_A	8367630	13704	0	0
DetectedPulseOut_A	8367630	310	0	0
DisabledIdleSt_A	8367630	7300185	0	0
DisabledNoDetection_A	8367630	7301947	0	0
EnterDebounceSt_A	8367630	487	0	0
EnterDetectSt_A	8367630	433	0	0
EnterStableSt_A	8367630	310	0	0
PulseIsPulse_A	8367630	310	0	0
StayInStableSt	8367630	13361	0	0
gen_high_level_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	276	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	919	0	0
T1	134786	2	0	0
T2	37113	16	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T6	0	4	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	12	0	0
T30	0	8	0	0
T35	0	4	0	0
T41	0	8	0	0
T42	0	4	0	0
T203	0	6	0	0
T206	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	52521	0	0
T1	134786	141	0	0
T2	37113	600	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T6	0	104	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	564	0	0
T30	0	296	0	0
T35	0	216	0	0
T41	0	231	0	0
T42	0	246	0	0
T203	0	609	0	0
T206	0	428	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7687676	0	0
T1	134786	129562	0	0
T2	37113	36668	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	118	0	0
T26	0	1	0	0
T65	34429	10	0	0
T77	0	4	0	0
T84	0	4	0	0
T87	0	5	0	0
T187	0	1	0	0
T216	425	0	0	0
T217	407	0	0	0
T218	492	0	0	0
T219	452	0	0	0
T220	1308	0	0	0
T221	874	0	0	0
T224	0	2	0	0
T225	0	16	0	0
T226	0	4	0	0
T227	0	12	0	0
T228	641	0	0	0
T229	497	0	0	0
T230	489	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	13704	0	0
T1	134786	47	0	0
T2	37113	360	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T6	0	168	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	317	0	0
T30	0	209	0	0
T35	0	138	0	0
T41	0	96	0	0
T42	0	52	0	0
T203	0	12	0	0
T206	0	263	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	310	0	0
T1	134786	1	0	0
T2	37113	8	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T6	0	2	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	6	0	0
T30	0	4	0	0
T35	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T203	0	3	0	0
T206	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7300185	0	0
T1	134786	128591	0	0
T2	37113	33971	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7301947	0	0
T1	134786	128606	0	0
T2	37113	33974	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	487	0	0
T1	134786	1	0	0
T2	37113	8	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T6	0	2	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	6	0	0
T30	0	4	0	0
T35	0	2	0	0
T41	0	5	0	0
T42	0	2	0	0
T203	0	3	0	0
T206	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	433	0	0
T1	134786	1	0	0
T2	37113	8	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T6	0	2	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	6	0	0
T30	0	4	0	0
T35	0	2	0	0
T41	0	3	0	0
T42	0	2	0	0
T203	0	3	0	0
T206	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	310	0	0
T1	134786	1	0	0
T2	37113	8	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T6	0	2	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	6	0	0
T30	0	4	0	0
T35	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T203	0	3	0	0
T206	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	310	0	0
T1	134786	1	0	0
T2	37113	8	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T6	0	2	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	6	0	0
T30	0	4	0	0
T35	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T203	0	3	0	0
T206	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	13361	0	0
T1	134786	46	0	0
T2	37113	352	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T6	0	166	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	311	0	0
T30	0	205	0	0
T35	0	136	0	0
T41	0	95	0	0
T42	0	50	0	0
T203	0	9	0	0
T206	0	259	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	276	0	0
T1	134786	1	0	0
T2	37113	8	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T6	0	2	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	6	0	0
T30	0	4	0	0
T35	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T203	0	3	0	0
T206	0	4	0	0