Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T23
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T23
1	0	Covered	T2,T6,T39
1	1	Covered	T2,T6,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T39
0	1	Covered	T41,T80,T200
1	0	Covered	T41,T200,T66

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T39
0	1	Covered	T2,T6,T39
1	0	Covered	T70,T231

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T39
1	-	Covered	T2,T6,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T23
DetectSt	168	Covered	T2,T6,T39
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T6,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T39
DebounceSt->IdleSt	163	Covered	T23,T41,T66
DetectSt->IdleSt	186	Covered	T41,T80,T200
DetectSt->StableSt	191	Covered	T2,T6,T39
IdleSt->DebounceSt	148	Covered	T2,T6,T23
StableSt->IdleSt	206	Covered	T2,T6,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T6,T23
0	1	Covered	T2,T6,T23
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T39
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T23
IdleSt	0	-	-	-	-	-	-	Covered	T2,T6,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T41,T66
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T23
DetectSt	-	-	-	-	1	-	-	Covered	T41,T80,T200
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T39
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T39
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T39
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T39
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	3229	0	0
CntIncr_A	8367630	109842	0	0
CntNoWrap_A	8367630	7685366	0	0
DetectStDropOut_A	8367630	535	0	0
DetectedOut_A	8367630	93624	0	0
DetectedPulseOut_A	8367630	892	0	0
DisabledIdleSt_A	8367630	7189774	0	0
DisabledNoDetection_A	8367630	7192030	0	0
EnterDebounceSt_A	8367630	1621	0	0
EnterDetectSt_A	8367630	1610	0	0
EnterStableSt_A	8367630	892	0	0
PulseIsPulse_A	8367630	892	0	0
StayInStableSt	8367630	92609	0	0
gen_high_event_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_high_level_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	766	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	3229	0	0
T2	37113	28	0	0
T3	13606	0	0	0
T6	7683	28	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T23	0	5	0	0
T28	0	14	0	0
T29	0	60	0	0
T30	0	30	0	0
T31	0	22	0	0
T39	0	54	0	0
T41	0	16	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	34	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	109842	0	0
T2	37113	840	0	0
T3	13606	0	0	0
T6	7683	924	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T23	0	215	0	0
T28	0	525	0	0
T29	0	1470	0	0
T30	0	705	0	0
T31	0	627	0	0
T39	0	1917	0	0
T41	0	372	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	1088	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7685366	0	0
T1	134786	129564	0	0
T2	37113	36656	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	535	0	0
T29	13974	0	0	0
T41	6914	1	0	0
T66	0	1	0	0
T70	0	26	0	0
T78	483	0	0	0
T80	0	22	0	0
T81	0	27	0	0
T82	0	19	0	0
T83	0	11	0	0
T118	555	0	0	0
T119	426	0	0	0
T120	422	0	0	0
T121	422	0	0	0
T122	505	0	0	0
T158	0	15	0	0
T200	0	10	0	0
T232	0	19	0	0
T233	506	0	0	0
T234	900	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	93624	0	0
T2	37113	2066	0	0
T3	13606	0	0	0
T6	7683	242	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	878	0	0
T29	0	2227	0	0
T30	0	1761	0	0
T31	0	859	0	0
T39	0	1752	0	0
T41	0	319	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	557	0	0
T202	0	1321	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	892	0	0
T2	37113	14	0	0
T3	13606	0	0	0
T6	7683	14	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	7	0	0
T29	0	30	0	0
T30	0	15	0	0
T31	0	11	0	0
T39	0	27	0	0
T41	0	5	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	17	0	0
T202	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7189774	0	0
T1	134786	129564	0	0
T2	37113	31268	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7192030	0	0
T1	134786	129581	0	0
T2	37113	31275	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	1621	0	0
T2	37113	14	0	0
T3	13606	0	0	0
T6	7683	14	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T23	0	5	0	0
T28	0	7	0	0
T29	0	30	0	0
T30	0	15	0	0
T31	0	11	0	0
T39	0	27	0	0
T41	0	9	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	17	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	1610	0	0
T2	37113	14	0	0
T3	13606	0	0	0
T6	7683	14	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	7	0	0
T29	0	30	0	0
T30	0	15	0	0
T31	0	11	0	0
T39	0	27	0	0
T41	0	7	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	17	0	0
T202	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	892	0	0
T2	37113	14	0	0
T3	13606	0	0	0
T6	7683	14	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	7	0	0
T29	0	30	0	0
T30	0	15	0	0
T31	0	11	0	0
T39	0	27	0	0
T41	0	5	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	17	0	0
T202	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	892	0	0
T2	37113	14	0	0
T3	13606	0	0	0
T6	7683	14	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	7	0	0
T29	0	30	0	0
T30	0	15	0	0
T31	0	11	0	0
T39	0	27	0	0
T41	0	5	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	17	0	0
T202	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	92609	0	0
T2	37113	2045	0	0
T3	13606	0	0	0
T6	7683	228	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	869	0	0
T29	0	2195	0	0
T30	0	1745	0	0
T31	0	847	0	0
T39	0	1725	0	0
T41	0	314	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	540	0	0
T202	0	1307	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	766	0	0
T2	37113	7	0	0
T3	13606	0	0	0
T6	7683	14	0	0
T7	4175	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T28	0	5	0	0
T29	0	28	0	0
T30	0	14	0	0
T31	0	10	0	0
T39	0	27	0	0
T41	0	5	0	0
T46	422	0	0	0
T47	428	0	0	0
T48	546	0	0	0
T62	0	17	0	0
T202	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T2,T41

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T41
0	1	Covered	T134,T224,T66
1	0	Covered	T41,T66

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T41
0	1	Covered	T1,T29,T42
1	0	Covered	T235

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T41
1	-	Covered	T1,T41,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T41
DetectSt	168	Covered	T1,T2,T41
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T2,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T41
DebounceSt->IdleSt	163	Covered	T41,T64,T26
DetectSt->IdleSt	186	Covered	T41,T134,T224
DetectSt->StableSt	191	Covered	T1,T2,T41
IdleSt->DebounceSt	148	Covered	T1,T2,T41
StableSt->IdleSt	206	Covered	T1,T2,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T41
0	1	Covered	T1,T2,T41
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T41
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T41,T66
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T64,T26,T134
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T41
DetectSt	-	-	-	-	1	-	-	Covered	T41,T134,T224
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T41
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T41
StableSt	-	-	-	-	-	-	1	Covered	T1,T41,T29
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8367630	942	0	0
CntIncr_A	8367630	51115	0	0
CntNoWrap_A	8367630	7687653	0	0
DetectStDropOut_A	8367630	36	0	0
DetectedOut_A	8367630	20494	0	0
DetectedPulseOut_A	8367630	411	0	0
DisabledIdleSt_A	8367630	7270072	0	0
DisabledNoDetection_A	8367630	7271822	0	0
EnterDebounceSt_A	8367630	492	0	0
EnterDetectSt_A	8367630	451	0	0
EnterStableSt_A	8367630	411	0	0
PulseIsPulse_A	8367630	411	0	0
StayInStableSt	8367630	20044	0	0
gen_high_level_sva.HighLevelEvent_A	8367630	7691069	0	0
gen_not_sticky_sva.StableStDropOut_A	8367630	368	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	942	0	0
T1	134786	4	0	0
T2	37113	4	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T29	0	4	0	0
T30	0	8	0	0
T31	0	2	0	0
T37	0	2	0	0
T41	0	8	0	0
T42	0	18	0	0
T203	0	4	0	0
T206	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	51115	0	0
T1	134786	226	0	0
T2	37113	110	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T29	0	162	0	0
T30	0	332	0	0
T31	0	40	0	0
T37	0	95	0	0
T41	0	156	0	0
T42	0	1017	0	0
T203	0	232	0	0
T206	0	166	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7687653	0	0
T1	134786	129560	0	0
T2	37113	36680	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	36	0	0
T66	0	1	0	0
T87	0	4	0	0
T90	0	9	0	0
T109	1706	0	0	0
T134	8028	6	0	0
T135	526	0	0	0
T136	421	0	0	0
T137	432	0	0	0
T139	14752	0	0	0
T148	0	4	0	0
T205	12449	0	0	0
T224	0	2	0	0
T236	0	3	0	0
T237	0	7	0	0
T238	38872	0	0	0
T239	444	0	0	0
T240	406	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	20494	0	0
T1	134786	151	0	0
T2	37113	126	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T29	0	80	0	0
T30	0	172	0	0
T31	0	55	0	0
T37	0	43	0	0
T41	0	95	0	0
T42	0	329	0	0
T203	0	182	0	0
T206	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	411	0	0
T1	134786	2	0	0
T2	37113	2	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T29	0	2	0	0
T30	0	4	0	0
T31	0	1	0	0
T37	0	1	0	0
T41	0	1	0	0
T42	0	9	0	0
T203	0	2	0	0
T206	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7270072	0	0
T1	134786	128591	0	0
T2	37113	34625	0	0
T3	13606	4512	0	0
T4	669	268	0	0
T5	506	105	0	0
T13	522	121	0	0
T14	421	20	0	0
T15	522	121	0	0
T16	430	29	0	0
T17	689	288	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7271822	0	0
T1	134786	128606	0	0
T2	37113	34633	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	492	0	0
T1	134786	2	0	0
T2	37113	2	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T29	0	2	0	0
T30	0	4	0	0
T31	0	1	0	0
T37	0	1	0	0
T41	0	5	0	0
T42	0	9	0	0
T203	0	2	0	0
T206	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	451	0	0
T1	134786	2	0	0
T2	37113	2	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T29	0	2	0	0
T30	0	4	0	0
T31	0	1	0	0
T37	0	1	0	0
T41	0	3	0	0
T42	0	9	0	0
T203	0	2	0	0
T206	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	411	0	0
T1	134786	2	0	0
T2	37113	2	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T29	0	2	0	0
T30	0	4	0	0
T31	0	1	0	0
T37	0	1	0	0
T41	0	1	0	0
T42	0	9	0	0
T203	0	2	0	0
T206	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	411	0	0
T1	134786	2	0	0
T2	37113	2	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T29	0	2	0	0
T30	0	4	0	0
T31	0	1	0	0
T37	0	1	0	0
T41	0	1	0	0
T42	0	9	0	0
T203	0	2	0	0
T206	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	20044	0	0
T1	134786	149	0	0
T2	37113	122	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T29	0	78	0	0
T30	0	168	0	0
T31	0	54	0	0
T37	0	42	0	0
T41	0	94	0	0
T42	0	320	0	0
T203	0	180	0	0
T206	0	6	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	7691069	0	0
T1	134786	129581	0	0
T2	37113	36699	0	0
T3	13606	4538	0	0
T4	669	269	0	0
T5	506	106	0	0
T13	522	122	0	0
T14	421	21	0	0
T15	522	122	0	0
T16	430	30	0	0
T17	689	289	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8367630	368	0	0
T1	134786	2	0	0
T2	37113	0	0	0
T3	13606	0	0	0
T4	669	0	0	0
T5	506	0	0	0
T13	522	0	0	0
T14	421	0	0	0
T15	522	0	0	0
T16	430	0	0	0
T17	689	0	0	0
T29	0	2	0	0
T30	0	4	0	0
T31	0	1	0	0
T37	0	1	0	0
T42	0	9	0	0
T65	0	14	0	0
T202	0	3	0	0
T203	0	2	0	0
T206	0	1	0	0