SYSRST_CTRL Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.370s	2.108ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	8.020s	2.471ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.720s	2.404ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	6.630s	2.549ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	10.370s	4.033ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.330s	2.053ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	5.836m	76.427ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	5.510s	3.341ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.650s	2.087ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.330s	2.053ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	5.510s	3.341ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	8.337m	201.086ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	7.605m	170.594ms	91	100	91.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	11.396m	303.905ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	9.029m	595.932ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.710s	2.509ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.670s	2.254ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	13.300s	4.872ms	48	50	96.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.500s	2.613ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	5.083m	2.510s	49	50	98.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	51.050s	37.879ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	8.909m	210.030ms	48	50	96.00
V2	alert_test	sysrst_ctrl_alert_test	6.080s	2.013ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.010s	2.015ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	8.080s	2.141ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	8.080s	2.141ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	10.370s	4.033ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.330s	2.053ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	5.510s	3.341ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	35.290s	9.152ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	10.370s	4.033ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.330s	2.053ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	5.510s	3.341ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	35.290s	9.152ms	20	20	100.00
V2		TOTAL			678	692	97.98
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.058m	42.014ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.857m	42.480ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.857m	42.480ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	5.723m	2.311s	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			913	932	97.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	11	73.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.12	99.38	96.46	100.00	98.08	98.85	99.71	94.34

Failure Buckets

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 5 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 5 failures.

35.sysrst_ctrl_combo_detect_with_pre_cond.3143994935762542903918275696663903228858126490138419009888587277858909189592
Line 567, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13796853034 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 24072512329 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2a
  UVM_INFO @ 24072543579 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x31
  UVM_INFO @ 24536981079 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2
  UVM_INFO @ 24536981079 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3

50.sysrst_ctrl_combo_detect_with_pre_cond.101798739158080235016882132388881119818513815041749846654760477151817416053662
Line 614, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/50.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 55461170887 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 55461170887 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 55461170887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 3 failures:

Test sysrst_ctrl_ultra_low_pwr has 1 failures.

1.sysrst_ctrl_ultra_low_pwr.81039272660921363716706651452258005675577100620986738248529579020857787015417
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2872219113 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 4734719113 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4734719113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

1.sysrst_ctrl_stress_all_with_rand_reset.111789444468036895199842254352423542465529551917292415677648979726357282668426
Line 601, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 21810457483 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 21982957483 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 373717957483 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 373828714707 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_pin_access_vseq
  UVM_INFO @ 375828141279 ps: (sysrst_ctrl_pin_access_vseq.sv:17) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Starting the body from pin_access_vseq

Test sysrst_ctrl_stress_all has 1 failures.

18.sysrst_ctrl_stress_all.100783867755207534064382757706529433435213173768273872584234909444334360078689
Line 569, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 10414214221 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 10421714221 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 12526714221 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 12586055342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 2 failures:
- Test sysrst_ctrl_ec_pwr_on_rst has 1 failures.
  - 3.sysrst_ctrl_ec_pwr_on_rst.70382559452229994196143569222970132070735101622597526214112360878027186998449
    Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  UVM_FATAL @ 2423537523 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 2423537523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
  - 32.sysrst_ctrl_stress_all_with_rand_reset.103137848845127335646730366632389210565429300929187315877340549712699305060656
    Line 622, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 62082112384 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 62082112384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:35) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (* [*] vs * [*]) has 2 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.

16.sysrst_ctrl_stress_all_with_rand_reset.85061070601878986986242480524186671077352912719976056808633300990434437535787
Line 568, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6126030767 ps: (sysrst_ctrl_pin_access_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 6126030767 ps: (sysrst_ctrl_pin_access_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 6126030767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.sysrst_ctrl_stress_all_with_rand_reset.58456955792619830641702754109904531399999967566294212608162558003504244696732
Line 572, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10994775376 ps: (sysrst_ctrl_pin_access_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 10994775376 ps: (sysrst_ctrl_pin_access_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 10994775376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-* has 2 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 2 failures.

54.sysrst_ctrl_combo_detect_with_pre_cond.63272379232889357736832268095452993894753834507877870692308217185540235365877
Line 568, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/54.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 15301026651 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-4
  UVM_INFO @ 15306026651 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0
  UVM_INFO @ 15521026651 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 15541026651 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 25574481189 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2f

84.sysrst_ctrl_combo_detect_with_pre_cond.39569644660468227252467192106289618075476073305096324473805652159129040277165
Line 584, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/84.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 28499377013 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-4
  UVM_INFO @ 28504377013 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0
  UVM_INFO @ 28699377013 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 28719377013 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 38744811303 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2b

Job sysrst_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test sysrst_ctrl_ec_pwr_on_rst has 1 failures.
  - 17.sysrst_ctrl_ec_pwr_on_rst.104677413865401995107802192797410272605386904681601638783136549793705389670193
    Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  Job ID: smart:7c7c919f-ebe0-4cff-888b-6d4b0ea65c14
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: * has 1 failures:
- Test sysrst_ctrl_stress_all has 1 failures.
  - 46.sysrst_ctrl_stress_all.1091811820602077113334557298342543480311902732618256191825091672560838925769
    Line 564, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 8855304549 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
  UVM_INFO @ 9130904549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

47.sysrst_ctrl_combo_detect_with_pre_cond.23790875538021500563322610282834543948146512699488224571596470806385090541596
Line 588, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 38792602824 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-4
  UVM_INFO @ 49042803558 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2c
  UVM_INFO @ 49043303562 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x11
  UVM_INFO @ 49912602824 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0
  UVM_INFO @ 49912602824 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1

UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:36) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

48.sysrst_ctrl_stress_all_with_rand_reset.45875207243733730756609999175266749149074236553937862079688162616773591547229
Line 589, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7904774502 ps: (sysrst_ctrl_pin_access_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 7904774502 ps: (sysrst_ctrl_pin_access_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key2_in == rdata_key2_in (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 7904774502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

81.sysrst_ctrl_combo_detect_with_pre_cond.73005196723131754466046107575516686927730957878364910868222788883532737519863
Line 574, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/81.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 25101944285 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 25101944285 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 25101944285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---