SYSRST_CTRL Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.360s	2.114ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	7.620s	2.465ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	3.630s	2.198ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	3.990s	2.552ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	11.760s	4.027ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.160s	2.038ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	4.192m	53.970ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	9.920s	2.670ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.600s	2.074ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.160s	2.038ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	9.920s	2.670ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	7.977m	184.195ms	49	50	98.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	7.138m	159.996ms	95	100	95.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	13.744m	309.912ms	49	50	98.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	9.875m	652.374ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.440s	2.508ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.560s	2.209ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	13.670s	5.341ms	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.870s	2.612ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	8.280m	2.299s	48	50	96.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.343m	31.049ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	6.380m	169.490ms	49	50	98.00
V2	alert_test	sysrst_ctrl_alert_test	5.900s	2.011ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.280s	2.014ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	7.740s	2.044ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	7.740s	2.044ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	11.760s	4.027ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.160s	2.038ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	9.920s	2.670ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	52.380s	10.803ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	11.760s	4.027ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.160s	2.038ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	9.920s	2.670ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	52.380s	10.803ms	20	20	100.00
V2		TOTAL			682	692	98.55
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.761m	42.012ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.923m	42.433ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.923m	42.433ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	4.309m	110.736ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			916	932	98.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	10	66.67
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.25	99.33	96.41	100.00	96.79	98.78	99.52	89.93

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 5 failures:

Test sysrst_ctrl_stress_all has 1 failures.

3.sysrst_ctrl_stress_all.7143885942722270462204133664451253613362206651282236600117435610563773105805
Line 564, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 12380970520 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 12483470520 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 14403470520 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 14452780718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_ultra_low_pwr has 2 failures.

24.sysrst_ctrl_ultra_low_pwr.6860233133671750797014596603286449379728376559424107097073565491548898628356
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 7444027523 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 7666527523 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 7666527523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.sysrst_ctrl_ultra_low_pwr.16285182038637473317071685991047743260927738996000267464105093296405816001813
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 8532196437 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 8864696437 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 10119696437 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 10132160726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.

28.sysrst_ctrl_stress_all_with_rand_reset.67711244281096551906910951462781543389003652244845329270520501040457354051339
Line 612, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 22240191714 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 280787691714 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 941022691714 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 941047385937 ps: (cip_base_vseq.sv:738) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Finished run 4/10 w/o reset

36.sysrst_ctrl_stress_all_with_rand_reset.112069469806095093382067750698378304833724103649249919741532651035493918031781
Line 577, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 122966799522 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 123229299522 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 123229299522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 2 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 2 failures.

6.sysrst_ctrl_combo_detect_with_pre_cond.55109072930376004433656654506345251817040447325364398753411054807057597594359
Line 595, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 41123837092 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 41123837092 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 41123837092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

58.sysrst_ctrl_combo_detect_with_pre_cond.105011543118866540972648808545859773206051892080710109818581776561523707840537
Line 621, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/58.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 86625610952 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 86625610952 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 86625610952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*]) has 2 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.

18.sysrst_ctrl_stress_all_with_rand_reset.108339777984612805629979664893429039530652029613194258186755132224811837777241
Line 680, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 63591314502 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 63591314502 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 63591314502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.sysrst_ctrl_stress_all_with_rand_reset.50352995156274900147413977882551797803296300976675690713121644158868142703160
Line 637, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 46300328573 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 46300328573 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 46300328573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: * has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

1.sysrst_ctrl_stress_all_with_rand_reset.30067441204434286909430583013136628156007794018038921320883919087260369523296
Line 673, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 71252023526 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
  UVM_INFO @ 71463858566 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_combo_detect_ec_rst_vseq
  UVM_INFO @ 73462005846 ps: (sysrst_ctrl_combo_detect_ec_rst_vseq.sv:44) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_ec_rst_vseq] Starting the body from combo detect ec_rst
  UVM_INFO @ 73651971266 ps: (sysrst_ctrl_combo_detect_ec_rst_vseq.sv:70) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_ec_rst_vseq] Value of wait_cycles:30
  UVM_INFO @ 73891002414 ps: (cip_base_vseq.sv:738) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]

UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:37) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key1_in == rdata_key1_in (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

13.sysrst_ctrl_stress_all_with_rand_reset.52144312986066354571736228752602096938978999679576995013496140755314351769312
Line 566, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6251005711 ps: (sysrst_ctrl_pin_access_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key1_in == rdata_key1_in (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 6251005711 ps: (sysrst_ctrl_pin_access_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key2_in == rdata_key2_in (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 6251005711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_vseq.sv:239) [sysrst_ctrl_combo_detect_vseq] Check failed rdata == intr_actions (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect has 1 failures.

17.sysrst_ctrl_combo_detect.26292092647281379209256209709445785198218714699647469488151371971149874470485
Line 564, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect/latest/run.log

  UVM_ERROR @ 14669263529 ps: (sysrst_ctrl_combo_detect_vseq.sv:239) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed rdata == intr_actions (0 [0x0] vs 2 [0x2])
  UVM_ERROR @ 14669263529 ps: (cip_base_vseq.sv:364) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 14669263529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:122) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key2_out_value == cfg.vif.key2_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_auto_blk_key_output has 1 failures.

33.sysrst_ctrl_auto_blk_key_output.67825307740489449574007719394488563447315136902943185454134430169451760354138
Line 560, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_auto_blk_key_output/latest/run.log

  UVM_ERROR @ 2167605519 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key2_out_value == cfg.vif.key2_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2267626282 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 32
  UVM_INFO @ 2562605519 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:47
  UVM_INFO @ 2677653614 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 54
  UVM_INFO @ 3267605519 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:93

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

53.sysrst_ctrl_combo_detect_with_pre_cond.29010200361881700361893062277130804576071695049296627216857863225072770265427
Line 618, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/53.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 57151509926 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4
  UVM_INFO @ 57161509926 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0
  UVM_INFO @ 57261509926 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 57281509926 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 67309485887 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x18

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(8) vs exp(4) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

64.sysrst_ctrl_combo_detect_with_pre_cond.74554927204086506895386297644956409929768863637924834481233290435842006181258
Line 571, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/64.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13198301747 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(8) vs exp(4) +/-4
  UVM_INFO @ 13288301747 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 13308301747 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 23419794549 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x1d
  UVM_INFO @ 23419898719 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0xe

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

69.sysrst_ctrl_combo_detect_with_pre_cond.100759572308927297937857020838232903507916033708132205960518784621414575078932
Line 611, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/69.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 68628064323 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 68723064323 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 68743064323 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 78989218176 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x31
  UVM_INFO @ 78989272230 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x2a