Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T6,T18,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T6,T7	VC_COV_UNR
1	Covered	T6,T18,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T6,T18,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T18,T25
1	0	Covered	T1,T6,T7
1	1	Covered	T6,T18,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T18,T46
0	1	Covered	T84,T102,T106
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T18,T46
0	1	Covered	T6,T18,T46
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T18,T46
1	-	Covered	T6,T18,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T18,T25
DetectSt	168	Covered	T6,T18,T46
IdleSt	163	Covered	T1,T6,T7
StableSt	191	Covered	T6,T18,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T18,T46
DebounceSt->IdleSt	163	Covered	T18,T25,T38
DetectSt->IdleSt	186	Covered	T84,T102,T106
DetectSt->StableSt	191	Covered	T6,T18,T46
IdleSt->DebounceSt	148	Covered	T6,T18,T25
StableSt->IdleSt	206	Covered	T6,T18,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T18,T25
0	1	Covered	T6,T18,T25
0	0	Excluded	T1,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T18,T46
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T18,T25
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T18,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T18,T25,T38
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T18,T25
DetectSt	-	-	-	-	1	-	-	Covered	T84,T102,T106
DetectSt	-	-	-	-	0	1	-	Covered	T6,T18,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T18,T46
StableSt	-	-	-	-	-	-	0	Covered	T6,T18,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7060683	207	0	0
CntIncr_A	7060683	303992	0	0
CntNoWrap_A	7060683	6422030	0	0
DetectStDropOut_A	7060683	3	0	0
DetectedOut_A	7060683	631	0	0
DetectedPulseOut_A	7060683	92	0	0
DisabledIdleSt_A	7060683	6113465	0	0
DisabledNoDetection_A	7060683	6115775	0	0
EnterDebounceSt_A	7060683	117	0	0
EnterDetectSt_A	7060683	95	0	0
EnterStableSt_A	7060683	92	0	0
PulseIsPulse_A	7060683	92	0	0
StayInStableSt	7060683	539	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7060683	7024	0	0
gen_low_level_sva.LowLevelEvent_A	7060683	6424588	0	0
gen_not_sticky_sva.StableStDropOut_A	7060683	92	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	207	0	0
T2	654	0	0	0
T6	36894	2	0	0
T7	496	0	0	0
T12	0	2	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	5	0	0
T25	0	1	0	0
T27	5561	0	0	0
T31	0	2	0	0
T38	0	3	0	0
T46	0	4	0	0
T48	0	6	0	0
T95	0	2	0	0
T96	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	303992	0	0
T2	654	0	0	0
T6	36894	82	0	0
T7	496	0	0	0
T12	0	53	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	54630	0	0
T25	0	49	0	0
T27	5561	0	0	0
T31	0	55	0	0
T38	0	86	0	0
T46	0	130	0	0
T48	0	173	0	0
T95	0	95	0	0
T96	0	16	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6422030	0	0
T1	13064	12657	0	0
T2	654	253	0	0
T6	36894	35289	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54738	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	3	0	0
T84	688	1	0	0
T102	0	1	0	0
T106	0	1	0	0
T113	502	0	0	0
T114	1837	0	0	0
T115	1154	0	0	0
T116	423	0	0	0
T117	37076	0	0	0
T118	8700	0	0	0
T119	522	0	0	0
T120	18319	0	0	0
T121	6165	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	631	0	0
T2	654	0	0	0
T6	36894	3	0	0
T7	496	0	0	0
T12	0	10	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	16	0	0
T27	5561	0	0	0
T31	0	2	0	0
T38	0	5	0	0
T46	0	7	0	0
T48	0	22	0	0
T95	0	9	0	0
T96	0	1	0	0
T123	0	5	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	92	0	0
T2	654	0	0	0
T6	36894	1	0	0
T7	496	0	0	0
T12	0	1	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	2	0	0
T27	5561	0	0	0
T31	0	1	0	0
T38	0	1	0	0
T46	0	2	0	0
T48	0	3	0	0
T95	0	1	0	0
T96	0	1	0	0
T123	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6113465	0	0
T1	13064	12657	0	0
T2	654	253	0	0
T6	36894	35163	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6115775	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35166	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	117	0	0
T2	654	0	0	0
T6	36894	1	0	0
T7	496	0	0	0
T12	0	1	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	3	0	0
T25	0	1	0	0
T27	5561	0	0	0
T31	0	1	0	0
T38	0	2	0	0
T46	0	2	0	0
T48	0	3	0	0
T95	0	1	0	0
T96	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	95	0	0
T2	654	0	0	0
T6	36894	1	0	0
T7	496	0	0	0
T12	0	1	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	2	0	0
T27	5561	0	0	0
T31	0	1	0	0
T38	0	1	0	0
T46	0	2	0	0
T48	0	3	0	0
T95	0	1	0	0
T96	0	1	0	0
T123	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	92	0	0
T2	654	0	0	0
T6	36894	1	0	0
T7	496	0	0	0
T12	0	1	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	2	0	0
T27	5561	0	0	0
T31	0	1	0	0
T38	0	1	0	0
T46	0	2	0	0
T48	0	3	0	0
T95	0	1	0	0
T96	0	1	0	0
T123	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	92	0	0
T2	654	0	0	0
T6	36894	1	0	0
T7	496	0	0	0
T12	0	1	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	2	0	0
T27	5561	0	0	0
T31	0	1	0	0
T38	0	1	0	0
T46	0	2	0	0
T48	0	3	0	0
T95	0	1	0	0
T96	0	1	0	0
T123	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	539	0	0
T2	654	0	0	0
T6	36894	2	0	0
T7	496	0	0	0
T12	0	9	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	14	0	0
T27	5561	0	0	0
T31	0	1	0	0
T38	0	4	0	0
T46	0	5	0	0
T48	0	19	0	0
T95	0	8	0	0
T123	0	3	0	0
T125	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	7024	0	0
T1	13064	25	0	0
T2	654	0	0	0
T6	36894	10	0	0
T7	496	10	0	0
T13	503	7	0	0
T14	5222	24	0	0
T15	419	2	0	0
T16	490	8	0	0
T17	505	4	0	0
T18	55144	3	0	0
T27	0	12	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	92	0	0
T2	654	0	0	0
T6	36894	1	0	0
T7	496	0	0	0
T12	0	1	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	2	0	0
T27	5561	0	0	0
T31	0	1	0	0
T38	0	1	0	0
T46	0	2	0	0
T48	0	3	0	0
T95	0	1	0	0
T96	0	1	0	0
T123	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T9,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T6,T7	VC_COV_UNR
1	Covered	T9,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T9,T23,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T22,T23
1	0	Covered	T1,T6,T7
1	1	Covered	T9,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T23,T56
0	1	Covered	T23,T91,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T23,T56
0	1	Unreachable
1	0	Covered	T9,T23,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T22,T23
DetectSt	168	Covered	T9,T23,T56
IdleSt	163	Covered	T1,T6,T7
StableSt	191	Covered	T9,T23,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T23,T56
DebounceSt->IdleSt	163	Covered	T22,T126,T91
DetectSt->IdleSt	186	Covered	T23,T91,T92
DetectSt->StableSt	191	Covered	T9,T23,T56
IdleSt->DebounceSt	148	Covered	T9,T22,T23
StableSt->IdleSt	206	Covered	T9,T23,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T22,T23
0	1	Covered	T9,T22,T23
0	0	Excluded	T1,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T23,T56
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T23,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T126,T91
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T23,T91,T92
DetectSt	-	-	-	-	0	1	-	Covered	T9,T23,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T23,T56
StableSt	-	-	-	-	-	-	0	Covered	T9,T23,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7060683	216	0	0
CntIncr_A	7060683	63554	0	0
CntNoWrap_A	7060683	6422021	0	0
DetectStDropOut_A	7060683	23	0	0
DetectedOut_A	7060683	161239	0	0
DetectedPulseOut_A	7060683	56	0	0
DisabledIdleSt_A	7060683	4946252	0	0
DisabledNoDetection_A	7060683	4948602	0	0
EnterDebounceSt_A	7060683	138	0	0
EnterDetectSt_A	7060683	79	0	0
EnterStableSt_A	7060683	56	0	0
PulseIsPulse_A	7060683	56	0	0
StayInStableSt	7060683	161183	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7060683	7024	0	0
gen_low_level_sva.LowLevelEvent_A	7060683	6424588	0	0
gen_sticky_sva.StableStDropOut_A	7060683	599577	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	216	0	0
T9	1381	2	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T22	0	1	0	0
T23	0	10	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	4	0	0
T61	0	2	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	420	0	0	0
T77	449	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	63554	0	0
T9	1381	99	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T22	0	43	0	0
T23	0	130	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	66	0	0
T61	0	96	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	43	0	0
T72	0	72	0	0
T73	0	40	0	0
T74	0	65	0	0
T75	0	51	0	0
T76	420	0	0	0
T77	449	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6422021	0	0
T1	13064	12657	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	23	0	0
T23	1021	4	0	0
T31	2019	0	0	0
T34	28277	0	0	0
T36	875	0	0	0
T48	713	0	0	0
T49	6372	0	0	0
T67	506	0	0	0
T91	0	4	0	0
T92	0	1	0	0
T93	17430	0	0	0
T129	954	0	0	0
T130	0	7	0	0
T131	0	4	0	0
T132	0	1	0	0
T133	0	2	0	0
T134	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	161239	0	0
T9	1381	202	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T23	0	1	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	423	0	0
T61	0	13	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	3	0	0
T72	0	228	0	0
T73	0	273	0	0
T74	0	298	0	0
T75	0	220	0	0
T76	420	0	0	0
T77	449	0	0	0
T91	0	151	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	56	0	0
T9	1381	1	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T23	0	1	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	2	0	0
T61	0	1	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	420	0	0	0
T77	449	0	0	0
T91	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	4946252	0	0
T1	13064	12657	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	4948602	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	138	0	0
T9	1381	1	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T22	0	1	0	0
T23	0	5	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	2	0	0
T61	0	1	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	420	0	0	0
T77	449	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	79	0	0
T9	1381	1	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T23	0	5	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	2	0	0
T61	0	1	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	420	0	0	0
T77	449	0	0	0
T91	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	56	0	0
T9	1381	1	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T23	0	1	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	2	0	0
T61	0	1	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	420	0	0	0
T77	449	0	0	0
T91	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	56	0	0
T9	1381	1	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T23	0	1	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	2	0	0
T61	0	1	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	420	0	0	0
T77	449	0	0	0
T91	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	161183	0	0
T9	1381	201	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	421	0	0
T61	0	12	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	2	0	0
T72	0	227	0	0
T73	0	272	0	0
T74	0	297	0	0
T75	0	219	0	0
T76	420	0	0	0
T77	449	0	0	0
T91	0	149	0	0
T127	0	214	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	7024	0	0
T1	13064	25	0	0
T2	654	0	0	0
T6	36894	10	0	0
T7	496	10	0	0
T13	503	7	0	0
T14	5222	24	0	0
T15	419	2	0	0
T16	490	8	0	0
T17	505	4	0	0
T18	55144	3	0	0
T27	0	12	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	599577	0	0
T9	1381	75	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T23	0	49	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	800	0	0
T61	0	29	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	140	0	0
T72	0	280	0	0
T73	0	103784	0	0
T74	0	106	0	0
T75	0	95	0	0
T76	420	0	0	0
T77	449	0	0	0
T91	0	569	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T6,T7,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T6,T7,T13
1	1	Covered	T6,T7,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T9,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T6,T7	VC_COV_UNR
1	Covered	T9,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T22,T23,T61

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T22,T23
1	0	Covered	T6,T7,T13
1	1	Covered	T9,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T61
0	1	Covered	T74,T89,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T61
0	1	Unreachable
1	0	Covered	T22,T23,T61

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T22,T23
DetectSt	168	Covered	T22,T23,T61
IdleSt	163	Covered	T1,T6,T7
StableSt	191	Covered	T22,T23,T61

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T23,T61
DebounceSt->IdleSt	163	Covered	T9,T56,T74
DetectSt->IdleSt	186	Covered	T74,T89,T90
DetectSt->StableSt	191	Covered	T22,T23,T61
IdleSt->DebounceSt	148	Covered	T9,T22,T23
StableSt->IdleSt	206	Covered	T22,T23,T61

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T22,T23
0	1	Covered	T9,T22,T23
0	0	Excluded	T1,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T61
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T23,T61
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T56,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T74,T89,T90
DetectSt	-	-	-	-	0	1	-	Covered	T22,T23,T61
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T23,T61
StableSt	-	-	-	-	-	-	0	Covered	T22,T23,T61
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7060683	189	0	0
CntIncr_A	7060683	208914	0	0
CntNoWrap_A	7060683	6422048	0	0
DetectStDropOut_A	7060683	6	0	0
DetectedOut_A	7060683	91284	0	0
DetectedPulseOut_A	7060683	58	0	0
DisabledIdleSt_A	7060683	4946252	0	0
DisabledNoDetection_A	7060683	4948602	0	0
EnterDebounceSt_A	7060683	126	0	0
EnterDetectSt_A	7060683	64	0	0
EnterStableSt_A	7060683	58	0	0
PulseIsPulse_A	7060683	58	0	0
StayInStableSt	7060683	91226	0	0
gen_high_level_sva.HighLevelEvent_A	7060683	6424588	0	0
gen_sticky_sva.StableStDropOut_A	7060683	879810	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	189	0	0
T9	1381	2	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T22	0	2	0	0
T23	0	2	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	10	0	0
T61	0	2	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	6	0	0
T75	0	2	0	0
T76	420	0	0	0
T77	449	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	208914	0	0
T9	1381	64	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T22	0	27	0	0
T23	0	33	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	640	0	0
T61	0	83	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	86	0	0
T72	0	11	0	0
T73	0	20798	0	0
T74	0	100	0	0
T75	0	15	0	0
T76	420	0	0	0
T77	449	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6422048	0	0
T1	13064	12657	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6	0	0
T74	1361	2	0	0
T75	1177	0	0	0
T82	73132	0	0	0
T89	0	1	0	0
T90	0	3	0	0
T135	5453	0	0	0
T136	640	0	0	0
T137	424	0	0	0
T138	434	0	0	0
T139	404	0	0	0
T140	445	0	0	0
T141	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	91284	0	0
T22	1314	22	0	0
T23	1021	208	0	0
T31	2019	0	0	0
T34	28277	0	0	0
T36	875	0	0	0
T48	713	0	0	0
T58	15638	0	0	0
T61	0	1	0	0
T67	506	0	0	0
T71	0	74	0	0
T72	0	58	0	0
T73	0	83197	0	0
T75	0	135	0	0
T91	0	360	0	0
T93	17430	0	0	0
T126	0	93	0	0
T127	0	83	0	0
T129	954	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	58	0	0
T22	1314	1	0	0
T23	1021	1	0	0
T31	2019	0	0	0
T34	28277	0	0	0
T36	875	0	0	0
T48	713	0	0	0
T58	15638	0	0	0
T61	0	1	0	0
T67	506	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T91	0	3	0	0
T93	17430	0	0	0
T126	0	1	0	0
T127	0	1	0	0
T129	954	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	4946252	0	0
T1	13064	12657	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	4948602	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	126	0	0
T9	1381	2	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	10	0	0
T61	0	1	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	4	0	0
T75	0	1	0	0
T76	420	0	0	0
T77	449	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	64	0	0
T22	1314	1	0	0
T23	1021	1	0	0
T31	2019	0	0	0
T34	28277	0	0	0
T36	875	0	0	0
T48	713	0	0	0
T58	15638	0	0	0
T61	0	1	0	0
T67	506	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T91	0	3	0	0
T93	17430	0	0	0
T126	0	1	0	0
T129	954	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	58	0	0
T22	1314	1	0	0
T23	1021	1	0	0
T31	2019	0	0	0
T34	28277	0	0	0
T36	875	0	0	0
T48	713	0	0	0
T58	15638	0	0	0
T61	0	1	0	0
T67	506	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T91	0	3	0	0
T93	17430	0	0	0
T126	0	1	0	0
T127	0	1	0	0
T129	954	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	58	0	0
T22	1314	1	0	0
T23	1021	1	0	0
T31	2019	0	0	0
T34	28277	0	0	0
T36	875	0	0	0
T48	713	0	0	0
T58	15638	0	0	0
T61	0	1	0	0
T67	506	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T91	0	3	0	0
T93	17430	0	0	0
T126	0	1	0	0
T127	0	1	0	0
T129	954	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	91226	0	0
T22	1314	21	0	0
T23	1021	207	0	0
T31	2019	0	0	0
T34	28277	0	0	0
T36	875	0	0	0
T48	713	0	0	0
T58	15638	0	0	0
T67	506	0	0	0
T71	0	73	0	0
T72	0	57	0	0
T73	0	83196	0	0
T75	0	134	0	0
T91	0	357	0	0
T93	17430	0	0	0
T126	0	92	0	0
T127	0	82	0	0
T128	0	39	0	0
T129	954	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	879810	0	0
T22	1314	74	0	0
T23	1021	115	0	0
T31	2019	0	0	0
T34	28277	0	0	0
T36	875	0	0	0
T48	713	0	0	0
T58	15638	0	0	0
T61	0	52	0	0
T67	506	0	0	0
T71	0	25	0	0
T72	0	507	0	0
T73	0	101	0	0
T75	0	213	0	0
T91	0	1029	0	0
T93	17430	0	0	0
T126	0	31	0	0
T127	0	263	0	0
T129	954	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T9,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T6,T7	VC_COV_UNR
1	Covered	T9,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T22,T23,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T22,T23
1	0	Covered	T1,T6,T7
1	1	Covered	T9,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T56
0	1	Covered	T73,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T56
0	1	Unreachable
1	0	Covered	T22,T23,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T22,T23
DetectSt	168	Covered	T22,T23,T56
IdleSt	163	Covered	T1,T6,T7
StableSt	191	Covered	T22,T23,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T23,T56
DebounceSt->IdleSt	163	Covered	T9,T71,T73
DetectSt->IdleSt	186	Covered	T73,T87,T88
DetectSt->StableSt	191	Covered	T22,T23,T56
IdleSt->DebounceSt	148	Covered	T9,T22,T23
StableSt->IdleSt	206	Covered	T22,T23,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T22,T23
0	1	Covered	T9,T22,T23
0	0	Excluded	T1,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T56
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T23,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T71,T73
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T73,T87,T88
DetectSt	-	-	-	-	0	1	-	Covered	T22,T23,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T23,T56
StableSt	-	-	-	-	-	-	0	Covered	T22,T23,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7060683	205	0	0
CntIncr_A	7060683	217917	0	0
CntNoWrap_A	7060683	6422032	0	0
DetectStDropOut_A	7060683	19	0	0
DetectedOut_A	7060683	747433	0	0
DetectedPulseOut_A	7060683	56	0	0
DisabledIdleSt_A	7060683	4946252	0	0
DisabledNoDetection_A	7060683	4948602	0	0
EnterDebounceSt_A	7060683	131	0	0
EnterDetectSt_A	7060683	75	0	0
EnterStableSt_A	7060683	56	0	0
PulseIsPulse_A	7060683	56	0	0
StayInStableSt	7060683	747377	0	0
gen_high_event_sva.HighLevelEvent_A	7060683	6424588	0	0
gen_high_level_sva.HighLevelEvent_A	7060683	6424588	0	0
gen_sticky_sva.StableStDropOut_A	7060683	225838	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	205	0	0
T9	1381	2	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T22	0	2	0	0
T23	0	2	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	4	0	0
T61	0	2	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	8	0	0
T74	0	4	0	0
T75	0	2	0	0
T76	420	0	0	0
T77	449	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	217917	0	0
T9	1381	36	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T22	0	95	0	0
T23	0	30	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	34	0	0
T61	0	12	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	14	0	0
T72	0	69	0	0
T73	0	400	0	0
T74	0	48	0	0
T75	0	14	0	0
T76	420	0	0	0
T77	449	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6422032	0	0
T1	13064	12657	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	19	0	0
T37	4359	0	0	0
T73	104533	3	0	0
T87	0	2	0	0
T88	0	1	0	0
T98	17296	0	0	0
T99	8524	0	0	0
T142	0	5	0	0
T143	0	2	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	402	0	0	0
T148	499	0	0	0
T149	765	0	0	0
T150	402	0	0	0
T151	2392	0	0	0
T152	495	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	747433	0	0
T22	1314	9	0	0
T23	1021	148	0	0
T31	2019	0	0	0
T34	28277	0	0	0
T36	875	0	0	0
T48	713	0	0	0
T56	0	283	0	0
T58	15638	0	0	0
T61	0	9	0	0
T67	506	0	0	0
T72	0	466	0	0
T75	0	109	0	0
T91	0	1027	0	0
T92	0	195	0	0
T93	17430	0	0	0
T127	0	405	0	0
T128	0	113	0	0
T129	954	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	56	0	0
T22	1314	1	0	0
T23	1021	1	0	0
T31	2019	0	0	0
T34	28277	0	0	0
T36	875	0	0	0
T48	713	0	0	0
T56	0	2	0	0
T58	15638	0	0	0
T61	0	1	0	0
T67	506	0	0	0
T72	0	1	0	0
T75	0	1	0	0
T91	0	3	0	0
T92	0	1	0	0
T93	17430	0	0	0
T127	0	1	0	0
T128	0	2	0	0
T129	954	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	4946252	0	0
T1	13064	12657	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	4948602	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	131	0	0
T9	1381	2	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	2	0	0
T61	0	1	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	5	0	0
T74	0	4	0	0
T75	0	1	0	0
T76	420	0	0	0
T77	449	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	75	0	0
T22	1314	1	0	0
T23	1021	1	0	0
T31	2019	0	0	0
T34	28277	0	0	0
T36	875	0	0	0
T48	713	0	0	0
T56	0	2	0	0
T58	15638	0	0	0
T61	0	1	0	0
T67	506	0	0	0
T72	0	1	0	0
T73	0	3	0	0
T75	0	1	0	0
T91	0	3	0	0
T92	0	1	0	0
T93	17430	0	0	0
T127	0	1	0	0
T129	954	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	56	0	0
T22	1314	1	0	0
T23	1021	1	0	0
T31	2019	0	0	0
T34	28277	0	0	0
T36	875	0	0	0
T48	713	0	0	0
T56	0	2	0	0
T58	15638	0	0	0
T61	0	1	0	0
T67	506	0	0	0
T72	0	1	0	0
T75	0	1	0	0
T91	0	3	0	0
T92	0	1	0	0
T93	17430	0	0	0
T127	0	1	0	0
T128	0	2	0	0
T129	954	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	56	0	0
T22	1314	1	0	0
T23	1021	1	0	0
T31	2019	0	0	0
T34	28277	0	0	0
T36	875	0	0	0
T48	713	0	0	0
T56	0	2	0	0
T58	15638	0	0	0
T61	0	1	0	0
T67	506	0	0	0
T72	0	1	0	0
T75	0	1	0	0
T91	0	3	0	0
T92	0	1	0	0
T93	17430	0	0	0
T127	0	1	0	0
T128	0	2	0	0
T129	954	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	747377	0	0
T22	1314	8	0	0
T23	1021	147	0	0
T31	2019	0	0	0
T34	28277	0	0	0
T36	875	0	0	0
T48	713	0	0	0
T56	0	281	0	0
T58	15638	0	0	0
T61	0	8	0	0
T67	506	0	0	0
T72	0	465	0	0
T75	0	108	0	0
T91	0	1024	0	0
T92	0	194	0	0
T93	17430	0	0	0
T127	0	404	0	0
T128	0	111	0	0
T129	954	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	225838	0	0
T22	1314	37	0	0
T23	1021	197	0	0
T31	2019	0	0	0
T34	28277	0	0	0
T36	875	0	0	0
T48	713	0	0	0
T56	0	998	0	0
T58	15638	0	0	0
T61	0	135	0	0
T67	506	0	0	0
T72	0	49	0	0
T75	0	245	0	0
T91	0	153	0	0
T92	0	111537	0	0
T93	17430	0	0	0
T127	0	50	0	0
T128	0	58	0	0
T129	954	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T4,T44,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T6,T7	VC_COV_UNR
1	Covered	T4,T44,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T4,T44,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T4
1	0	Covered	T1,T6,T7
1	1	Covered	T4,T44,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T44,T40
0	1	Covered	T153,T154
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T44,T40
0	1	Covered	T4,T39,T43
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T44,T40
1	-	Covered	T4,T39,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T44,T40
DetectSt	168	Covered	T4,T44,T40
IdleSt	163	Covered	T1,T6,T7
StableSt	191	Covered	T4,T44,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T44,T40
DebounceSt->IdleSt	163	Covered	T79,T80,T118
DetectSt->IdleSt	186	Covered	T153,T154
DetectSt->StableSt	191	Covered	T4,T44,T40
IdleSt->DebounceSt	148	Covered	T4,T44,T40
StableSt->IdleSt	206	Covered	T4,T40,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T44,T40
0	1	Covered	T4,T44,T40
0	0	Excluded	T1,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T44,T40
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T44,T40
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T44,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T118
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T44,T40
DetectSt	-	-	-	-	1	-	-	Covered	T153,T154
DetectSt	-	-	-	-	0	1	-	Covered	T4,T44,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T39,T43
StableSt	-	-	-	-	-	-	0	Covered	T4,T44,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7060683	81	0	0
CntIncr_A	7060683	54129	0	0
CntNoWrap_A	7060683	6422156	0	0
DetectStDropOut_A	7060683	2	0	0
DetectedOut_A	7060683	89058	0	0
DetectedPulseOut_A	7060683	37	0	0
DisabledIdleSt_A	7060683	6123115	0	0
DisabledNoDetection_A	7060683	6125413	0	0
EnterDebounceSt_A	7060683	42	0	0
EnterDetectSt_A	7060683	39	0	0
EnterStableSt_A	7060683	37	0	0
PulseIsPulse_A	7060683	37	0	0
StayInStableSt	7060683	89000	0	0
gen_high_level_sva.HighLevelEvent_A	7060683	6424588	0	0
gen_not_sticky_sva.StableStDropOut_A	7060683	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	81	0	0
T4	46053	4	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	0	0	0
T11	535	0	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	6	0	0
T44	0	2	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T76	420	0	0	0
T124	422	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	54129	0	0
T4	46053	18818	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	0	0	0
T11	535	0	0	0
T37	0	36	0	0
T39	0	93	0	0
T40	0	91	0	0
T42	0	28	0	0
T43	0	153	0	0
T44	0	60	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T76	420	0	0	0
T124	422	0	0	0
T155	0	20	0	0
T156	0	10	0	0
T157	0	89	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6422156	0	0
T1	13064	12657	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	2	0	0
T107	11012	0	0	0
T153	969	1	0	0
T154	0	1	0	0
T158	9624	0	0	0
T159	183029	0	0	0
T160	522	0	0	0
T161	3553	0	0	0
T162	423	0	0	0
T163	4190	0	0	0
T164	25955	0	0	0
T165	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	89058	0	0
T4	46053	84	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	0	0	0
T11	535	0	0	0
T37	0	36	0	0
T39	0	1	0	0
T40	0	40	0	0
T42	0	217	0	0
T43	0	124	0	0
T44	0	38	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T76	420	0	0	0
T124	422	0	0	0
T155	0	60	0	0
T156	0	129	0	0
T157	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	37	0	0
T4	46053	2	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	0	0	0
T11	535	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T76	420	0	0	0
T124	422	0	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6123115	0	0
T1	13064	12657	0	0
T2	654	3	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6125413	0	0
T1	13064	12661	0	0
T2	654	3	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	42	0	0
T4	46053	2	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	0	0	0
T11	535	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T76	420	0	0	0
T124	422	0	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	39	0	0
T4	46053	2	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	0	0	0
T11	535	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T76	420	0	0	0
T124	422	0	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	37	0	0
T4	46053	2	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	0	0	0
T11	535	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T76	420	0	0	0
T124	422	0	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	37	0	0
T4	46053	2	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	0	0	0
T11	535	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T76	420	0	0	0
T124	422	0	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	89000	0	0
T4	46053	81	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	0	0	0
T11	535	0	0	0
T37	0	34	0	0
T40	0	38	0	0
T42	0	215	0	0
T43	0	120	0	0
T44	0	36	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T76	420	0	0	0
T124	422	0	0	0
T155	0	59	0	0
T156	0	127	0	0
T157	0	37	0	0
T166	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	16	0	0
T4	46053	1	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	0	0	0
T11	535	0	0	0
T39	0	1	0	0
T43	0	2	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T76	420	0	0	0
T118	0	1	0	0
T121	0	1	0	0
T124	422	0	0	0
T155	0	1	0	0
T166	0	1	0	0
T167	0	2	0	0
T168	0	1	0	0
T169	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T4,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T6,T7	VC_COV_UNR
1	Covered	T4,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T4,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T10,T11
1	0	Covered	T1,T6,T7
1	1	Covered	T4,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T10,T11
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T10,T11
0	1	Covered	T4,T68,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T10,T11
1	-	Covered	T4,T68,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T10,T11
DetectSt	168	Covered	T4,T10,T11
IdleSt	163	Covered	T1,T6,T7
StableSt	191	Covered	T4,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T10,T11
DebounceSt->IdleSt	163	Covered	T125,T79,T80
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4,T10,T11
IdleSt->DebounceSt	148	Covered	T4,T10,T11
StableSt->IdleSt	206	Covered	T4,T68,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T10,T11
0	1	Covered	T4,T10,T11
0	0	Excluded	T1,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T11
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T170,T171,T108
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T10,T11
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T4,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T68,T38
StableSt	-	-	-	-	-	-	0	Covered	T4,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7060683	99	0	0
CntIncr_A	7060683	21403	0	0
CntNoWrap_A	7060683	6422138	0	0
DetectStDropOut_A	7060683	0	0	0
DetectedOut_A	7060683	12107	0	0
DetectedPulseOut_A	7060683	46	0	0
DisabledIdleSt_A	7060683	6352673	0	0
DisabledNoDetection_A	7060683	6354975	0	0
EnterDebounceSt_A	7060683	54	0	0
EnterDetectSt_A	7060683	46	0	0
EnterStableSt_A	7060683	46	0	0
PulseIsPulse_A	7060683	46	0	0
StayInStableSt	7060683	12043	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7060683	2703	0	0
gen_low_level_sva.LowLevelEvent_A	7060683	6424588	0	0
gen_not_sticky_sva.StableStDropOut_A	7060683	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	99	0	0
T4	46053	4	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	2	0	0
T11	535	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T68	0	2	0	0
T76	420	0	0	0
T124	422	0	0	0
T156	0	2	0	0
T157	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	21403	0	0
T4	46053	18818	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	82	0	0
T11	535	39	0	0
T37	0	36	0	0
T38	0	160	0	0
T41	0	77	0	0
T42	0	28	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T68	0	88	0	0
T76	420	0	0	0
T124	422	0	0	0
T125	0	73	0	0
T156	0	10	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6422138	0	0
T1	13064	12657	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	12107	0	0
T4	46053	7920	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	136	0	0
T11	535	39	0	0
T37	0	17	0	0
T38	0	94	0	0
T41	0	261	0	0
T42	0	40	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T68	0	9	0	0
T76	420	0	0	0
T124	422	0	0	0
T156	0	61	0	0
T157	0	147	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	46	0	0
T4	46053	2	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	1	0	0
T11	535	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T68	0	1	0	0
T76	420	0	0	0
T124	422	0	0	0
T156	0	1	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6352673	0	0
T1	13064	12657	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6354975	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	54	0	0
T4	46053	2	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	1	0	0
T11	535	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T68	0	1	0	0
T76	420	0	0	0
T124	422	0	0	0
T125	0	1	0	0
T156	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	46	0	0
T4	46053	2	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	1	0	0
T11	535	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T68	0	1	0	0
T76	420	0	0	0
T124	422	0	0	0
T156	0	1	0	0
T157	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	46	0	0
T4	46053	2	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	1	0	0
T11	535	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T68	0	1	0	0
T76	420	0	0	0
T124	422	0	0	0
T156	0	1	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	46	0	0
T4	46053	2	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	1	0	0
T11	535	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T68	0	1	0	0
T76	420	0	0	0
T124	422	0	0	0
T156	0	1	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	12043	0	0
T4	46053	7918	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	134	0	0
T11	535	37	0	0
T37	0	16	0	0
T38	0	91	0	0
T41	0	260	0	0
T42	0	39	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T68	0	8	0	0
T76	420	0	0	0
T124	422	0	0	0
T156	0	60	0	0
T157	0	146	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	2703	0	0
T2	654	1	0	0
T3	0	1	0	0
T6	36894	9	0	0
T7	496	5	0	0
T13	503	5	0	0
T14	5222	0	0	0
T15	419	2	0	0
T16	490	4	0	0
T17	505	5	0	0
T18	55144	0	0	0
T24	0	13	0	0
T27	5561	0	0	0
T53	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	28	0	0
T4	46053	2	0	0
T5	32397	0	0	0
T9	1381	0	0	0
T10	628	0	0	0
T11	535	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	5467	0	0	0
T62	493	0	0	0
T65	506	0	0	0
T68	0	1	0	0
T76	420	0	0	0
T124	422	0	0	0
T156	0	1	0	0
T157	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0