Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.09	100.00	95.01		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	89.26	93.48	85.71		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	90.69	95.65	85.71		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	90.69	95.65	85.71		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	96.66	97.83	90.48		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	96.66	97.83	90.48		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
90.69	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
90.69	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
96.66	97.83

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
96.66	97.83

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
89.26	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T27
1	Covered	T1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T27,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T27,T5

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T27,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T5
1	0	Covered	T1,T6,T14
1	1	Covered	T1,T27,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T27,T5
0	1	Covered	T47,T35,T78
1	0	Covered	T79,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T27,T5
0	1	Covered	T1,T27,T5
1	0	Covered	T81,T79,T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T27,T5
1	-	Covered	T1,T27,T5

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
90.69	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
90.69	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
96.66	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
96.66	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
89.26	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T6,T2,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T6,T2,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T6,T2,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T18
1	0	Covered	T1,T6,T7
1	1	Covered	T6,T2,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T2,T18
0	1	Covered	T82,T83,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T2,T18
0	1	Covered	T6,T18,T4
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T2,T18
1	-	Covered	T6,T18,T4

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T26
1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T14,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T14,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T14,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T5,T33
1	1	Covered	T1,T14,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T26
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T70,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T45
0	1	Covered	T1,T5,T45
1	0	Covered	T69,T86,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T45
1	-	Covered	T1,T5,T45

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T9,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T9,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T22,T23,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T22,T23
1	0	Covered	T1,T6,T7
1	1	Covered	T9,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T56
0	1	Covered	T73,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T56
0	1	Unreachable
1	0	Covered	T22,T23,T56

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T2,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T3,T4,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T2,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T6,T7
1	1	Covered	T3,T4,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T36,T39,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T4,T38,T41
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T4
1	-	Covered	T4,T38,T41

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T6,T7,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T6,T7,T13
1	1	Covered	T6,T7,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T9,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T9,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T22,T23,T61

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T22,T23
1	0	Covered	T6,T7,T13
1	1	Covered	T9,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T61
0	1	Covered	T74,T89,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T61
0	1	Unreachable
1	0	Covered	T22,T23,T61

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T9,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T9,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T9,T23,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T22,T23
1	0	Covered	T1,T6,T7
1	1	Covered	T9,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T23,T56
0	1	Covered	T23,T91,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T23,T56
0	1	Unreachable
1	0	Covered	T9,T23,T56

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T2,T18
DetectSt	168	Covered	T6,T2,T18
IdleSt	163	Covered	T1,T6,T7
StableSt	191	Covered	T6,T2,T18

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T2,T18
DebounceSt->IdleSt	163	Covered	T18,T3,T25
DetectSt->IdleSt	186	Covered	T23,T73,T74
DetectSt->StableSt	191	Covered	T6,T2,T18
IdleSt->DebounceSt	148	Covered	T6,T2,T18
StableSt->IdleSt	206	Covered	T6,T18,T4

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
90.69	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
90.69	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
96.66	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
96.66	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.26	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T2,T18
0	1	Covered	T6,T2,T18
0	0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T2,T18
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T2,T18
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T2,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T18,T3,T25
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T2,T18
DetectSt	-	-	-	-	1	-	-	Covered	T23,T74,T82
DetectSt	-	-	-	-	0	1	-	Covered	T6,T2,T18
DetectSt	-	-	-	-	0	0	-	Covered	T1,T27,T5
StableSt	-	-	-	-	-	-	1	Covered	T6,T18,T4
StableSt	-	-	-	-	-	-	0	Covered	T6,T2,T18
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T14,T26
0	1	Covered	T1,T14,T26
0	0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T26
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T26
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T71,T73
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T26
DetectSt	-	-	-	-	1	-	-	Covered	T1,T14,T26
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T33
DetectSt	-	-	-	-	0	0	-	Covered	T1,T14,T26
StableSt	-	-	-	-	-	-	1	Covered	T1,T5,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T33
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	183577758	17771	0	0
CntIncr_A	183577758	2128457	0	0
CntNoWrap_A	183577758	166960391	0	0
DetectStDropOut_A	183577758	1901	0	0
DetectedOut_A	183577758	2065885	0	0
DetectedPulseOut_A	183577758	5770	0	0
DisabledIdleSt_A	183577758	155471623	0	0
DisabledNoDetection_A	183577758	155528342	0	0
EnterDebounceSt_A	183577758	9215	0	0
EnterDetectSt_A	183577758	8578	0	0
EnterStableSt_A	183577758	5770	0	0
PulseIsPulse_A	183577758	5770	0	0
StayInStableSt	183577758	2059316	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	63546147	52605	0	0
gen_high_event_sva.HighLevelEvent_A	35303415	32122940	0	0
gen_high_level_sva.HighLevelEvent_A	120031611	109217996	0	0
gen_low_level_sva.LowLevelEvent_A	63546147	57821292	0	0
gen_not_sticky_sva.StableStDropOut_A	162395709	4754	0	0
gen_sticky_sva.StableStDropOut_A	21182049	1705225	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183577758	17771	0	0
T1	91448	28	0	0
T2	5232	0	0	0
T3	642	0	0	0
T4	46053	0	0	0
T5	0	34	0	0
T6	295152	2	0	0
T7	3968	0	0	0
T8	604	0	0	0
T12	0	10	0	0
T13	4024	0	0	0
T14	41776	52	0	0
T15	3352	0	0	0
T16	3920	0	0	0
T17	4040	0	0	0
T18	441152	5	0	0
T24	1823	0	0	0
T25	693	1	0	0
T26	4565	60	0	0
T27	11122	6	0	0
T30	1149	0	0	0
T31	0	4	0	0
T32	0	52	0	0
T34	0	2	0	0
T35	0	12	0	0
T38	0	3	0	0
T46	0	4	0	0
T48	0	6	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T78	0	18	0	0
T93	0	6	0	0
T94	0	6	0	0
T95	0	2	0	0
T96	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183577758	2128457	0	0
T1	91448	754	0	0
T2	5232	0	0	0
T3	642	0	0	0
T4	46053	0	0	0
T5	0	1138	0	0
T6	295152	82	0	0
T7	3968	0	0	0
T8	604	0	0	0
T12	0	373	0	0
T13	4024	0	0	0
T14	41776	1351	0	0
T15	3352	0	0	0
T16	3920	0	0	0
T17	4040	0	0	0
T18	441152	54630	0	0
T24	1823	0	0	0
T25	693	49	0	0
T26	4565	1163	0	0
T27	11122	291	0	0
T30	1149	0	0	0
T31	0	80	0	0
T32	0	1114	0	0
T34	0	236	0	0
T35	0	602	0	0
T38	0	86	0	0
T46	0	130	0	0
T48	0	173	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T78	0	1206	0	0
T93	0	333	0	0
T94	0	417	0	0
T95	0	95	0	0
T96	0	16	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183577758	166960391	0	0
T1	339664	328976	0	0
T2	17004	6572	0	0
T6	959244	917564	0	0
T7	12896	2470	0	0
T13	13078	2652	0	0
T14	135772	125242	0	0
T15	10894	468	0	0
T16	12740	2314	0	0
T17	13130	2704	0	0
T18	1433744	1423313	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183577758	1901	0	0
T1	13064	7	0	0
T14	0	26	0	0
T26	0	30	0	0
T32	9888	0	0	0
T35	9224	6	0	0
T45	0	26	0	0
T49	0	24	0	0
T68	648	0	0	0
T69	35631	0	0	0
T78	24663	0	0	0
T79	0	1	0	0
T84	688	1	0	0
T85	0	6	0	0
T94	19311	0	0	0
T97	0	29	0	0
T98	0	11	0	0
T99	0	5	0	0
T100	0	2	0	0
T101	0	3	0	0
T102	0	1	0	0
T103	0	2	0	0
T104	0	2	0	0
T105	0	5	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	10	0	0
T109	464	0	0	0
T110	525	0	0	0
T111	502	0	0	0
T112	15187	0	0	0
T113	502	0	0	0
T114	1837	0	0	0
T115	1154	0	0	0
T116	423	0	0	0
T117	37076	0	0	0
T118	8700	0	0	0
T119	522	0	0	0
T120	18319	0	0	0
T121	6165	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183577758	2065885	0	0
T2	654	0	0	0
T3	642	0	0	0
T5	32397	1144	0	0
T6	36894	3	0	0
T7	496	0	0	0
T8	604	0	0	0
T12	0	309	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	16	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T27	11122	68	0	0
T30	1149	0	0	0
T31	0	5	0	0
T32	0	2028	0	0
T33	0	235	0	0
T34	0	89	0	0
T38	0	5	0	0
T46	0	7	0	0
T48	0	22	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T69	0	4821	0	0
T78	0	102	0	0
T93	0	258	0	0
T94	0	265	0	0
T95	0	9	0	0
T96	0	1	0	0
T112	0	8	0	0
T122	0	150	0	0
T123	0	5	0	0
T124	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183577758	5770	0	0
T2	654	0	0	0
T3	642	0	0	0
T5	32397	17	0	0
T6	36894	1	0	0
T7	496	0	0	0
T8	604	0	0	0
T12	0	5	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	2	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T27	11122	3	0	0
T30	1149	0	0	0
T31	0	2	0	0
T32	0	26	0	0
T33	0	6	0	0
T34	0	1	0	0
T38	0	1	0	0
T46	0	2	0	0
T48	0	3	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T69	0	26	0	0
T78	0	9	0	0
T93	0	3	0	0
T94	0	3	0	0
T95	0	1	0	0
T96	0	1	0	0
T112	0	2	0	0
T122	0	4	0	0
T123	0	2	0	0
T124	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183577758	155471623	0	0
T1	339664	312183	0	0
T2	17004	4578	0	0
T6	959244	917438	0	0
T7	12896	2470	0	0
T13	13078	2652	0	0
T14	135772	114122	0	0
T15	10894	468	0	0
T16	12740	2314	0	0
T17	13130	2704	0	0
T18	1433744	1368578	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183577758	155528342	0	0
T1	339664	312273	0	0
T2	17004	4596	0	0
T6	959244	917516	0	0
T7	12896	2496	0	0
T13	13078	2678	0	0
T14	135772	114144	0	0
T15	10894	494	0	0
T16	12740	2340	0	0
T17	13130	2730	0	0
T18	1433744	1368603	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183577758	9215	0	0
T1	91448	14	0	0
T2	5232	0	0	0
T3	642	0	0	0
T4	46053	0	0	0
T5	0	17	0	0
T6	295152	1	0	0
T7	3968	0	0	0
T8	604	0	0	0
T12	0	5	0	0
T13	4024	0	0	0
T14	41776	26	0	0
T15	3352	0	0	0
T16	3920	0	0	0
T17	4040	0	0	0
T18	441152	3	0	0
T24	1823	0	0	0
T25	693	1	0	0
T26	4565	30	0	0
T27	11122	3	0	0
T30	1149	0	0	0
T31	0	2	0	0
T32	0	26	0	0
T34	0	1	0	0
T35	0	6	0	0
T38	0	2	0	0
T46	0	2	0	0
T48	0	3	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T78	0	9	0	0
T93	0	3	0	0
T94	0	3	0	0
T95	0	1	0	0
T96	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183577758	8578	0	0
T1	91448	14	0	0
T2	5232	0	0	0
T3	642	0	0	0
T4	46053	0	0	0
T5	0	17	0	0
T6	295152	1	0	0
T7	3968	0	0	0
T8	604	0	0	0
T12	0	5	0	0
T13	4024	0	0	0
T14	41776	26	0	0
T15	3352	0	0	0
T16	3920	0	0	0
T17	4040	0	0	0
T18	441152	2	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	30	0	0
T27	11122	3	0	0
T30	1149	0	0	0
T31	0	2	0	0
T32	0	26	0	0
T34	0	1	0	0
T35	0	6	0	0
T38	0	1	0	0
T46	0	2	0	0
T48	0	3	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T78	0	9	0	0
T93	0	3	0	0
T94	0	3	0	0
T95	0	1	0	0
T96	0	1	0	0
T123	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183577758	5770	0	0
T2	654	0	0	0
T3	642	0	0	0
T5	32397	17	0	0
T6	36894	1	0	0
T7	496	0	0	0
T8	604	0	0	0
T12	0	5	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	2	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T27	11122	3	0	0
T30	1149	0	0	0
T31	0	2	0	0
T32	0	26	0	0
T33	0	6	0	0
T34	0	1	0	0
T38	0	1	0	0
T46	0	2	0	0
T48	0	3	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T69	0	26	0	0
T78	0	9	0	0
T93	0	3	0	0
T94	0	3	0	0
T95	0	1	0	0
T96	0	1	0	0
T112	0	2	0	0
T122	0	4	0	0
T123	0	2	0	0
T124	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183577758	5770	0	0
T2	654	0	0	0
T3	642	0	0	0
T5	32397	17	0	0
T6	36894	1	0	0
T7	496	0	0	0
T8	604	0	0	0
T12	0	5	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	2	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T27	11122	3	0	0
T30	1149	0	0	0
T31	0	2	0	0
T32	0	26	0	0
T33	0	6	0	0
T34	0	1	0	0
T38	0	1	0	0
T46	0	2	0	0
T48	0	3	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T69	0	26	0	0
T78	0	9	0	0
T93	0	3	0	0
T94	0	3	0	0
T95	0	1	0	0
T96	0	1	0	0
T112	0	2	0	0
T122	0	4	0	0
T123	0	2	0	0
T124	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	183577758	2059316	0	0
T2	654	0	0	0
T3	642	0	0	0
T5	32397	1121	0	0
T6	36894	2	0	0
T7	496	0	0	0
T8	604	0	0	0
T12	0	304	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	14	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T27	11122	65	0	0
T30	1149	0	0	0
T31	0	3	0	0
T32	0	2001	0	0
T33	0	229	0	0
T34	0	88	0	0
T38	0	4	0	0
T46	0	5	0	0
T48	0	19	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T69	0	4791	0	0
T78	0	93	0	0
T93	0	255	0	0
T94	0	262	0	0
T95	0	8	0	0
T112	0	6	0	0
T122	0	145	0	0
T123	0	3	0	0
T124	422	0	0	0
T125	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63546147	52605	0	0
T1	91448	193	0	0
T2	5886	3	0	0
T3	0	3	0	0
T6	332046	77	0	0
T7	4464	72	0	0
T13	4527	47	0	0
T14	46998	163	0	0
T15	3771	15	0	0
T16	4410	64	0	0
T17	4545	42	0	0
T18	496296	9	0	0
T24	0	13	0	0
T27	11122	84	0	0
T30	0	4	0	0
T52	0	4	0	0
T53	0	14	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35303415	32122940	0	0
T1	65320	63305	0	0
T2	3270	1270	0	0
T6	184470	176470	0	0
T7	2480	480	0	0
T13	2515	515	0	0
T14	26110	24110	0	0
T15	2095	95	0	0
T16	2450	450	0	0
T17	2525	525	0	0
T18	275720	273720	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120031611	109217996	0	0
T1	222088	215237	0	0
T2	11118	4318	0	0
T6	627198	599998	0	0
T7	8432	1632	0	0
T13	8551	1751	0	0
T14	88774	81974	0	0
T15	7123	323	0	0
T16	8330	1530	0	0
T17	8585	1785	0	0
T18	937448	930648	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63546147	57821292	0	0
T1	117576	113949	0	0
T2	5886	2286	0	0
T6	332046	317646	0	0
T7	4464	864	0	0
T13	4527	927	0	0
T14	46998	43398	0	0
T15	3771	171	0	0
T16	4410	810	0	0
T17	4545	945	0	0
T18	496296	492696	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162395709	4754	0	0
T2	654	0	0	0
T3	642	0	0	0
T5	32397	11	0	0
T6	36894	1	0	0
T7	496	0	0	0
T8	604	0	0	0
T12	0	5	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	2	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T27	11122	3	0	0
T30	1149	0	0	0
T31	0	2	0	0
T32	0	25	0	0
T33	0	6	0	0
T34	0	1	0	0
T38	0	1	0	0
T46	0	2	0	0
T48	0	3	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T59	0	6	0	0
T69	0	22	0	0
T78	0	9	0	0
T93	0	3	0	0
T94	0	3	0	0
T95	0	1	0	0
T96	0	1	0	0
T112	0	2	0	0
T123	0	2	0	0
T124	422	0	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21182049	1705225	0	0
T9	1381	75	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T22	2628	111	0	0
T23	2042	361	0	0
T31	4038	0	0	0
T34	56554	0	0	0
T36	1750	0	0	0
T45	5467	0	0	0
T46	749	0	0	0
T48	1426	0	0	0
T56	0	1798	0	0
T58	31276	0	0	0
T61	0	216	0	0
T62	493	0	0	0
T66	502	0	0	0
T67	1012	0	0	0
T71	0	165	0	0
T72	0	836	0	0
T73	0	103885	0	0
T74	0	106	0	0
T75	0	553	0	0
T76	420	0	0	0
T77	449	0	0	0
T91	0	1751	0	0
T92	0	111537	0	0
T93	34860	0	0	0
T126	0	31	0	0
T127	0	313	0	0
T128	0	58	0	0
T129	1908	0	0	0