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Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.26 93.48 85.71 83.33 90.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.26 93.48 85.71 83.33 90.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T6,T7
10CoveredT1,T6,T7
11CoveredT1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT3,T38,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T6,T7 VC_COV_UNR
1CoveredT3,T58,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT3,T38,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT3,T58,T38
10CoveredT1,T6,T7
11CoveredT3,T58,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT3,T38,T40
01CoveredT172,T238
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT38,T40,T41
01CoveredT3,T38,T41
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT38,T40,T41
1-CoveredT3,T38,T41

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
DebounceSt 148 Covered T3,T58,T38
DetectSt 168 Covered T3,T38,T40
IdleSt 163 Covered T1,T6,T7
StableSt 191 Covered T3,T38,T40


transitions   Line No.   Covered   Tests   
DebounceSt->DetectSt 168 Covered T3,T38,T40
DebounceSt->IdleSt 163 Covered T58,T79,T237
DetectSt->IdleSt 186 Covered T172,T238
DetectSt->StableSt 191 Covered T3,T38,T40
IdleSt->DebounceSt 148 Covered T3,T58,T38
StableSt->IdleSt 206 Covered T3,T38,T40



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T3,T38,T40
0 1 Covered T3,T58,T38
0 0 Excluded T1,T6,T7 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T38,T40
0 Covered T1,T6,T7


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T3,T58,T38
IdleSt 0 - - - - - - Covered T1,T6,T7
DebounceSt - 1 - - - - - Covered T79,T80
DebounceSt - 0 1 1 - - - Covered T3,T38,T40
DebounceSt - 0 1 0 - - - Covered T237,T171
DebounceSt - 0 0 - - - - Covered T3,T58,T38
DetectSt - - - - 1 - - Covered T172,T238
DetectSt - - - - 0 1 - Covered T3,T38,T40
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T3,T38,T41
StableSt - - - - - - 0 Covered T38,T40,T41
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
CntClr_A 7060683 94 0 0
CntIncr_A 7060683 64467 0 0
CntNoWrap_A 7060683 6422143 0 0
DetectStDropOut_A 7060683 2 0 0
DetectedOut_A 7060683 57127 0 0
DetectedPulseOut_A 7060683 43 0 0
DisabledIdleSt_A 7060683 6122154 0 0
DisabledNoDetection_A 7060683 6124470 0 0
EnterDebounceSt_A 7060683 50 0 0
EnterDetectSt_A 7060683 45 0 0
EnterStableSt_A 7060683 43 0 0
PulseIsPulse_A 7060683 43 0 0
StayInStableSt 7060683 57064 0 0
gen_high_level_sva.HighLevelEvent_A 7060683 6424588 0 0
gen_not_sticky_sva.StableStDropOut_A 7060683 23 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 94 0 0
T3 642 2 0 0
T4 46053 0 0 0
T5 32397 0 0 0
T8 604 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T37 0 2 0 0
T38 0 6 0 0
T40 0 2 0 0
T41 0 2 0 0
T53 532 0 0 0
T54 522 0 0 0
T65 506 0 0 0
T92 0 2 0 0
T166 0 2 0 0
T167 0 4 0 0
T174 0 4 0 0
T194 0 4 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 64467 0 0
T3 642 95 0 0
T4 46053 0 0 0
T5 32397 0 0 0
T8 604 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T37 0 36 0 0
T38 0 240 0 0
T40 0 91 0 0
T41 0 77 0 0
T53 532 0 0 0
T54 522 0 0 0
T58 0 4951 0 0
T65 506 0 0 0
T92 0 23517 0 0
T166 0 95 0 0
T174 0 148 0 0
T194 0 144 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6422143 0 0
T1 13064 12657 0 0
T2 654 253 0 0
T6 36894 35291 0 0
T7 496 95 0 0
T13 503 102 0 0
T14 5222 4821 0 0
T15 419 18 0 0
T16 490 89 0 0
T17 505 104 0 0
T18 55144 54743 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 2 0 0
T172 38208 1 0 0
T238 0 1 0 0
T244 493 0 0 0
T245 504 0 0 0
T246 407 0 0 0
T247 17045 0 0 0
T248 516 0 0 0
T249 503 0 0 0
T250 425 0 0 0
T251 422 0 0 0
T252 504 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 57127 0 0
T3 642 1 0 0
T4 46053 0 0 0
T5 32397 0 0 0
T8 604 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T37 0 90 0 0
T38 0 247 0 0
T40 0 42 0 0
T41 0 393 0 0
T53 532 0 0 0
T54 522 0 0 0
T65 506 0 0 0
T92 0 41 0 0
T166 0 51 0 0
T167 0 95 0 0
T174 0 72 0 0
T194 0 166 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 43 0 0
T3 642 1 0 0
T4 46053 0 0 0
T5 32397 0 0 0
T8 604 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T37 0 1 0 0
T38 0 3 0 0
T40 0 1 0 0
T41 0 1 0 0
T53 532 0 0 0
T54 522 0 0 0
T65 506 0 0 0
T92 0 1 0 0
T166 0 1 0 0
T167 0 2 0 0
T174 0 2 0 0
T194 0 2 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6122154 0 0
T1 13064 12657 0 0
T2 654 253 0 0
T6 36894 35291 0 0
T7 496 95 0 0
T13 503 102 0 0
T14 5222 4821 0 0
T15 419 18 0 0
T16 490 89 0 0
T17 505 104 0 0
T18 55144 54743 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6124470 0 0
T1 13064 12661 0 0
T2 654 254 0 0
T6 36894 35294 0 0
T7 496 96 0 0
T13 503 103 0 0
T14 5222 4822 0 0
T15 419 19 0 0
T16 490 90 0 0
T17 505 105 0 0
T18 55144 54744 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 50 0 0
T3 642 1 0 0
T4 46053 0 0 0
T5 32397 0 0 0
T8 604 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T37 0 1 0 0
T38 0 3 0 0
T40 0 1 0 0
T41 0 1 0 0
T53 532 0 0 0
T54 522 0 0 0
T58 0 1 0 0
T65 506 0 0 0
T92 0 1 0 0
T166 0 1 0 0
T174 0 2 0 0
T194 0 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 45 0 0
T3 642 1 0 0
T4 46053 0 0 0
T5 32397 0 0 0
T8 604 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T37 0 1 0 0
T38 0 3 0 0
T40 0 1 0 0
T41 0 1 0 0
T53 532 0 0 0
T54 522 0 0 0
T65 506 0 0 0
T92 0 1 0 0
T166 0 1 0 0
T167 0 2 0 0
T174 0 2 0 0
T194 0 2 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 43 0 0
T3 642 1 0 0
T4 46053 0 0 0
T5 32397 0 0 0
T8 604 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T37 0 1 0 0
T38 0 3 0 0
T40 0 1 0 0
T41 0 1 0 0
T53 532 0 0 0
T54 522 0 0 0
T65 506 0 0 0
T92 0 1 0 0
T166 0 1 0 0
T167 0 2 0 0
T174 0 2 0 0
T194 0 2 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 43 0 0
T3 642 1 0 0
T4 46053 0 0 0
T5 32397 0 0 0
T8 604 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T37 0 1 0 0
T38 0 3 0 0
T40 0 1 0 0
T41 0 1 0 0
T53 532 0 0 0
T54 522 0 0 0
T65 506 0 0 0
T92 0 1 0 0
T166 0 1 0 0
T167 0 2 0 0
T174 0 2 0 0
T194 0 2 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 57064 0 0
T37 0 88 0 0
T38 7479 243 0 0
T40 0 40 0 0
T41 0 392 0 0
T61 728 0 0 0
T71 10496 0 0 0
T92 0 39 0 0
T166 0 49 0 0
T167 0 93 0 0
T172 0 5 0 0
T174 0 69 0 0
T186 530 0 0 0
T187 637 0 0 0
T188 405 0 0 0
T189 406 0 0 0
T190 445 0 0 0
T191 55684 0 0 0
T192 454 0 0 0
T194 0 163 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6424588 0 0
T1 13064 12661 0 0
T2 654 254 0 0
T6 36894 35294 0 0
T7 496 96 0 0
T13 503 103 0 0
T14 5222 4822 0 0
T15 419 19 0 0
T16 490 90 0 0
T17 505 105 0 0
T18 55144 54744 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 23 0 0
T3 642 1 0 0
T4 46053 0 0 0
T5 32397 0 0 0
T8 604 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T38 0 2 0 0
T41 0 1 0 0
T53 532 0 0 0
T54 522 0 0 0
T65 506 0 0 0
T167 0 2 0 0
T169 0 2 0 0
T172 0 1 0 0
T174 0 1 0 0
T194 0 1 0 0
T216 0 2 0 0
T238 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T6,T7
10CoveredT1,T6,T7
11CoveredT1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT10,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T6,T7 VC_COV_UNR
1CoveredT10,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT10,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT2,T10,T11
10CoveredT1,T6,T7
11CoveredT10,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT10,T38,T39
01CoveredT102,T216
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT10,T38,T39
01CoveredT38,T39,T174
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT10,T38,T39
1-CoveredT38,T39,T174

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
DebounceSt 148 Covered T10,T38,T39
DetectSt 168 Covered T10,T38,T39
IdleSt 163 Covered T1,T6,T7
StableSt 191 Covered T10,T38,T39


transitions   Line No.   Covered   Tests   
DebounceSt->DetectSt 168 Covered T10,T38,T39
DebounceSt->IdleSt 163 Covered T38,T79,T80
DetectSt->IdleSt 186 Covered T102,T216
DetectSt->StableSt 191 Covered T10,T38,T39
IdleSt->DebounceSt 148 Covered T10,T38,T39
StableSt->IdleSt 206 Covered T38,T39,T174



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T10,T38,T39
0 1 Covered T10,T38,T39
0 0 Excluded T1,T6,T7 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T10,T38,T39
0 Covered T1,T6,T7


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T10,T38,T39
IdleSt 0 - - - - - - Covered T1,T6,T7
DebounceSt - 1 - - - - - Covered T79,T80
DebounceSt - 0 1 1 - - - Covered T10,T38,T39
DebounceSt - 0 1 0 - - - Covered T38
DebounceSt - 0 0 - - - - Covered T10,T38,T39
DetectSt - - - - 1 - - Covered T102,T216
DetectSt - - - - 0 1 - Covered T10,T38,T39
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T38,T39,T174
StableSt - - - - - - 0 Covered T10,T38,T39
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
CntClr_A 7060683 65 0 0
CntIncr_A 7060683 34875 0 0
CntNoWrap_A 7060683 6422172 0 0
DetectStDropOut_A 7060683 2 0 0
DetectedOut_A 7060683 109528 0 0
DetectedPulseOut_A 7060683 29 0 0
DisabledIdleSt_A 7060683 5969233 0 0
DisabledNoDetection_A 7060683 5971538 0 0
EnterDebounceSt_A 7060683 34 0 0
EnterDetectSt_A 7060683 31 0 0
EnterStableSt_A 7060683 29 0 0
PulseIsPulse_A 7060683 29 0 0
StayInStableSt 7060683 109485 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 7060683 6334 0 0
gen_low_level_sva.LowLevelEvent_A 7060683 6424588 0 0
gen_not_sticky_sva.StableStDropOut_A 7060683 15 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 65 0 0
T10 628 2 0 0
T11 535 0 0 0
T12 60652 0 0 0
T38 0 5 0 0
T39 0 2 0 0
T45 5467 0 0 0
T46 749 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T79 0 1 0 0
T157 0 2 0 0
T167 0 6 0 0
T174 0 2 0 0
T200 0 2 0 0
T225 0 2 0 0
T226 402 0 0 0
T253 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 34875 0 0
T10 628 82 0 0
T11 535 0 0 0
T12 60652 0 0 0
T38 0 208 0 0
T39 0 93 0 0
T45 5467 0 0 0
T46 749 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T79 0 31 0 0
T157 0 89 0 0
T167 0 193 0 0
T174 0 74 0 0
T200 0 73 0 0
T225 0 15 0 0
T226 402 0 0 0
T253 0 28 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6422172 0 0
T1 13064 12657 0 0
T2 654 253 0 0
T6 36894 35291 0 0
T7 496 95 0 0
T13 503 102 0 0
T14 5222 4821 0 0
T15 419 18 0 0
T16 490 89 0 0
T17 505 104 0 0
T18 55144 54743 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 2 0 0
T102 68596 1 0 0
T216 0 1 0 0
T254 3749 0 0 0
T255 796 0 0 0
T256 416 0 0 0
T257 570 0 0 0
T258 19233 0 0 0
T259 523 0 0 0
T260 3080 0 0 0
T261 487 0 0 0
T262 523 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 109528 0 0
T10 628 39 0 0
T11 535 0 0 0
T12 60652 0 0 0
T38 0 218 0 0
T39 0 134 0 0
T45 5467 0 0 0
T46 749 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T118 0 21 0 0
T157 0 13 0 0
T167 0 224 0 0
T174 0 174 0 0
T200 0 54 0 0
T225 0 42 0 0
T226 402 0 0 0
T253 0 106 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 29 0 0
T10 628 1 0 0
T11 535 0 0 0
T12 60652 0 0 0
T38 0 2 0 0
T39 0 1 0 0
T45 5467 0 0 0
T46 749 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T118 0 2 0 0
T157 0 1 0 0
T167 0 3 0 0
T174 0 1 0 0
T200 0 1 0 0
T225 0 1 0 0
T226 402 0 0 0
T253 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 5969233 0 0
T1 13064 12657 0 0
T2 654 3 0 0
T6 36894 35291 0 0
T7 496 95 0 0
T13 503 102 0 0
T14 5222 4821 0 0
T15 419 18 0 0
T16 490 89 0 0
T17 505 104 0 0
T18 55144 54743 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 5971538 0 0
T1 13064 12661 0 0
T2 654 3 0 0
T6 36894 35294 0 0
T7 496 96 0 0
T13 503 103 0 0
T14 5222 4822 0 0
T15 419 19 0 0
T16 490 90 0 0
T17 505 105 0 0
T18 55144 54744 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 34 0 0
T10 628 1 0 0
T11 535 0 0 0
T12 60652 0 0 0
T38 0 3 0 0
T39 0 1 0 0
T45 5467 0 0 0
T46 749 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T79 0 1 0 0
T157 0 1 0 0
T167 0 3 0 0
T174 0 1 0 0
T200 0 1 0 0
T225 0 1 0 0
T226 402 0 0 0
T253 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 31 0 0
T10 628 1 0 0
T11 535 0 0 0
T12 60652 0 0 0
T38 0 2 0 0
T39 0 1 0 0
T45 5467 0 0 0
T46 749 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T118 0 2 0 0
T157 0 1 0 0
T167 0 3 0 0
T174 0 1 0 0
T200 0 1 0 0
T225 0 1 0 0
T226 402 0 0 0
T253 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 29 0 0
T10 628 1 0 0
T11 535 0 0 0
T12 60652 0 0 0
T38 0 2 0 0
T39 0 1 0 0
T45 5467 0 0 0
T46 749 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T118 0 2 0 0
T157 0 1 0 0
T167 0 3 0 0
T174 0 1 0 0
T200 0 1 0 0
T225 0 1 0 0
T226 402 0 0 0
T253 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 29 0 0
T10 628 1 0 0
T11 535 0 0 0
T12 60652 0 0 0
T38 0 2 0 0
T39 0 1 0 0
T45 5467 0 0 0
T46 749 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T118 0 2 0 0
T157 0 1 0 0
T167 0 3 0 0
T174 0 1 0 0
T200 0 1 0 0
T225 0 1 0 0
T226 402 0 0 0
T253 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 109485 0 0
T10 628 37 0 0
T11 535 0 0 0
T12 60652 0 0 0
T38 0 215 0 0
T39 0 133 0 0
T45 5467 0 0 0
T46 749 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T118 0 19 0 0
T157 0 12 0 0
T167 0 220 0 0
T174 0 173 0 0
T200 0 52 0 0
T225 0 40 0 0
T226 402 0 0 0
T253 0 105 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6334 0 0
T1 13064 34 0 0
T2 654 0 0 0
T3 0 1 0 0
T6 36894 6 0 0
T7 496 7 0 0
T13 503 4 0 0
T14 5222 26 0 0
T15 419 2 0 0
T16 490 9 0 0
T17 505 5 0 0
T18 55144 0 0 0
T27 0 10 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6424588 0 0
T1 13064 12661 0 0
T2 654 254 0 0
T6 36894 35294 0 0
T7 496 96 0 0
T13 503 103 0 0
T14 5222 4822 0 0
T15 419 19 0 0
T16 490 90 0 0
T17 505 105 0 0
T18 55144 54744 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 15 0 0
T38 7479 1 0 0
T39 0 1 0 0
T61 728 0 0 0
T71 10496 0 0 0
T102 0 1 0 0
T118 0 2 0 0
T157 0 1 0 0
T167 0 2 0 0
T174 0 1 0 0
T186 530 0 0 0
T187 637 0 0 0
T188 405 0 0 0
T189 406 0 0 0
T190 445 0 0 0
T191 55684 0 0 0
T192 454 0 0 0
T216 0 1 0 0
T238 0 1 0 0
T253 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T6,T7
10CoveredT1,T6,T7
11CoveredT1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT3,T8,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T6,T7 VC_COV_UNR
1CoveredT3,T8,T4

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT3,T8,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT3,T8,T4
10CoveredT1,T6,T7
11CoveredT3,T8,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT3,T8,T4
01CoveredT82,T207,T167
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT3,T8,T4
01CoveredT4,T11,T38
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT3,T8,T4
1-CoveredT4,T11,T38

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
DebounceSt 148 Covered T3,T8,T4
DetectSt 168 Covered T3,T8,T4
IdleSt 163 Covered T1,T6,T7
StableSt 191 Covered T3,T8,T4


transitions   Line No.   Covered   Tests   
DebounceSt->DetectSt 168 Covered T3,T8,T4
DebounceSt->IdleSt 163 Covered T40,T39,T194
DetectSt->IdleSt 186 Covered T82,T207,T167
DetectSt->StableSt 191 Covered T3,T8,T4
IdleSt->DebounceSt 148 Covered T3,T8,T4
StableSt->IdleSt 206 Covered T4,T11,T38



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T3,T8,T4
0 1 Covered T3,T8,T4
0 0 Excluded T1,T6,T7 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T8,T4
0 Covered T1,T6,T7


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T3,T8,T4
IdleSt 0 - - - - - - Covered T1,T6,T7
DebounceSt - 1 - - - - - Covered T79,T80
DebounceSt - 0 1 1 - - - Covered T3,T8,T4
DebounceSt - 0 1 0 - - - Covered T40,T39,T194
DebounceSt - 0 0 - - - - Covered T3,T8,T4
DetectSt - - - - 1 - - Covered T82,T207,T167
DetectSt - - - - 0 1 - Covered T3,T8,T4
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T4,T11,T38
StableSt - - - - - - 0 Covered T3,T8,T4
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
CntClr_A 7060683 118 0 0
CntIncr_A 7060683 53058 0 0
CntNoWrap_A 7060683 6422119 0 0
DetectStDropOut_A 7060683 4 0 0
DetectedOut_A 7060683 17088 0 0
DetectedPulseOut_A 7060683 51 0 0
DisabledIdleSt_A 7060683 6144879 0 0
DisabledNoDetection_A 7060683 6147182 0 0
EnterDebounceSt_A 7060683 63 0 0
EnterDetectSt_A 7060683 55 0 0
EnterStableSt_A 7060683 51 0 0
PulseIsPulse_A 7060683 51 0 0
StayInStableSt 7060683 17016 0 0
gen_high_level_sva.HighLevelEvent_A 7060683 6424588 0 0
gen_not_sticky_sva.StableStDropOut_A 7060683 30 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 118 0 0
T3 642 2 0 0
T4 46053 2 0 0
T5 32397 0 0 0
T8 604 2 0 0
T11 0 2 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T37 0 2 0 0
T38 0 2 0 0
T39 0 3 0 0
T40 0 1 0 0
T41 0 4 0 0
T53 532 0 0 0
T54 522 0 0 0
T65 506 0 0 0
T125 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 53058 0 0
T3 642 95 0 0
T4 46053 9409 0 0
T5 32397 0 0 0
T8 604 53 0 0
T11 0 39 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T37 0 36 0 0
T38 0 48 0 0
T39 0 186 0 0
T40 0 91 0 0
T41 0 154 0 0
T53 532 0 0 0
T54 522 0 0 0
T65 506 0 0 0
T125 0 89 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6422119 0 0
T1 13064 12657 0 0
T2 654 253 0 0
T6 36894 35291 0 0
T7 496 95 0 0
T13 503 102 0 0
T14 5222 4821 0 0
T15 419 18 0 0
T16 490 89 0 0
T17 505 104 0 0
T18 55144 54743 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 4 0 0
T82 73132 1 0 0
T118 0 1 0 0
T126 1516 0 0 0
T167 0 1 0 0
T194 2720 0 0 0
T207 0 1 0 0
T209 426 0 0 0
T210 7228 0 0 0
T211 424 0 0 0
T212 10349 0 0 0
T213 523 0 0 0
T214 5020 0 0 0
T215 503 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 17088 0 0
T3 642 138 0 0
T4 46053 13411 0 0
T5 32397 0 0 0
T8 604 41 0 0
T11 0 7 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T37 0 89 0 0
T38 0 112 0 0
T39 0 132 0 0
T41 0 286 0 0
T53 532 0 0 0
T54 522 0 0 0
T65 506 0 0 0
T125 0 36 0 0
T194 0 4 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 51 0 0
T3 642 1 0 0
T4 46053 1 0 0
T5 32397 0 0 0
T8 604 1 0 0
T11 0 1 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T37 0 1 0 0
T38 0 1 0 0
T39 0 1 0 0
T41 0 2 0 0
T53 532 0 0 0
T54 522 0 0 0
T65 506 0 0 0
T125 0 1 0 0
T194 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6144879 0 0
T1 13064 12657 0 0
T2 654 253 0 0
T6 36894 35291 0 0
T7 496 95 0 0
T13 503 102 0 0
T14 5222 4821 0 0
T15 419 18 0 0
T16 490 89 0 0
T17 505 104 0 0
T18 55144 54743 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6147182 0 0
T1 13064 12661 0 0
T2 654 254 0 0
T6 36894 35294 0 0
T7 496 96 0 0
T13 503 103 0 0
T14 5222 4822 0 0
T15 419 19 0 0
T16 490 90 0 0
T17 505 105 0 0
T18 55144 54744 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 63 0 0
T3 642 1 0 0
T4 46053 1 0 0
T5 32397 0 0 0
T8 604 1 0 0
T11 0 1 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T37 0 1 0 0
T38 0 1 0 0
T39 0 2 0 0
T40 0 1 0 0
T41 0 2 0 0
T53 532 0 0 0
T54 522 0 0 0
T65 506 0 0 0
T125 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 55 0 0
T3 642 1 0 0
T4 46053 1 0 0
T5 32397 0 0 0
T8 604 1 0 0
T11 0 1 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T37 0 1 0 0
T38 0 1 0 0
T39 0 1 0 0
T41 0 2 0 0
T53 532 0 0 0
T54 522 0 0 0
T65 506 0 0 0
T82 0 1 0 0
T125 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 51 0 0
T3 642 1 0 0
T4 46053 1 0 0
T5 32397 0 0 0
T8 604 1 0 0
T11 0 1 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T37 0 1 0 0
T38 0 1 0 0
T39 0 1 0 0
T41 0 2 0 0
T53 532 0 0 0
T54 522 0 0 0
T65 506 0 0 0
T125 0 1 0 0
T194 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 51 0 0
T3 642 1 0 0
T4 46053 1 0 0
T5 32397 0 0 0
T8 604 1 0 0
T11 0 1 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T37 0 1 0 0
T38 0 1 0 0
T39 0 1 0 0
T41 0 2 0 0
T53 532 0 0 0
T54 522 0 0 0
T65 506 0 0 0
T125 0 1 0 0
T194 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 17016 0 0
T3 642 136 0 0
T4 46053 13410 0 0
T5 32397 0 0 0
T8 604 39 0 0
T11 0 6 0 0
T24 1823 0 0 0
T25 693 0 0 0
T26 4565 0 0 0
T37 0 87 0 0
T38 0 111 0 0
T39 0 130 0 0
T41 0 284 0 0
T53 532 0 0 0
T54 522 0 0 0
T65 506 0 0 0
T125 0 34 0 0
T194 0 3 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6424588 0 0
T1 13064 12661 0 0
T2 654 254 0 0
T6 36894 35294 0 0
T7 496 96 0 0
T13 503 103 0 0
T14 5222 4822 0 0
T15 419 19 0 0
T16 490 90 0 0
T17 505 105 0 0
T18 55144 54744 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 30 0 0
T4 46053 1 0 0
T5 32397 0 0 0
T9 1381 0 0 0
T10 628 0 0 0
T11 535 1 0 0
T38 0 1 0 0
T41 0 2 0 0
T45 5467 0 0 0
T62 493 0 0 0
T65 506 0 0 0
T76 420 0 0 0
T121 0 2 0 0
T124 422 0 0 0
T166 0 1 0 0
T167 0 1 0 0
T168 0 2 0 0
T172 0 1 0 0
T194 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464393.48
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125322990.62
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 0 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211885.71
Logical211885.71
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T6,T7
10CoveredT1,T6,T7
11CoveredT1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT2,T36,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T6,T7 VC_COV_UNR
1CoveredT2,T36,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT2,T36,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT2,T8,T36
10CoveredT1,T6,T7
11CoveredT2,T36,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT2,T36,T38
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT2,T36,T38
01CoveredT36,T41,T39
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT2,T36,T38
1-CoveredT36,T41,T39

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
DebounceSt 148 Covered T2,T36,T38
DetectSt 168 Covered T2,T36,T38
IdleSt 163 Covered T1,T6,T7
StableSt 191 Covered T2,T36,T38


transitions   Line No.   Covered   Tests   
DebounceSt->DetectSt 168 Covered T2,T36,T38
DebounceSt->IdleSt 163 Covered T79,T80
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T2,T36,T38
IdleSt->DebounceSt 148 Covered T2,T36,T38
StableSt->IdleSt 206 Covered T36,T38,T40



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T2,T36,T38
0 1 Covered T2,T36,T38
0 0 Excluded T1,T6,T7 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T36,T38
0 Covered T1,T6,T7


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T2,T36,T38
IdleSt 0 - - - - - - Covered T1,T6,T7
DebounceSt - 1 - - - - - Covered T79,T80
DebounceSt - 0 1 1 - - - Covered T2,T36,T38
DebounceSt - 0 1 0 - - - Not Covered
DebounceSt - 0 0 - - - - Covered T2,T36,T38
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T2,T36,T38
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T36,T41,T39
StableSt - - - - - - 0 Covered T2,T36,T38
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
CntClr_A 7060683 82 0 0
CntIncr_A 7060683 2111 0 0
CntNoWrap_A 7060683 6422155 0 0
DetectStDropOut_A 7060683 0 0 0
DetectedOut_A 7060683 2472 0 0
DetectedPulseOut_A 7060683 40 0 0
DisabledIdleSt_A 7060683 6406839 0 0
DisabledNoDetection_A 7060683 6409142 0 0
EnterDebounceSt_A 7060683 42 0 0
EnterDetectSt_A 7060683 40 0 0
EnterStableSt_A 7060683 40 0 0
PulseIsPulse_A 7060683 40 0 0
StayInStableSt 7060683 2410 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 7060683 6350 0 0
gen_low_level_sva.LowLevelEvent_A 7060683 6424588 0 0
gen_not_sticky_sva.StableStDropOut_A 7060683 18 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 82 0 0
T2 654 2 0 0
T3 642 0 0 0
T8 604 0 0 0
T18 55144 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T27 5561 0 0 0
T30 1149 0 0 0
T36 0 4 0 0
T38 0 2 0 0
T39 0 2 0 0
T40 0 2 0 0
T41 0 4 0 0
T43 0 2 0 0
T52 636 0 0 0
T53 532 0 0 0
T136 0 2 0 0
T156 0 4 0 0
T207 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 2111 0 0
T2 654 73 0 0
T3 642 0 0 0
T8 604 0 0 0
T18 55144 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T27 5561 0 0 0
T30 1149 0 0 0
T36 0 104 0 0
T38 0 48 0 0
T39 0 93 0 0
T40 0 91 0 0
T41 0 154 0 0
T43 0 51 0 0
T52 636 0 0 0
T53 532 0 0 0
T136 0 91 0 0
T156 0 20 0 0
T207 0 68 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6422155 0 0
T1 13064 12657 0 0
T2 654 251 0 0
T6 36894 35291 0 0
T7 496 95 0 0
T13 503 102 0 0
T14 5222 4821 0 0
T15 419 18 0 0
T16 490 89 0 0
T17 505 104 0 0
T18 55144 54743 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 2472 0 0
T2 654 42 0 0
T3 642 0 0 0
T8 604 0 0 0
T18 55144 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T27 5561 0 0 0
T30 1149 0 0 0
T36 0 83 0 0
T38 0 88 0 0
T39 0 41 0 0
T40 0 41 0 0
T41 0 80 0 0
T43 0 71 0 0
T52 636 0 0 0
T53 532 0 0 0
T136 0 45 0 0
T156 0 158 0 0
T207 0 163 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 40 0 0
T2 654 1 0 0
T3 642 0 0 0
T8 604 0 0 0
T18 55144 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T27 5561 0 0 0
T30 1149 0 0 0
T36 0 2 0 0
T38 0 1 0 0
T39 0 1 0 0
T40 0 1 0 0
T41 0 2 0 0
T43 0 1 0 0
T52 636 0 0 0
T53 532 0 0 0
T136 0 1 0 0
T156 0 2 0 0
T207 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6406839 0 0
T1 13064 12657 0 0
T2 654 3 0 0
T6 36894 35291 0 0
T7 496 95 0 0
T13 503 102 0 0
T14 5222 4821 0 0
T15 419 18 0 0
T16 490 89 0 0
T17 505 104 0 0
T18 55144 54743 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6409142 0 0
T1 13064 12661 0 0
T2 654 3 0 0
T6 36894 35294 0 0
T7 496 96 0 0
T13 503 103 0 0
T14 5222 4822 0 0
T15 419 19 0 0
T16 490 90 0 0
T17 505 105 0 0
T18 55144 54744 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 42 0 0
T2 654 1 0 0
T3 642 0 0 0
T8 604 0 0 0
T18 55144 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T27 5561 0 0 0
T30 1149 0 0 0
T36 0 2 0 0
T38 0 1 0 0
T39 0 1 0 0
T40 0 1 0 0
T41 0 2 0 0
T43 0 1 0 0
T52 636 0 0 0
T53 532 0 0 0
T136 0 1 0 0
T156 0 2 0 0
T207 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 40 0 0
T2 654 1 0 0
T3 642 0 0 0
T8 604 0 0 0
T18 55144 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T27 5561 0 0 0
T30 1149 0 0 0
T36 0 2 0 0
T38 0 1 0 0
T39 0 1 0 0
T40 0 1 0 0
T41 0 2 0 0
T43 0 1 0 0
T52 636 0 0 0
T53 532 0 0 0
T136 0 1 0 0
T156 0 2 0 0
T207 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 40 0 0
T2 654 1 0 0
T3 642 0 0 0
T8 604 0 0 0
T18 55144 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T27 5561 0 0 0
T30 1149 0 0 0
T36 0 2 0 0
T38 0 1 0 0
T39 0 1 0 0
T40 0 1 0 0
T41 0 2 0 0
T43 0 1 0 0
T52 636 0 0 0
T53 532 0 0 0
T136 0 1 0 0
T156 0 2 0 0
T207 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 40 0 0
T2 654 1 0 0
T3 642 0 0 0
T8 604 0 0 0
T18 55144 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T27 5561 0 0 0
T30 1149 0 0 0
T36 0 2 0 0
T38 0 1 0 0
T39 0 1 0 0
T40 0 1 0 0
T41 0 2 0 0
T43 0 1 0 0
T52 636 0 0 0
T53 532 0 0 0
T136 0 1 0 0
T156 0 2 0 0
T207 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 2410 0 0
T2 654 40 0 0
T3 642 0 0 0
T8 604 0 0 0
T18 55144 0 0 0
T24 1823 0 0 0
T25 693 0 0 0
T27 5561 0 0 0
T30 1149 0 0 0
T36 0 80 0 0
T38 0 86 0 0
T39 0 40 0 0
T40 0 39 0 0
T41 0 77 0 0
T43 0 70 0 0
T52 636 0 0 0
T53 532 0 0 0
T136 0 43 0 0
T156 0 155 0 0
T207 0 162 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6350 0 0
T1 13064 32 0 0
T2 654 1 0 0
T6 36894 9 0 0
T7 496 9 0 0
T13 503 5 0 0
T14 5222 23 0 0
T15 419 1 0 0
T16 490 6 0 0
T17 505 3 0 0
T18 55144 0 0 0
T27 0 10 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6424588 0 0
T1 13064 12661 0 0
T2 654 254 0 0
T6 36894 35294 0 0
T7 496 96 0 0
T13 503 103 0 0
T14 5222 4822 0 0
T15 419 19 0 0
T16 490 90 0 0
T17 505 105 0 0
T18 55144 54744 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 18 0 0
T36 875 1 0 0
T39 0 1 0 0
T41 0 1 0 0
T43 0 1 0 0
T48 713 0 0 0
T49 6372 0 0 0
T67 506 0 0 0
T118 0 1 0 0
T121 0 1 0 0
T134 423 0 0 0
T156 0 1 0 0
T167 0 1 0 0
T195 407 0 0 0
T196 503 0 0 0
T197 416 0 0 0
T198 422 0 0 0
T199 507 0 0 0
T207 0 1 0 0
T216 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T6,T7
10CoveredT1,T6,T7
11CoveredT1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT11,T36,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T6,T7 VC_COV_UNR
1CoveredT11,T36,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT11,T36,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT8,T11,T58
10CoveredT1,T6,T7
11CoveredT11,T36,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT11,T36,T40
01CoveredT36,T172,T263
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT11,T36,T40
01CoveredT11,T37,T174
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT11,T36,T40
1-CoveredT11,T37,T174

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
DebounceSt 148 Covered T11,T36,T40
DetectSt 168 Covered T11,T36,T40
IdleSt 163 Covered T1,T6,T7
StableSt 191 Covered T11,T36,T40


transitions   Line No.   Covered   Tests   
DebounceSt->DetectSt 168 Covered T11,T36,T40
DebounceSt->IdleSt 163 Covered T36,T79,T80
DetectSt->IdleSt 186 Covered T36,T172,T263
DetectSt->StableSt 191 Covered T11,T36,T40
IdleSt->DebounceSt 148 Covered T11,T36,T40
StableSt->IdleSt 206 Covered T11,T40,T37



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T11,T36,T40
0 1 Covered T11,T36,T40
0 0 Excluded T1,T6,T7 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T11,T36,T40
0 Covered T1,T6,T7


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T11,T36,T40
IdleSt 0 - - - - - - Covered T1,T6,T7
DebounceSt - 1 - - - - - Covered T79,T80
DebounceSt - 0 1 1 - - - Covered T11,T36,T40
DebounceSt - 0 1 0 - - - Covered T36,T193
DebounceSt - 0 0 - - - - Covered T11,T36,T40
DetectSt - - - - 1 - - Covered T36,T172,T263
DetectSt - - - - 0 1 - Covered T11,T36,T40
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T11,T37,T174
StableSt - - - - - - 0 Covered T11,T36,T40
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
CntClr_A 7060683 116 0 0
CntIncr_A 7060683 119240 0 0
CntNoWrap_A 7060683 6422121 0 0
DetectStDropOut_A 7060683 3 0 0
DetectedOut_A 7060683 117545 0 0
DetectedPulseOut_A 7060683 53 0 0
DisabledIdleSt_A 7060683 6102788 0 0
DisabledNoDetection_A 7060683 6105090 0 0
EnterDebounceSt_A 7060683 60 0 0
EnterDetectSt_A 7060683 56 0 0
EnterStableSt_A 7060683 53 0 0
PulseIsPulse_A 7060683 53 0 0
StayInStableSt 7060683 117463 0 0
gen_high_level_sva.HighLevelEvent_A 7060683 6424588 0 0
gen_not_sticky_sva.StableStDropOut_A 7060683 24 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 116 0 0
T11 535 2 0 0
T12 60652 0 0 0
T36 0 5 0 0
T37 0 2 0 0
T40 0 2 0 0
T43 0 4 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 2 0 0
T155 0 2 0 0
T156 0 4 0 0
T174 0 2 0 0
T226 402 0 0 0
T264 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 119240 0 0
T11 535 39 0 0
T12 60652 0 0 0
T36 0 156 0 0
T37 0 36 0 0
T40 0 91 0 0
T43 0 102 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 17062 0 0
T155 0 20 0 0
T156 0 20 0 0
T174 0 74 0 0
T226 402 0 0 0
T264 0 54 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6422121 0 0
T1 13064 12657 0 0
T2 654 253 0 0
T6 36894 35291 0 0
T7 496 95 0 0
T13 503 102 0 0
T14 5222 4821 0 0
T15 419 18 0 0
T16 490 89 0 0
T17 505 104 0 0
T18 55144 54743 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 3 0 0
T36 875 1 0 0
T48 713 0 0 0
T49 6372 0 0 0
T67 506 0 0 0
T134 423 0 0 0
T172 0 1 0 0
T195 407 0 0 0
T196 503 0 0 0
T197 416 0 0 0
T198 422 0 0 0
T199 507 0 0 0
T263 0 1 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 117545 0 0
T11 535 9 0 0
T12 60652 0 0 0
T36 0 43 0 0
T37 0 15 0 0
T40 0 42 0 0
T43 0 258 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 38556 0 0
T155 0 124 0 0
T156 0 50 0 0
T174 0 148 0 0
T226 402 0 0 0
T264 0 208 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 53 0 0
T11 535 1 0 0
T12 60652 0 0 0
T36 0 1 0 0
T37 0 1 0 0
T40 0 1 0 0
T43 0 2 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 1 0 0
T155 0 1 0 0
T156 0 2 0 0
T174 0 1 0 0
T226 402 0 0 0
T264 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6102788 0 0
T1 13064 12657 0 0
T2 654 253 0 0
T6 36894 35291 0 0
T7 496 95 0 0
T13 503 102 0 0
T14 5222 4821 0 0
T15 419 18 0 0
T16 490 89 0 0
T17 505 104 0 0
T18 55144 54743 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6105090 0 0
T1 13064 12661 0 0
T2 654 254 0 0
T6 36894 35294 0 0
T7 496 96 0 0
T13 503 103 0 0
T14 5222 4822 0 0
T15 419 19 0 0
T16 490 90 0 0
T17 505 105 0 0
T18 55144 54744 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 60 0 0
T11 535 1 0 0
T12 60652 0 0 0
T36 0 3 0 0
T37 0 1 0 0
T40 0 1 0 0
T43 0 2 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 1 0 0
T155 0 1 0 0
T156 0 2 0 0
T174 0 1 0 0
T226 402 0 0 0
T264 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 56 0 0
T11 535 1 0 0
T12 60652 0 0 0
T36 0 2 0 0
T37 0 1 0 0
T40 0 1 0 0
T43 0 2 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 1 0 0
T155 0 1 0 0
T156 0 2 0 0
T174 0 1 0 0
T226 402 0 0 0
T264 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 53 0 0
T11 535 1 0 0
T12 60652 0 0 0
T36 0 1 0 0
T37 0 1 0 0
T40 0 1 0 0
T43 0 2 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 1 0 0
T155 0 1 0 0
T156 0 2 0 0
T174 0 1 0 0
T226 402 0 0 0
T264 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 53 0 0
T11 535 1 0 0
T12 60652 0 0 0
T36 0 1 0 0
T37 0 1 0 0
T40 0 1 0 0
T43 0 2 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 1 0 0
T155 0 1 0 0
T156 0 2 0 0
T174 0 1 0 0
T226 402 0 0 0
T264 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 117463 0 0
T11 535 8 0 0
T12 60652 0 0 0
T36 0 41 0 0
T37 0 14 0 0
T40 0 40 0 0
T43 0 255 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 38555 0 0
T155 0 122 0 0
T156 0 48 0 0
T174 0 147 0 0
T226 402 0 0 0
T264 0 206 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6424588 0 0
T1 13064 12661 0 0
T2 654 254 0 0
T6 36894 35294 0 0
T7 496 96 0 0
T13 503 103 0 0
T14 5222 4822 0 0
T15 419 19 0 0
T16 490 90 0 0
T17 505 105 0 0
T18 55144 54744 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 24 0 0
T11 535 1 0 0
T12 60652 0 0 0
T37 0 1 0 0
T43 0 1 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 1 0 0
T83 0 1 0 0
T121 0 1 0 0
T156 0 2 0 0
T169 0 1 0 0
T174 0 1 0 0
T208 0 1 0 0
T226 402 0 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T6,T7
10CoveredT1,T6,T7
11CoveredT1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT11,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T6,T7 VC_COV_UNR
1CoveredT11,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T6,T7
1CoveredT11,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT2,T11,T58
10CoveredT1,T6,T7
11CoveredT11,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT11,T36,T37
01CoveredT83
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT11,T36,T37
01CoveredT36,T207,T167
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT11,T36,T37
1-CoveredT36,T207,T167

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
DebounceSt 148 Covered T11,T36,T37
DetectSt 168 Covered T11,T36,T37
IdleSt 163 Covered T1,T6,T7
StableSt 191 Covered T11,T36,T37


transitions   Line No.   Covered   Tests   
DebounceSt->DetectSt 168 Covered T11,T36,T37
DebounceSt->IdleSt 163 Covered T79,T80,T175
DetectSt->IdleSt 186 Covered T83
DetectSt->StableSt 191 Covered T11,T36,T37
IdleSt->DebounceSt 148 Covered T11,T36,T37
StableSt->IdleSt 206 Covered T36,T37,T174



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T11,T36,T37
0 1 Covered T11,T36,T37
0 0 Excluded T1,T6,T7 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T11,T36,T37
0 Covered T1,T6,T7


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T11,T36,T37
IdleSt 0 - - - - - - Covered T1,T6,T7
DebounceSt - 1 - - - - - Covered T79,T80
DebounceSt - 0 1 1 - - - Covered T11,T36,T37
DebounceSt - 0 1 0 - - - Covered T175,T176
DebounceSt - 0 0 - - - - Covered T11,T36,T37
DetectSt - - - - 1 - - Covered T83
DetectSt - - - - 0 1 - Covered T11,T36,T37
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T36,T207,T167
StableSt - - - - - - 0 Covered T11,T36,T37
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T6,T7
0 Covered T1,T6,T7


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
CntClr_A 7060683 68 0 0
CntIncr_A 7060683 18658 0 0
CntNoWrap_A 7060683 6422169 0 0
DetectStDropOut_A 7060683 1 0 0
DetectedOut_A 7060683 2736 0 0
DetectedPulseOut_A 7060683 31 0 0
DisabledIdleSt_A 7060683 6272765 0 0
DisabledNoDetection_A 7060683 6275068 0 0
EnterDebounceSt_A 7060683 36 0 0
EnterDetectSt_A 7060683 32 0 0
EnterStableSt_A 7060683 31 0 0
PulseIsPulse_A 7060683 31 0 0
StayInStableSt 7060683 2688 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 7060683 7024 0 0
gen_low_level_sva.LowLevelEvent_A 7060683 6424588 0 0
gen_not_sticky_sva.StableStDropOut_A 7060683 14 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 68 0 0
T11 535 2 0 0
T12 60652 0 0 0
T36 0 4 0 0
T37 0 2 0 0
T42 0 2 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 2 0 0
T166 0 2 0 0
T167 0 2 0 0
T174 0 2 0 0
T207 0 2 0 0
T208 0 2 0 0
T226 402 0 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 18658 0 0
T11 535 39 0 0
T12 60652 0 0 0
T36 0 104 0 0
T37 0 36 0 0
T42 0 28 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 17062 0 0
T166 0 95 0 0
T167 0 48 0 0
T174 0 74 0 0
T207 0 68 0 0
T208 0 42 0 0
T226 402 0 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6422169 0 0
T1 13064 12657 0 0
T2 654 253 0 0
T6 36894 35291 0 0
T7 496 95 0 0
T13 503 102 0 0
T14 5222 4821 0 0
T15 419 18 0 0
T16 490 89 0 0
T17 505 104 0 0
T18 55144 54743 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 1 0 0
T79 7250 0 0 0
T81 7479 0 0 0
T83 17667 1 0 0
T177 28954 0 0 0
T178 28628 0 0 0
T179 14502 0 0 0
T180 7489 0 0 0
T181 521 0 0 0
T182 12426 0 0 0
T183 816 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 2736 0 0
T11 535 38 0 0
T12 60652 0 0 0
T36 0 159 0 0
T37 0 37 0 0
T42 0 49 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 41 0 0
T166 0 46 0 0
T167 0 227 0 0
T174 0 172 0 0
T207 0 43 0 0
T208 0 42 0 0
T226 402 0 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 31 0 0
T11 535 1 0 0
T12 60652 0 0 0
T36 0 2 0 0
T37 0 1 0 0
T42 0 1 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 1 0 0
T166 0 1 0 0
T167 0 1 0 0
T174 0 1 0 0
T207 0 1 0 0
T208 0 1 0 0
T226 402 0 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6272765 0 0
T1 13064 12657 0 0
T2 654 3 0 0
T6 36894 35291 0 0
T7 496 95 0 0
T13 503 102 0 0
T14 5222 4821 0 0
T15 419 18 0 0
T16 490 89 0 0
T17 505 104 0 0
T18 55144 54743 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6275068 0 0
T1 13064 12661 0 0
T2 654 3 0 0
T6 36894 35294 0 0
T7 496 96 0 0
T13 503 103 0 0
T14 5222 4822 0 0
T15 419 19 0 0
T16 490 90 0 0
T17 505 105 0 0
T18 55144 54744 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 36 0 0
T11 535 1 0 0
T12 60652 0 0 0
T36 0 2 0 0
T37 0 1 0 0
T42 0 1 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 1 0 0
T166 0 1 0 0
T167 0 1 0 0
T174 0 1 0 0
T207 0 1 0 0
T208 0 1 0 0
T226 402 0 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 32 0 0
T11 535 1 0 0
T12 60652 0 0 0
T36 0 2 0 0
T37 0 1 0 0
T42 0 1 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 1 0 0
T166 0 1 0 0
T167 0 1 0 0
T174 0 1 0 0
T207 0 1 0 0
T208 0 1 0 0
T226 402 0 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 31 0 0
T11 535 1 0 0
T12 60652 0 0 0
T36 0 2 0 0
T37 0 1 0 0
T42 0 1 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 1 0 0
T166 0 1 0 0
T167 0 1 0 0
T174 0 1 0 0
T207 0 1 0 0
T208 0 1 0 0
T226 402 0 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 31 0 0
T11 535 1 0 0
T12 60652 0 0 0
T36 0 2 0 0
T37 0 1 0 0
T42 0 1 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 1 0 0
T166 0 1 0 0
T167 0 1 0 0
T174 0 1 0 0
T207 0 1 0 0
T208 0 1 0 0
T226 402 0 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 2688 0 0
T11 535 36 0 0
T12 60652 0 0 0
T36 0 157 0 0
T37 0 35 0 0
T42 0 47 0 0
T45 5467 0 0 0
T46 749 0 0 0
T57 685 0 0 0
T62 493 0 0 0
T66 502 0 0 0
T76 420 0 0 0
T77 449 0 0 0
T82 0 39 0 0
T166 0 44 0 0
T167 0 226 0 0
T174 0 170 0 0
T207 0 42 0 0
T208 0 40 0 0
T226 402 0 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 7024 0 0
T1 13064 25 0 0
T2 654 0 0 0
T6 36894 10 0 0
T7 496 10 0 0
T13 503 7 0 0
T14 5222 24 0 0
T15 419 2 0 0
T16 490 8 0 0
T17 505 4 0 0
T18 55144 3 0 0
T27 0 12 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 6424588 0 0
T1 13064 12661 0 0
T2 654 254 0 0
T6 36894 35294 0 0
T7 496 96 0 0
T13 503 103 0 0
T14 5222 4822 0 0
T15 419 19 0 0
T16 490 90 0 0
T17 505 105 0 0
T18 55144 54744 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7060683 14 0 0
T36 875 2 0 0
T48 713 0 0 0
T49 6372 0 0 0
T67 506 0 0 0
T102 0 3 0 0
T104 0 1 0 0
T106 0 1 0 0
T134 423 0 0 0
T167 0 1 0 0
T195 407 0 0 0
T196 503 0 0 0
T197 416 0 0 0
T198 422 0 0 0
T199 507 0 0 0
T207 0 1 0 0
T216 0 1 0 0
T238 0 1 0 0
T239 0 1 0 0
T265 0 1 0 0