Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T26
1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T14,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T14,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T14,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T5,T33
1	1	Covered	T1,T14,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T26
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T70,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T33,T32
0	1	Covered	T5,T33,T32
1	0	Covered	T266

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T33,T32
1	-	Covered	T5,T33,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T26
DetectSt	168	Covered	T1,T14,T26
IdleSt	163	Covered	T1,T6,T7
StableSt	191	Covered	T5,T33,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T26
DebounceSt->IdleSt	163	Covered	T219,T214,T267
DetectSt->IdleSt	186	Covered	T1,T14,T26
DetectSt->StableSt	191	Covered	T5,T33,T32
IdleSt->DebounceSt	148	Covered	T1,T14,T26
StableSt->IdleSt	206	Covered	T5,T33,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T14,T26
0	1	Covered	T1,T14,T26
0	0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T26
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T26
IdleSt	0	-	-	-	-	-	-	Covered	T1,T14,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T219,T214,T267
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T26
DetectSt	-	-	-	-	1	-	-	Covered	T1,T14,T26
DetectSt	-	-	-	-	0	1	-	Covered	T5,T33,T32
DetectSt	-	-	-	-	0	0	-	Covered	T1,T14,T26
StableSt	-	-	-	-	-	-	1	Covered	T5,T33,T32
StableSt	-	-	-	-	-	-	0	Covered	T5,T33,T32
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7060683	3294	0	0
CntIncr_A	7060683	105201	0	0
CntNoWrap_A	7060683	6418943	0	0
DetectStDropOut_A	7060683	455	0	0
DetectedOut_A	7060683	76378	0	0
DetectedPulseOut_A	7060683	969	0	0
DisabledIdleSt_A	7060683	5972575	0	0
DisabledNoDetection_A	7060683	5974715	0	0
EnterDebounceSt_A	7060683	1668	0	0
EnterDetectSt_A	7060683	1627	0	0
EnterStableSt_A	7060683	969	0	0
PulseIsPulse_A	7060683	969	0	0
StayInStableSt	7060683	75290	0	0
gen_high_event_sva.HighLevelEvent_A	7060683	6424588	0	0
gen_high_level_sva.HighLevelEvent_A	7060683	6424588	0	0
gen_not_sticky_sva.StableStDropOut_A	7060683	844	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	3294	0	0
T1	13064	28	0	0
T2	654	0	0	0
T5	0	28	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	52	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	60	0	0
T32	0	44	0	0
T33	0	12	0	0
T45	0	52	0	0
T49	0	48	0	0
T69	0	52	0	0
T70	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	105201	0	0
T1	13064	754	0	0
T2	654	0	0	0
T5	0	868	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	1351	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1163	0	0
T32	0	902	0	0
T33	0	276	0	0
T45	0	1481	0	0
T49	0	1795	0	0
T69	0	5980	0	0
T70	0	1373	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6418943	0	0
T1	13064	12629	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4769	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	455	0	0
T1	13064	7	0	0
T2	654	0	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	26	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	30	0	0
T45	0	26	0	0
T49	0	24	0	0
T85	0	6	0	0
T97	0	29	0	0
T98	0	11	0	0
T100	0	2	0	0
T268	0	25	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	76378	0	0
T5	32397	942	0	0
T9	1381	0	0	0
T10	628	0	0	0
T11	535	0	0	0
T32	0	1855	0	0
T33	0	235	0	0
T45	5467	0	0	0
T46	749	0	0	0
T62	493	0	0	0
T69	0	4821	0	0
T76	420	0	0	0
T77	449	0	0	0
T122	0	150	0	0
T124	422	0	0	0
T192	0	29	0	0
T219	0	331	0	0
T269	0	230	0	0
T270	0	53	0	0
T271	0	245	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	969	0	0
T5	32397	14	0	0
T9	1381	0	0	0
T10	628	0	0	0
T11	535	0	0	0
T32	0	22	0	0
T33	0	6	0	0
T45	5467	0	0	0
T46	749	0	0	0
T62	493	0	0	0
T69	0	26	0	0
T76	420	0	0	0
T77	449	0	0	0
T122	0	4	0	0
T124	422	0	0	0
T192	0	1	0	0
T219	0	2	0	0
T269	0	11	0	0
T270	0	4	0	0
T271	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	5972575	0	0
T1	13064	9738	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	2015	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	5974715	0	0
T1	13064	9741	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	2015	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	1668	0	0
T1	13064	14	0	0
T2	654	0	0	0
T5	0	14	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	26	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	30	0	0
T32	0	22	0	0
T33	0	6	0	0
T45	0	26	0	0
T49	0	24	0	0
T69	0	26	0	0
T70	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	1627	0	0
T1	13064	14	0	0
T2	654	0	0	0
T5	0	14	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	26	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	30	0	0
T32	0	22	0	0
T33	0	6	0	0
T45	0	26	0	0
T49	0	24	0	0
T69	0	26	0	0
T70	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	969	0	0
T5	32397	14	0	0
T9	1381	0	0	0
T10	628	0	0	0
T11	535	0	0	0
T32	0	22	0	0
T33	0	6	0	0
T45	5467	0	0	0
T46	749	0	0	0
T62	493	0	0	0
T69	0	26	0	0
T76	420	0	0	0
T77	449	0	0	0
T122	0	4	0	0
T124	422	0	0	0
T192	0	1	0	0
T219	0	2	0	0
T269	0	11	0	0
T270	0	4	0	0
T271	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	969	0	0
T5	32397	14	0	0
T9	1381	0	0	0
T10	628	0	0	0
T11	535	0	0	0
T32	0	22	0	0
T33	0	6	0	0
T45	5467	0	0	0
T46	749	0	0	0
T62	493	0	0	0
T69	0	26	0	0
T76	420	0	0	0
T77	449	0	0	0
T122	0	4	0	0
T124	422	0	0	0
T192	0	1	0	0
T219	0	2	0	0
T269	0	11	0	0
T270	0	4	0	0
T271	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	75290	0	0
T5	32397	925	0	0
T9	1381	0	0	0
T10	628	0	0	0
T11	535	0	0	0
T32	0	1832	0	0
T33	0	229	0	0
T45	5467	0	0	0
T46	749	0	0	0
T62	493	0	0	0
T69	0	4791	0	0
T76	420	0	0	0
T77	449	0	0	0
T122	0	145	0	0
T124	422	0	0	0
T192	0	27	0	0
T219	0	329	0	0
T269	0	219	0	0
T270	0	49	0	0
T271	0	234	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	844	0	0
T5	32397	11	0	0
T9	1381	0	0	0
T10	628	0	0	0
T11	535	0	0	0
T32	0	21	0	0
T33	0	6	0	0
T45	5467	0	0	0
T46	749	0	0	0
T62	493	0	0	0
T69	0	22	0	0
T76	420	0	0	0
T77	449	0	0	0
T122	0	3	0	0
T124	422	0	0	0
T219	0	2	0	0
T269	0	10	0	0
T270	0	4	0	0
T271	0	11	0	0
T272	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T27
1	Covered	T1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T27,T5,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T6,T7	VC_COV_UNR
1	Covered	T27,T5,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T27,T5,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T5,T12
1	0	Covered	T1,T6,T14
1	1	Covered	T27,T5,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T5,T12
0	1	Covered	T35,T99,T101
1	0	Covered	T79,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T5,T12
0	1	Covered	T27,T12,T34
1	0	Covered	T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T5,T12
1	-	Covered	T27,T12,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T5,T12
DetectSt	168	Covered	T27,T5,T12
IdleSt	163	Covered	T1,T6,T7
StableSt	191	Covered	T27,T5,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T5,T12
DebounceSt->IdleSt	163	Covered	T50,T191,T192
DetectSt->IdleSt	186	Covered	T35,T99,T101
DetectSt->StableSt	191	Covered	T27,T5,T12
IdleSt->DebounceSt	148	Covered	T27,T5,T12
StableSt->IdleSt	206	Covered	T27,T5,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T27,T5,T12
0	1	Covered	T27,T5,T12
0	0	Excluded	T1,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T5,T12
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T5,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T5,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T50,T191,T192
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T5,T12
DetectSt	-	-	-	-	1	-	-	Covered	T35,T99,T101
DetectSt	-	-	-	-	0	1	-	Covered	T27,T5,T12
DetectSt	-	-	-	-	0	0	-	Covered	T27,T5,T12
StableSt	-	-	-	-	-	-	1	Covered	T27,T12,T34
StableSt	-	-	-	-	-	-	0	Covered	T27,T5,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7060683	935	0	0
CntIncr_A	7060683	48794	0	0
CntNoWrap_A	7060683	6421302	0	0
DetectStDropOut_A	7060683	35	0	0
DetectedOut_A	7060683	17185	0	0
DetectedPulseOut_A	7060683	393	0	0
DisabledIdleSt_A	7060683	6012949	0	0
DisabledNoDetection_A	7060683	6014522	0	0
EnterDebounceSt_A	7060683	505	0	0
EnterDetectSt_A	7060683	432	0	0
EnterStableSt_A	7060683	393	0	0
PulseIsPulse_A	7060683	393	0	0
StayInStableSt	7060683	16767	0	0
gen_high_level_sva.HighLevelEvent_A	7060683	6424588	0	0
gen_not_sticky_sva.StableStDropOut_A	7060683	365	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	935	0	0
T3	642	0	0	0
T5	0	6	0	0
T8	604	0	0	0
T12	0	8	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T27	5561	6	0	0
T30	1149	0	0	0
T31	0	2	0	0
T32	0	8	0	0
T34	0	2	0	0
T35	0	12	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T78	0	18	0	0
T93	0	6	0	0
T94	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	48794	0	0
T3	642	0	0	0
T5	0	270	0	0
T8	604	0	0	0
T12	0	320	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T27	5561	291	0	0
T30	1149	0	0	0
T31	0	25	0	0
T32	0	212	0	0
T34	0	236	0	0
T35	0	602	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T78	0	1206	0	0
T93	0	333	0	0
T94	0	417	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6421302	0	0
T1	13064	12657	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	35	0	0
T32	9888	0	0	0
T35	9224	6	0	0
T68	648	0	0	0
T69	35631	0	0	0
T78	24663	0	0	0
T79	0	1	0	0
T94	19311	0	0	0
T99	0	5	0	0
T101	0	3	0	0
T103	0	2	0	0
T104	0	2	0	0
T105	0	5	0	0
T107	0	1	0	0
T108	0	10	0	0
T109	464	0	0	0
T110	525	0	0	0
T111	502	0	0	0
T112	15187	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	17185	0	0
T3	642	0	0	0
T5	0	202	0	0
T8	604	0	0	0
T12	0	299	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T27	5561	68	0	0
T30	1149	0	0	0
T31	0	3	0	0
T32	0	173	0	0
T34	0	89	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T78	0	102	0	0
T93	0	258	0	0
T94	0	265	0	0
T112	0	8	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	393	0	0
T3	642	0	0	0
T5	0	3	0	0
T8	604	0	0	0
T12	0	4	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T27	5561	3	0	0
T30	1149	0	0	0
T31	0	1	0	0
T32	0	4	0	0
T34	0	1	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T78	0	9	0	0
T93	0	3	0	0
T94	0	3	0	0
T112	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6012949	0	0
T1	13064	12657	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6014522	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	505	0	0
T3	642	0	0	0
T5	0	3	0	0
T8	604	0	0	0
T12	0	4	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T27	5561	3	0	0
T30	1149	0	0	0
T31	0	1	0	0
T32	0	4	0	0
T34	0	1	0	0
T35	0	6	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T78	0	9	0	0
T93	0	3	0	0
T94	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	432	0	0
T3	642	0	0	0
T5	0	3	0	0
T8	604	0	0	0
T12	0	4	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T27	5561	3	0	0
T30	1149	0	0	0
T31	0	1	0	0
T32	0	4	0	0
T34	0	1	0	0
T35	0	6	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T78	0	9	0	0
T93	0	3	0	0
T94	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	393	0	0
T3	642	0	0	0
T5	0	3	0	0
T8	604	0	0	0
T12	0	4	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T27	5561	3	0	0
T30	1149	0	0	0
T31	0	1	0	0
T32	0	4	0	0
T34	0	1	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T78	0	9	0	0
T93	0	3	0	0
T94	0	3	0	0
T112	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	393	0	0
T3	642	0	0	0
T5	0	3	0	0
T8	604	0	0	0
T12	0	4	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T27	5561	3	0	0
T30	1149	0	0	0
T31	0	1	0	0
T32	0	4	0	0
T34	0	1	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T78	0	9	0	0
T93	0	3	0	0
T94	0	3	0	0
T112	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	16767	0	0
T3	642	0	0	0
T5	0	196	0	0
T8	604	0	0	0
T12	0	295	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T27	5561	65	0	0
T30	1149	0	0	0
T31	0	2	0	0
T32	0	169	0	0
T34	0	88	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T78	0	93	0	0
T93	0	255	0	0
T94	0	262	0	0
T112	0	6	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	365	0	0
T3	642	0	0	0
T8	604	0	0	0
T12	0	4	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T27	5561	3	0	0
T30	1149	0	0	0
T31	0	1	0	0
T32	0	4	0	0
T34	0	1	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T59	0	6	0	0
T78	0	9	0	0
T93	0	3	0	0
T94	0	3	0	0
T112	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T26
1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T14,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T14,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T14,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T5,T33
1	1	Covered	T1,T14,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T26
0	1	Covered	T14,T26,T49
1	0	Covered	T270,T273,T247

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T45
0	1	Covered	T1,T5,T45
1	0	Covered	T69,T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T45
1	-	Covered	T1,T5,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T26
DetectSt	168	Covered	T1,T14,T26
IdleSt	163	Covered	T1,T6,T7
StableSt	191	Covered	T1,T5,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T26
DebounceSt->IdleSt	163	Covered	T219,T214,T267
DetectSt->IdleSt	186	Covered	T14,T26,T49
DetectSt->StableSt	191	Covered	T1,T5,T45
IdleSt->DebounceSt	148	Covered	T1,T14,T26
StableSt->IdleSt	206	Covered	T1,T5,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T14,T26
0	1	Covered	T1,T14,T26
0	0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T26
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T26
IdleSt	0	-	-	-	-	-	-	Covered	T1,T14,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T219,T214,T267
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T26
DetectSt	-	-	-	-	1	-	-	Covered	T14,T26,T49
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T45
DetectSt	-	-	-	-	0	0	-	Covered	T1,T14,T26
StableSt	-	-	-	-	-	-	1	Covered	T1,T5,T45
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7060683	3153	0	0
CntIncr_A	7060683	105329	0	0
CntNoWrap_A	7060683	6419084	0	0
DetectStDropOut_A	7060683	377	0	0
DetectedOut_A	7060683	72981	0	0
DetectedPulseOut_A	7060683	1014	0	0
DisabledIdleSt_A	7060683	5977143	0	0
DisabledNoDetection_A	7060683	5979306	0	0
EnterDebounceSt_A	7060683	1594	0	0
EnterDetectSt_A	7060683	1560	0	0
EnterStableSt_A	7060683	1014	0	0
PulseIsPulse_A	7060683	1014	0	0
StayInStableSt	7060683	71870	0	0
gen_high_event_sva.HighLevelEvent_A	7060683	6424588	0	0
gen_high_level_sva.HighLevelEvent_A	7060683	6424588	0	0
gen_not_sticky_sva.StableStDropOut_A	7060683	896	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	3153	0	0
T1	13064	20	0	0
T2	654	0	0	0
T5	0	16	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	10	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	45	0	0
T32	0	42	0	0
T33	0	42	0	0
T45	0	14	0	0
T49	0	20	0	0
T69	0	40	0	0
T70	0	40	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	105329	0	0
T1	13064	280	0	0
T2	654	0	0	0
T5	0	456	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	258	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	897	0	0
T32	0	1512	0	0
T33	0	1281	0	0
T45	0	322	0	0
T49	0	746	0	0
T69	0	4120	0	0
T70	0	1040	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6419084	0	0
T1	13064	12637	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4811	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	377	0	0
T2	654	0	0	0
T3	642	0	0	0
T14	5222	5	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	22	0	0
T27	5561	0	0	0
T30	1149	0	0	0
T49	0	10	0	0
T52	636	0	0	0
T97	0	22	0	0
T247	0	18	0	0
T268	0	11	0	0
T273	0	13	0	0
T274	0	19	0	0
T275	0	20	0	0
T276	0	17	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	72981	0	0
T1	13064	674	0	0
T2	654	0	0	0
T5	0	2174	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	421	0	0
T33	0	1925	0	0
T45	0	71	0	0
T69	0	2347	0	0
T70	0	1747	0	0
T85	0	153	0	0
T122	0	1249	0	0
T269	0	2091	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	1014	0	0
T1	13064	10	0	0
T2	654	0	0	0
T5	0	8	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	21	0	0
T33	0	21	0	0
T45	0	7	0	0
T69	0	20	0	0
T70	0	20	0	0
T85	0	10	0	0
T122	0	13	0	0
T269	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	5977143	0	0
T1	13064	9325	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	2015	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	5979306	0	0
T1	13064	9327	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	2015	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	1594	0	0
T1	13064	10	0	0
T2	654	0	0	0
T5	0	8	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	5	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	23	0	0
T32	0	21	0	0
T33	0	21	0	0
T45	0	7	0	0
T49	0	10	0	0
T69	0	20	0	0
T70	0	20	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	1560	0	0
T1	13064	10	0	0
T2	654	0	0	0
T5	0	8	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	5	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	23	0	0
T32	0	21	0	0
T33	0	21	0	0
T45	0	7	0	0
T49	0	10	0	0
T69	0	20	0	0
T70	0	20	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	1014	0	0
T1	13064	10	0	0
T2	654	0	0	0
T5	0	8	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	21	0	0
T33	0	21	0	0
T45	0	7	0	0
T69	0	20	0	0
T70	0	20	0	0
T85	0	10	0	0
T122	0	13	0	0
T269	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	1014	0	0
T1	13064	10	0	0
T2	654	0	0	0
T5	0	8	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	21	0	0
T33	0	21	0	0
T45	0	7	0	0
T69	0	20	0	0
T70	0	20	0	0
T85	0	10	0	0
T122	0	13	0	0
T269	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	71870	0	0
T1	13064	663	0	0
T2	654	0	0	0
T5	0	2161	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	400	0	0
T33	0	1899	0	0
T45	0	64	0	0
T69	0	2327	0	0
T70	0	1726	0	0
T85	0	143	0	0
T122	0	1236	0	0
T269	0	2060	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	896	0	0
T1	13064	9	0	0
T2	654	0	0	0
T5	0	3	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	21	0	0
T33	0	16	0	0
T45	0	7	0	0
T69	0	8	0	0
T70	0	19	0	0
T85	0	10	0	0
T122	0	13	0	0
T269	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T26
1	Covered	T1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T5,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T6,T7	VC_COV_UNR
1	Covered	T1,T5,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T5,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T45
1	0	Covered	T1,T6,T14
1	1	Covered	T1,T5,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T12
0	1	Covered	T47,T191,T277
1	0	Covered	T79,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T12
0	1	Covered	T1,T5,T12
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T12
1	-	Covered	T1,T5,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T12
DetectSt	168	Covered	T1,T5,T12
IdleSt	163	Covered	T1,T6,T7
StableSt	191	Covered	T1,T5,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T12
DebounceSt->IdleSt	163	Covered	T5,T12,T47
DetectSt->IdleSt	186	Covered	T47,T191,T277
DetectSt->StableSt	191	Covered	T1,T5,T12
IdleSt->DebounceSt	148	Covered	T1,T5,T12
StableSt->IdleSt	206	Covered	T1,T5,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T5,T12
0	1	Covered	T1,T5,T12
0	0	Excluded	T1,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T12
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T5,T12,T47
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T12
DetectSt	-	-	-	-	1	-	-	Covered	T47,T191,T277
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T12
StableSt	-	-	-	-	-	-	1	Covered	T1,T5,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7060683	932	0	0
CntIncr_A	7060683	54303	0	0
CntNoWrap_A	7060683	6421305	0	0
DetectStDropOut_A	7060683	60	0	0
DetectedOut_A	7060683	18627	0	0
DetectedPulseOut_A	7060683	375	0	0
DisabledIdleSt_A	7060683	6013057	0	0
DisabledNoDetection_A	7060683	6014686	0	0
EnterDebounceSt_A	7060683	494	0	0
EnterDetectSt_A	7060683	440	0	0
EnterStableSt_A	7060683	375	0	0
PulseIsPulse_A	7060683	375	0	0
StayInStableSt	7060683	18229	0	0
gen_high_level_sva.HighLevelEvent_A	7060683	6424588	0	0
gen_not_sticky_sva.StableStDropOut_A	7060683	348	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	932	0	0
T1	13064	2	0	0
T2	654	0	0	0
T5	0	5	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	35	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T33	0	10	0	0
T34	0	13	0	0
T35	0	4	0	0
T47	0	29	0	0
T78	0	25	0	0
T93	0	6	0	0
T112	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	54303	0	0
T1	13064	43	0	0
T2	654	0	0	0
T5	0	248	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	2432	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T33	0	240	0	0
T34	0	1748	0	0
T35	0	154	0	0
T47	0	1683	0	0
T78	0	1132	0	0
T93	0	348	0	0
T112	0	459	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6421305	0	0
T1	13064	12655	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	60	0	0
T22	1314	0	0	0
T23	1021	0	0	0
T31	2019	0	0	0
T34	28277	0	0	0
T36	875	0	0	0
T47	5656	14	0	0
T48	713	0	0	0
T58	15638	0	0	0
T93	17430	0	0	0
T99	0	5	0	0
T103	0	3	0	0
T129	954	0	0	0
T191	0	7	0	0
T277	0	3	0	0
T278	0	5	0	0
T279	0	2	0	0
T280	0	2	0	0
T281	0	3	0	0
T282	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	18627	0	0
T1	13064	80	0	0
T2	654	0	0	0
T5	0	106	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	597	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T33	0	429	0	0
T34	0	429	0	0
T35	0	46	0	0
T70	0	107	0	0
T78	0	674	0	0
T93	0	242	0	0
T112	0	57	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	375	0	0
T1	13064	1	0	0
T2	654	0	0	0
T5	0	2	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	16	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T33	0	5	0	0
T34	0	6	0	0
T35	0	2	0	0
T70	0	2	0	0
T78	0	12	0	0
T93	0	3	0	0
T112	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6013057	0	0
T1	13064	11984	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6014686	0	0
T1	13064	11987	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	494	0	0
T1	13064	1	0	0
T2	654	0	0	0
T5	0	3	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	19	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T33	0	5	0	0
T34	0	7	0	0
T35	0	2	0	0
T47	0	15	0	0
T78	0	13	0	0
T93	0	3	0	0
T112	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	440	0	0
T1	13064	1	0	0
T2	654	0	0	0
T5	0	2	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	16	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T33	0	5	0	0
T34	0	6	0	0
T35	0	2	0	0
T47	0	14	0	0
T78	0	12	0	0
T93	0	3	0	0
T112	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	375	0	0
T1	13064	1	0	0
T2	654	0	0	0
T5	0	2	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	16	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T33	0	5	0	0
T34	0	6	0	0
T35	0	2	0	0
T70	0	2	0	0
T78	0	12	0	0
T93	0	3	0	0
T112	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	375	0	0
T1	13064	1	0	0
T2	654	0	0	0
T5	0	2	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	16	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T33	0	5	0	0
T34	0	6	0	0
T35	0	2	0	0
T70	0	2	0	0
T78	0	12	0	0
T93	0	3	0	0
T112	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	18229	0	0
T1	13064	79	0	0
T2	654	0	0	0
T5	0	103	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	581	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T33	0	424	0	0
T34	0	423	0	0
T35	0	44	0	0
T70	0	105	0	0
T78	0	662	0	0
T93	0	239	0	0
T112	0	54	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	348	0	0
T1	13064	1	0	0
T2	654	0	0	0
T5	0	1	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	16	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T33	0	5	0	0
T34	0	6	0	0
T35	0	2	0	0
T70	0	2	0	0
T78	0	12	0	0
T93	0	3	0	0
T112	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T26
1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T14,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T14,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T14,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T5,T33
1	1	Covered	T1,T14,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T26
0	1	Covered	T14,T26,T45
1	0	Covered	T98,T210,T212

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T33
0	1	Covered	T1,T5,T33
1	0	Covered	T79,T230

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T33
1	-	Covered	T1,T5,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T26
DetectSt	168	Covered	T1,T14,T26
IdleSt	163	Covered	T1,T6,T7
StableSt	191	Covered	T1,T5,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T26
DebounceSt->IdleSt	163	Covered	T219,T214,T267
DetectSt->IdleSt	186	Covered	T14,T26,T45
DetectSt->StableSt	191	Covered	T1,T5,T33
IdleSt->DebounceSt	148	Covered	T1,T14,T26
StableSt->IdleSt	206	Covered	T1,T5,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T14,T26
0	1	Covered	T1,T14,T26
0	0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T26
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T26
IdleSt	0	-	-	-	-	-	-	Covered	T1,T14,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T219,T214,T267
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T26
DetectSt	-	-	-	-	1	-	-	Covered	T14,T26,T45
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T33
DetectSt	-	-	-	-	0	0	-	Covered	T1,T14,T26
StableSt	-	-	-	-	-	-	1	Covered	T1,T5,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T33
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7060683	2878	0	0
CntIncr_A	7060683	101764	0	0
CntNoWrap_A	7060683	6419359	0	0
DetectStDropOut_A	7060683	375	0	0
DetectedOut_A	7060683	83257	0	0
DetectedPulseOut_A	7060683	853	0	0
DisabledIdleSt_A	7060683	5964094	0	0
DisabledNoDetection_A	7060683	5966237	0	0
EnterDebounceSt_A	7060683	1452	0	0
EnterDetectSt_A	7060683	1426	0	0
EnterStableSt_A	7060683	853	0	0
PulseIsPulse_A	7060683	853	0	0
StayInStableSt	7060683	82287	0	0
gen_high_event_sva.HighLevelEvent_A	7060683	6424588	0	0
gen_high_level_sva.HighLevelEvent_A	7060683	6424588	0	0
gen_not_sticky_sva.StableStDropOut_A	7060683	733	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	2878	0	0
T1	13064	30	0	0
T2	654	0	0	0
T5	0	44	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	20	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	26	0	0
T32	0	24	0	0
T33	0	20	0	0
T45	0	50	0	0
T49	0	48	0	0
T69	0	52	0	0
T70	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	101764	0	0
T1	13064	810	0	0
T2	654	0	0	0
T5	0	1298	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	518	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	496	0	0
T32	0	636	0	0
T33	0	620	0	0
T45	0	1429	0	0
T49	0	1799	0	0
T69	0	5460	0	0
T70	0	462	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6419359	0	0
T1	13064	12627	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4801	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	375	0	0
T2	654	0	0	0
T3	642	0	0	0
T14	5222	10	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	13	0	0
T27	5561	0	0	0
T30	1149	0	0	0
T45	0	25	0	0
T49	0	24	0	0
T52	636	0	0	0
T97	0	16	0	0
T98	0	5	0	0
T212	0	10	0	0
T247	0	6	0	0
T268	0	11	0	0
T274	0	19	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	83257	0	0
T1	13064	1544	0	0
T2	654	0	0	0
T5	0	3663	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	882	0	0
T33	0	367	0	0
T69	0	5341	0	0
T70	0	255	0	0
T85	0	54	0	0
T100	0	742	0	0
T122	0	372	0	0
T269	0	630	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	853	0	0
T1	13064	15	0	0
T2	654	0	0	0
T5	0	22	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	12	0	0
T33	0	10	0	0
T69	0	26	0	0
T70	0	6	0	0
T85	0	3	0	0
T100	0	10	0	0
T122	0	6	0	0
T269	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	5964094	0	0
T1	13064	8188	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	2015	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	5966237	0	0
T1	13064	8188	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	2015	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	1452	0	0
T1	13064	15	0	0
T2	654	0	0	0
T5	0	22	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	10	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	13	0	0
T32	0	12	0	0
T33	0	10	0	0
T45	0	25	0	0
T49	0	24	0	0
T69	0	26	0	0
T70	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	1426	0	0
T1	13064	15	0	0
T2	654	0	0	0
T5	0	22	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	10	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	13	0	0
T32	0	12	0	0
T33	0	10	0	0
T45	0	25	0	0
T49	0	24	0	0
T69	0	26	0	0
T70	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	853	0	0
T1	13064	15	0	0
T2	654	0	0	0
T5	0	22	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	12	0	0
T33	0	10	0	0
T69	0	26	0	0
T70	0	6	0	0
T85	0	3	0	0
T100	0	10	0	0
T122	0	6	0	0
T269	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	853	0	0
T1	13064	15	0	0
T2	654	0	0	0
T5	0	22	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	12	0	0
T33	0	10	0	0
T69	0	26	0	0
T70	0	6	0	0
T85	0	3	0	0
T100	0	10	0	0
T122	0	6	0	0
T269	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	82287	0	0
T1	13064	1526	0	0
T2	654	0	0	0
T5	0	3632	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	869	0	0
T33	0	357	0	0
T69	0	5311	0	0
T70	0	248	0	0
T85	0	51	0	0
T100	0	728	0	0
T122	0	363	0	0
T269	0	618	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	733	0	0
T1	13064	12	0	0
T2	654	0	0	0
T5	0	13	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	11	0	0
T33	0	10	0	0
T69	0	22	0	0
T70	0	5	0	0
T85	0	3	0	0
T100	0	6	0	0
T122	0	3	0	0
T269	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T27
1	Covered	T1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T27,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T6,T7	VC_COV_UNR
1	Covered	T1,T27,T5

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T27,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T5
1	0	Covered	T1,T6,T14
1	1	Covered	T1,T27,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T27,T5
0	1	Covered	T78,T59,T191
1	0	Covered	T79,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T27,T5
0	1	Covered	T27,T5,T12
1	0	Covered	T81,T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T27,T5
1	-	Covered	T27,T5,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T27,T5
DetectSt	168	Covered	T1,T27,T5
IdleSt	163	Covered	T1,T6,T7
StableSt	191	Covered	T1,T27,T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T27,T5
DebounceSt->IdleSt	163	Covered	T27,T5,T12
DetectSt->IdleSt	186	Covered	T78,T59,T191
DetectSt->StableSt	191	Covered	T1,T27,T5
IdleSt->DebounceSt	148	Covered	T1,T27,T5
StableSt->IdleSt	206	Covered	T1,T27,T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T27,T5
0	1	Covered	T1,T27,T5
0	0	Excluded	T1,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T27,T5
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T27,T5
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T27,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T5,T12
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T27,T5
DetectSt	-	-	-	-	1	-	-	Covered	T78,T59,T191
DetectSt	-	-	-	-	0	1	-	Covered	T1,T27,T5
DetectSt	-	-	-	-	0	0	-	Covered	T1,T27,T5
StableSt	-	-	-	-	-	-	1	Covered	T27,T5,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T27,T5
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7060683	831	0	0
CntIncr_A	7060683	48819	0	0
CntNoWrap_A	7060683	6421406	0	0
DetectStDropOut_A	7060683	51	0	0
DetectedOut_A	7060683	16408	0	0
DetectedPulseOut_A	7060683	338	0	0
DisabledIdleSt_A	7060683	6015814	0	0
DisabledNoDetection_A	7060683	6017465	0	0
EnterDebounceSt_A	7060683	439	0	0
EnterDetectSt_A	7060683	392	0	0
EnterStableSt_A	7060683	338	0	0
PulseIsPulse_A	7060683	338	0	0
StayInStableSt	7060683	16030	0	0
gen_high_level_sva.HighLevelEvent_A	7060683	6424588	0	0
gen_not_sticky_sva.StableStDropOut_A	7060683	293	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	831	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	15	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	14	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T27	0	11	0	0
T32	0	2	0	0
T34	0	8	0	0
T35	0	5	0	0
T69	0	6	0	0
T93	0	6	0	0
T94	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	48819	0	0
T1	13064	122	0	0
T2	654	0	0	0
T5	0	493	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	895	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T27	0	604	0	0
T32	0	42	0	0
T34	0	1236	0	0
T35	0	255	0	0
T69	0	651	0	0
T93	0	483	0	0
T94	0	266	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6421406	0	0
T1	13064	12653	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	51	0	0
T59	0	2	0	0
T63	498	0	0	0
T64	497	0	0	0
T70	17519	0	0	0
T78	24663	1	0	0
T79	0	1	0	0
T99	0	4	0	0
T111	502	0	0	0
T112	15187	0	0	0
T122	12120	0	0	0
T167	0	1	0	0
T191	0	5	0	0
T269	17239	0	0	0
T278	0	6	0	0
T280	0	2	0	0
T283	0	8	0	0
T284	0	8	0	0
T285	512	0	0	0
T286	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	16408	0	0
T1	13064	121	0	0
T2	654	0	0	0
T5	0	651	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	273	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T27	0	62	0	0
T32	0	53	0	0
T34	0	66	0	0
T35	0	8	0	0
T69	0	206	0	0
T93	0	108	0	0
T94	0	188	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	338	0	0
T1	13064	2	0	0
T2	654	0	0	0
T5	0	7	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	6	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T27	0	5	0	0
T32	0	1	0	0
T34	0	4	0	0
T35	0	2	0	0
T69	0	3	0	0
T93	0	3	0	0
T94	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6015814	0	0
T1	13064	11116	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6017465	0	0
T1	13064	11117	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	439	0	0
T1	13064	2	0	0
T2	654	0	0	0
T5	0	8	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	8	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T27	0	6	0	0
T32	0	1	0	0
T34	0	4	0	0
T35	0	3	0	0
T69	0	3	0	0
T93	0	3	0	0
T94	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	392	0	0
T1	13064	2	0	0
T2	654	0	0	0
T5	0	7	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	6	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T27	0	5	0	0
T32	0	1	0	0
T34	0	4	0	0
T35	0	2	0	0
T69	0	3	0	0
T93	0	3	0	0
T94	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	338	0	0
T1	13064	2	0	0
T2	654	0	0	0
T5	0	7	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	6	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T27	0	5	0	0
T32	0	1	0	0
T34	0	4	0	0
T35	0	2	0	0
T69	0	3	0	0
T93	0	3	0	0
T94	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	338	0	0
T1	13064	2	0	0
T2	654	0	0	0
T5	0	7	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	6	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T27	0	5	0	0
T32	0	1	0	0
T34	0	4	0	0
T35	0	2	0	0
T69	0	3	0	0
T93	0	3	0	0
T94	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	16030	0	0
T1	13064	117	0	0
T2	654	0	0	0
T5	0	644	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	267	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T27	0	57	0	0
T32	0	52	0	0
T34	0	62	0	0
T35	0	6	0	0
T69	0	203	0	0
T93	0	105	0	0
T94	0	186	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	293	0	0
T3	642	0	0	0
T5	0	7	0	0
T8	604	0	0	0
T12	0	6	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T27	5561	5	0	0
T30	1149	0	0	0
T32	0	1	0	0
T34	0	4	0	0
T35	0	2	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T69	0	3	0	0
T93	0	3	0	0
T94	0	2	0	0
T112	0	1	0	0