Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T26
1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T14,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T14,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T14,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T5,T33
1	1	Covered	T1,T14,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T26
0	1	Covered	T14,T26,T5
1	0	Covered	T5,T122,T98

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T33,T32
0	1	Covered	T1,T33,T32
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T33,T32
1	-	Covered	T1,T33,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T26
DetectSt	168	Covered	T1,T14,T26
IdleSt	163	Covered	T1,T6,T7
StableSt	191	Covered	T1,T33,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T26
DebounceSt->IdleSt	163	Covered	T219,T214,T267
DetectSt->IdleSt	186	Covered	T14,T26,T5
DetectSt->StableSt	191	Covered	T1,T33,T32
IdleSt->DebounceSt	148	Covered	T1,T14,T26
StableSt->IdleSt	206	Covered	T1,T33,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T14,T26
0	1	Covered	T1,T14,T26
0	0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T26
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T26
IdleSt	0	-	-	-	-	-	-	Covered	T1,T14,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T219,T214,T267
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T26
DetectSt	-	-	-	-	1	-	-	Covered	T14,T26,T5
DetectSt	-	-	-	-	0	1	-	Covered	T1,T33,T32
DetectSt	-	-	-	-	0	0	-	Covered	T1,T14,T26
StableSt	-	-	-	-	-	-	1	Covered	T1,T33,T32
StableSt	-	-	-	-	-	-	0	Covered	T1,T33,T32
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7060683	2878	0	0
CntIncr_A	7060683	108599	0	0
CntNoWrap_A	7060683	6419359	0	0
DetectStDropOut_A	7060683	401	0	0
DetectedOut_A	7060683	54000	0	0
DetectedPulseOut_A	7060683	692	0	0
DisabledIdleSt_A	7060683	5991251	0	0
DisabledNoDetection_A	7060683	5993434	0	0
EnterDebounceSt_A	7060683	1465	0	0
EnterDetectSt_A	7060683	1414	0	0
EnterStableSt_A	7060683	692	0	0
PulseIsPulse_A	7060683	692	0	0
StayInStableSt	7060683	53231	0	0
gen_high_event_sva.HighLevelEvent_A	7060683	6424588	0	0
gen_high_level_sva.HighLevelEvent_A	7060683	6424588	0	0
gen_not_sticky_sva.StableStDropOut_A	7060683	614	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	2878	0	0
T1	13064	20	0	0
T2	654	0	0	0
T5	0	59	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	22	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	16	0	0
T32	0	12	0	0
T33	0	42	0	0
T45	0	56	0	0
T49	0	60	0	0
T69	0	48	0	0
T70	0	56	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	108599	0	0
T1	13064	320	0	0
T2	654	0	0	0
T5	0	2452	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	566	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	306	0	0
T32	0	348	0	0
T33	0	903	0	0
T45	0	1590	0	0
T49	0	2251	0	0
T69	0	5184	0	0
T70	0	1848	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6419359	0	0
T1	13064	12637	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4799	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	401	0	0
T2	654	0	0	0
T3	642	0	0	0
T5	0	8	0	0
T14	5222	11	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	8	0	0
T27	5561	0	0	0
T30	1149	0	0	0
T45	0	28	0	0
T49	0	30	0	0
T52	636	0	0	0
T97	0	14	0	0
T98	0	8	0	0
T122	0	4	0	0
T268	0	13	0	0
T270	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	54000	0	0
T1	13064	634	0	0
T2	654	0	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	144	0	0
T33	0	2012	0	0
T69	0	5222	0	0
T70	0	2169	0	0
T85	0	1611	0	0
T100	0	1563	0	0
T219	0	964	0	0
T269	0	63	0	0
T271	0	158	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	692	0	0
T1	13064	10	0	0
T2	654	0	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	6	0	0
T33	0	21	0	0
T69	0	24	0	0
T70	0	28	0	0
T85	0	23	0	0
T100	0	14	0	0
T219	0	5	0	0
T269	0	7	0	0
T271	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	5991251	0	0
T1	13064	9325	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	2015	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	5993434	0	0
T1	13064	9327	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	2015	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	1465	0	0
T1	13064	10	0	0
T2	654	0	0	0
T5	0	30	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	11	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	8	0	0
T32	0	6	0	0
T33	0	21	0	0
T45	0	28	0	0
T49	0	30	0	0
T69	0	24	0	0
T70	0	28	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	1414	0	0
T1	13064	10	0	0
T2	654	0	0	0
T5	0	30	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	11	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	8	0	0
T32	0	6	0	0
T33	0	21	0	0
T45	0	28	0	0
T49	0	30	0	0
T69	0	24	0	0
T70	0	28	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	692	0	0
T1	13064	10	0	0
T2	654	0	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	6	0	0
T33	0	21	0	0
T69	0	24	0	0
T70	0	28	0	0
T85	0	23	0	0
T100	0	14	0	0
T219	0	5	0	0
T269	0	7	0	0
T271	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	692	0	0
T1	13064	10	0	0
T2	654	0	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	6	0	0
T33	0	21	0	0
T69	0	24	0	0
T70	0	28	0	0
T85	0	23	0	0
T100	0	14	0	0
T219	0	5	0	0
T269	0	7	0	0
T271	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	53231	0	0
T1	13064	623	0	0
T2	654	0	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	138	0	0
T33	0	1988	0	0
T69	0	5195	0	0
T70	0	2137	0	0
T85	0	1588	0	0
T100	0	1545	0	0
T219	0	959	0	0
T269	0	56	0	0
T271	0	133	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	614	0	0
T1	13064	9	0	0
T2	654	0	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T32	0	6	0	0
T33	0	18	0	0
T69	0	21	0	0
T70	0	24	0	0
T85	0	23	0	0
T100	0	10	0	0
T219	0	5	0	0
T269	0	6	0	0
T271	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T27
1	Covered	T1,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T27,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T6,T7	VC_COV_UNR
1	Covered	T1,T27,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T12,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T12
1	0	Covered	T1,T6,T14
1	1	Covered	T1,T27,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T33
0	1	Covered	T35,T112,T59
1	0	Covered	T79,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T33
0	1	Covered	T1,T12,T33
1	0	Covered	T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T12,T33
1	-	Covered	T1,T12,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T27,T12
DetectSt	168	Covered	T1,T12,T33
IdleSt	163	Covered	T1,T6,T7
StableSt	191	Covered	T1,T12,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T33
DebounceSt->IdleSt	163	Covered	T27,T12,T35
DetectSt->IdleSt	186	Covered	T35,T112,T59
DetectSt->StableSt	191	Covered	T1,T12,T33
IdleSt->DebounceSt	148	Covered	T1,T27,T12
StableSt->IdleSt	206	Covered	T1,T12,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T27,T12
0	1	Covered	T1,T27,T12
0	0	Excluded	T1,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T33
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T27,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T12,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T27,T12
DetectSt	-	-	-	-	1	-	-	Covered	T35,T112,T59
DetectSt	-	-	-	-	0	1	-	Covered	T1,T12,T33
DetectSt	-	-	-	-	0	0	-	Covered	T1,T12,T33
StableSt	-	-	-	-	-	-	1	Covered	T1,T12,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T12,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7060683	777	0	0
CntIncr_A	7060683	42977	0	0
CntNoWrap_A	7060683	6421460	0	0
DetectStDropOut_A	7060683	71	0	0
DetectedOut_A	7060683	12916	0	0
DetectedPulseOut_A	7060683	290	0	0
DisabledIdleSt_A	7060683	6027747	0	0
DisabledNoDetection_A	7060683	6029400	0	0
EnterDebounceSt_A	7060683	412	0	0
EnterDetectSt_A	7060683	365	0	0
EnterStableSt_A	7060683	290	0	0
PulseIsPulse_A	7060683	290	0	0
StayInStableSt	7060683	12611	0	0
gen_high_level_sva.HighLevelEvent_A	7060683	6424588	0	0
gen_not_sticky_sva.StableStDropOut_A	7060683	271	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	777	0	0
T1	13064	2	0	0
T2	654	0	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	9	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T27	0	1	0	0
T33	0	6	0	0
T34	0	4	0	0
T35	0	24	0	0
T69	0	6	0	0
T78	0	3	0	0
T93	0	2	0	0
T94	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	42977	0	0
T1	13064	77	0	0
T2	654	0	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	664	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T27	0	69	0	0
T33	0	207	0	0
T34	0	568	0	0
T35	0	1241	0	0
T69	0	684	0	0
T78	0	183	0	0
T93	0	192	0	0
T94	0	186	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6421460	0	0
T1	13064	12655	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	71	0	0
T32	9888	0	0	0
T35	9224	11	0	0
T59	0	2	0	0
T68	648	0	0	0
T69	35631	0	0	0
T78	24663	0	0	0
T94	19311	0	0	0
T108	0	16	0	0
T109	464	0	0	0
T110	525	0	0	0
T111	502	0	0	0
T112	15187	6	0	0
T172	0	3	0	0
T191	0	4	0	0
T200	0	4	0	0
T287	0	8	0	0
T288	0	4	0	0
T289	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	12916	0	0
T1	13064	46	0	0
T2	654	0	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	43	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T33	0	194	0	0
T34	0	84	0	0
T69	0	169	0	0
T70	0	390	0	0
T78	0	25	0	0
T93	0	5	0	0
T94	0	41	0	0
T191	0	220	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	290	0	0
T1	13064	1	0	0
T2	654	0	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	4	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T69	0	3	0	0
T70	0	4	0	0
T78	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T191	0	15	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6027747	0	0
T1	13064	12024	0	0
T2	654	253	0	0
T6	36894	35291	0	0
T7	496	95	0	0
T13	503	102	0	0
T14	5222	4821	0	0
T15	419	18	0	0
T16	490	89	0	0
T17	505	104	0	0
T18	55144	54743	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6029400	0	0
T1	13064	12027	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	412	0	0
T1	13064	1	0	0
T2	654	0	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	5	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T27	0	1	0	0
T33	0	3	0	0
T34	0	2	0	0
T35	0	13	0	0
T69	0	3	0	0
T78	0	2	0	0
T93	0	1	0	0
T94	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	365	0	0
T1	13064	1	0	0
T2	654	0	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	4	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T35	0	11	0	0
T69	0	3	0	0
T78	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T112	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	290	0	0
T1	13064	1	0	0
T2	654	0	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	4	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T69	0	3	0	0
T70	0	4	0	0
T78	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T191	0	15	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	290	0	0
T1	13064	1	0	0
T2	654	0	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	4	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T69	0	3	0	0
T70	0	4	0	0
T78	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T191	0	15	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	12611	0	0
T1	13064	45	0	0
T2	654	0	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	39	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T33	0	191	0	0
T34	0	82	0	0
T69	0	163	0	0
T70	0	386	0	0
T78	0	24	0	0
T93	0	4	0	0
T94	0	40	0	0
T191	0	205	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	6424588	0	0
T1	13064	12661	0	0
T2	654	254	0	0
T6	36894	35294	0	0
T7	496	96	0	0
T13	503	103	0	0
T14	5222	4822	0	0
T15	419	19	0	0
T16	490	90	0	0
T17	505	105	0	0
T18	55144	54744	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7060683	271	0	0
T1	13064	1	0	0
T2	654	0	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	4	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T70	0	4	0	0
T78	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T191	0	15	0	0
T277	0	11	0	0