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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.91 99.37 96.46 100.00 98.08 98.78 99.71 92.97


Total test records in report: 913
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T795 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.584690801 Aug 09 05:11:21 PM PDT 24 Aug 09 05:11:27 PM PDT 24 2011679954 ps
T24 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3157584849 Aug 09 05:10:59 PM PDT 24 Aug 09 05:13:34 PM PDT 24 65010814389 ps
T25 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.1988499382 Aug 09 05:11:12 PM PDT 24 Aug 09 05:11:15 PM PDT 24 2092151026 ps
T796 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3320942715 Aug 09 05:11:33 PM PDT 24 Aug 09 05:11:37 PM PDT 24 2016500314 ps
T797 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3619534110 Aug 09 05:11:35 PM PDT 24 Aug 09 05:11:42 PM PDT 24 2013591581 ps
T798 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2164819801 Aug 09 05:11:33 PM PDT 24 Aug 09 05:11:36 PM PDT 24 2024580199 ps
T277 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2166993504 Aug 09 05:11:20 PM PDT 24 Aug 09 05:11:23 PM PDT 24 2145334710 ps
T799 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2608705483 Aug 09 05:11:41 PM PDT 24 Aug 09 05:11:43 PM PDT 24 2023131848 ps
T26 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2632396148 Aug 09 05:11:35 PM PDT 24 Aug 09 05:11:37 PM PDT 24 2115985182 ps
T278 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3502406903 Aug 09 05:11:29 PM PDT 24 Aug 09 05:11:37 PM PDT 24 2128527087 ps
T27 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3931010121 Aug 09 05:11:12 PM PDT 24 Aug 09 05:11:28 PM PDT 24 22424831563 ps
T28 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3631000596 Aug 09 05:10:57 PM PDT 24 Aug 09 05:11:32 PM PDT 24 42750549409 ps
T800 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2593493162 Aug 09 05:11:34 PM PDT 24 Aug 09 05:11:39 PM PDT 24 2010899827 ps
T801 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.3327952590 Aug 09 05:11:39 PM PDT 24 Aug 09 05:11:45 PM PDT 24 2010598099 ps
T17 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2952355931 Aug 09 05:11:31 PM PDT 24 Aug 09 05:11:53 PM PDT 24 8126872366 ps
T283 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3514917939 Aug 09 05:11:06 PM PDT 24 Aug 09 05:11:13 PM PDT 24 2075494694 ps
T288 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.4063915426 Aug 09 05:10:59 PM PDT 24 Aug 09 05:11:05 PM PDT 24 2046565370 ps
T802 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.486231448 Aug 09 05:11:42 PM PDT 24 Aug 09 05:11:45 PM PDT 24 2019680580 ps
T281 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3932458814 Aug 09 05:11:12 PM PDT 24 Aug 09 05:12:05 PM PDT 24 22235138801 ps
T326 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1865384381 Aug 09 05:11:20 PM PDT 24 Aug 09 05:11:24 PM PDT 24 2045196293 ps
T803 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.4286408346 Aug 09 05:11:27 PM PDT 24 Aug 09 05:11:29 PM PDT 24 2043335729 ps
T354 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1626059193 Aug 09 05:11:33 PM PDT 24 Aug 09 05:12:28 PM PDT 24 22234662504 ps
T314 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3452932092 Aug 09 05:11:13 PM PDT 24 Aug 09 05:11:15 PM PDT 24 2084733039 ps
T315 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3559306123 Aug 09 05:11:07 PM PDT 24 Aug 09 05:11:35 PM PDT 24 34791307664 ps
T804 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.820751973 Aug 09 05:11:37 PM PDT 24 Aug 09 05:11:38 PM PDT 24 2062772418 ps
T805 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.2687311168 Aug 09 05:11:36 PM PDT 24 Aug 09 05:11:42 PM PDT 24 2013792420 ps
T18 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2067394128 Aug 09 05:11:29 PM PDT 24 Aug 09 05:12:02 PM PDT 24 10438704091 ps
T806 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2869001128 Aug 09 05:11:06 PM PDT 24 Aug 09 05:11:09 PM PDT 24 2069529921 ps
T286 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.342552454 Aug 09 05:11:15 PM PDT 24 Aug 09 05:11:20 PM PDT 24 2066687317 ps
T807 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3659472409 Aug 09 05:11:04 PM PDT 24 Aug 09 05:11:07 PM PDT 24 2121632495 ps
T355 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.1082836818 Aug 09 05:11:06 PM PDT 24 Aug 09 05:12:05 PM PDT 24 22216951822 ps
T808 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1097673531 Aug 09 05:11:06 PM PDT 24 Aug 09 05:11:07 PM PDT 24 2103831806 ps
T809 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3965699473 Aug 09 05:11:23 PM PDT 24 Aug 09 05:11:25 PM PDT 24 2151065380 ps
T316 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1535845734 Aug 09 05:11:09 PM PDT 24 Aug 09 05:12:25 PM PDT 24 70260809433 ps
T810 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2411268296 Aug 09 05:11:21 PM PDT 24 Aug 09 05:11:26 PM PDT 24 2014182449 ps
T811 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2574822856 Aug 09 05:11:31 PM PDT 24 Aug 09 05:11:32 PM PDT 24 2071964092 ps
T812 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.3632328611 Aug 09 05:11:33 PM PDT 24 Aug 09 05:11:39 PM PDT 24 2012146091 ps
T19 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.581585690 Aug 09 05:11:29 PM PDT 24 Aug 09 05:11:35 PM PDT 24 2044448564 ps
T317 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3805347921 Aug 09 05:11:01 PM PDT 24 Aug 09 05:11:11 PM PDT 24 2613306666 ps
T327 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2537462534 Aug 09 05:11:29 PM PDT 24 Aug 09 05:11:35 PM PDT 24 8251982802 ps
T328 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2876494543 Aug 09 05:11:12 PM PDT 24 Aug 09 05:11:15 PM PDT 24 7873455740 ps
T329 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.3073488668 Aug 09 05:11:20 PM PDT 24 Aug 09 05:11:30 PM PDT 24 8064680036 ps
T330 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1629191024 Aug 09 05:11:05 PM PDT 24 Aug 09 05:11:11 PM PDT 24 2064428751 ps
T331 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2901884297 Aug 09 05:11:19 PM PDT 24 Aug 09 05:11:23 PM PDT 24 2035403067 ps
T813 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.923772283 Aug 09 05:11:22 PM PDT 24 Aug 09 05:11:27 PM PDT 24 7064881290 ps
T290 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.966219865 Aug 09 05:11:29 PM PDT 24 Aug 09 05:11:35 PM PDT 24 2074343527 ps
T350 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1456579740 Aug 09 05:10:59 PM PDT 24 Aug 09 05:12:52 PM PDT 24 42362461076 ps
T287 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3138819517 Aug 09 05:11:06 PM PDT 24 Aug 09 05:11:10 PM PDT 24 2048870904 ps
T814 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1012875424 Aug 09 05:11:28 PM PDT 24 Aug 09 05:12:01 PM PDT 24 8007321303 ps
T815 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.881535455 Aug 09 05:11:34 PM PDT 24 Aug 09 05:11:40 PM PDT 24 2042790398 ps
T816 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2229869393 Aug 09 05:11:00 PM PDT 24 Aug 09 05:11:02 PM PDT 24 2079685716 ps
T817 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.250758099 Aug 09 05:11:21 PM PDT 24 Aug 09 05:12:15 PM PDT 24 22220846578 ps
T818 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3776725058 Aug 09 05:11:35 PM PDT 24 Aug 09 05:11:41 PM PDT 24 2013714428 ps
T318 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.1189692025 Aug 09 05:11:23 PM PDT 24 Aug 09 05:11:27 PM PDT 24 2064206748 ps
T819 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.438407056 Aug 09 05:10:57 PM PDT 24 Aug 09 05:11:00 PM PDT 24 4056683948 ps
T820 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1120908960 Aug 09 05:11:35 PM PDT 24 Aug 09 05:11:40 PM PDT 24 2012819278 ps
T284 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2026201293 Aug 09 05:11:00 PM PDT 24 Aug 09 05:11:07 PM PDT 24 2030527135 ps
T821 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.6763169 Aug 09 05:11:18 PM PDT 24 Aug 09 05:11:24 PM PDT 24 2033214413 ps
T822 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3023662826 Aug 09 05:11:22 PM PDT 24 Aug 09 05:11:24 PM PDT 24 2041055078 ps
T352 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3712992672 Aug 09 05:11:13 PM PDT 24 Aug 09 05:11:18 PM PDT 24 23733053464 ps
T823 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3238487302 Aug 09 05:11:13 PM PDT 24 Aug 09 05:11:16 PM PDT 24 2081777619 ps
T289 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1669519258 Aug 09 05:10:58 PM PDT 24 Aug 09 05:11:02 PM PDT 24 2581824736 ps
T824 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.4236036786 Aug 09 05:11:33 PM PDT 24 Aug 09 05:11:39 PM PDT 24 2011398435 ps
T825 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3302693482 Aug 09 05:11:38 PM PDT 24 Aug 09 05:11:44 PM PDT 24 2010947303 ps
T826 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3910503804 Aug 09 05:11:34 PM PDT 24 Aug 09 05:11:38 PM PDT 24 2039911946 ps
T827 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.292662890 Aug 09 05:11:25 PM PDT 24 Aug 09 05:11:27 PM PDT 24 2246536645 ps
T828 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3668912229 Aug 09 05:11:35 PM PDT 24 Aug 09 05:11:39 PM PDT 24 2141389958 ps
T829 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3659655845 Aug 09 05:11:33 PM PDT 24 Aug 09 05:11:39 PM PDT 24 2011815018 ps
T830 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2998958094 Aug 09 05:10:58 PM PDT 24 Aug 09 05:11:00 PM PDT 24 2105663419 ps
T831 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1747874522 Aug 09 05:11:05 PM PDT 24 Aug 09 05:11:15 PM PDT 24 4931441099 ps
T832 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2249147847 Aug 09 05:11:23 PM PDT 24 Aug 09 05:11:29 PM PDT 24 2079374778 ps
T833 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.869441936 Aug 09 05:11:20 PM PDT 24 Aug 09 05:11:23 PM PDT 24 2184583787 ps
T319 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3021334759 Aug 09 05:11:06 PM PDT 24 Aug 09 05:11:12 PM PDT 24 3121427778 ps
T834 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1753372887 Aug 09 05:11:38 PM PDT 24 Aug 09 05:11:41 PM PDT 24 2038892219 ps
T351 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.789485615 Aug 09 05:11:07 PM PDT 24 Aug 09 05:12:55 PM PDT 24 42390721036 ps
T835 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.92848951 Aug 09 05:11:33 PM PDT 24 Aug 09 05:11:34 PM PDT 24 2139212264 ps
T836 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.1668595955 Aug 09 05:11:12 PM PDT 24 Aug 09 05:11:28 PM PDT 24 7169948326 ps
T837 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2536161384 Aug 09 05:11:05 PM PDT 24 Aug 09 05:11:07 PM PDT 24 2044885044 ps
T838 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.856361472 Aug 09 05:11:24 PM PDT 24 Aug 09 05:11:39 PM PDT 24 22263545983 ps
T839 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2275411347 Aug 09 05:11:39 PM PDT 24 Aug 09 05:11:42 PM PDT 24 2026301931 ps
T840 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2486857377 Aug 09 05:11:34 PM PDT 24 Aug 09 05:11:38 PM PDT 24 2017412813 ps
T841 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.696445883 Aug 09 05:11:15 PM PDT 24 Aug 09 05:11:17 PM PDT 24 2049396283 ps
T320 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3018865701 Aug 09 05:10:58 PM PDT 24 Aug 09 05:11:01 PM PDT 24 2050443328 ps
T321 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.600289903 Aug 09 05:11:06 PM PDT 24 Aug 09 05:11:10 PM PDT 24 2028899766 ps
T842 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2079131918 Aug 09 05:11:21 PM PDT 24 Aug 09 05:11:26 PM PDT 24 4595879161 ps
T843 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1096621655 Aug 09 05:11:20 PM PDT 24 Aug 09 05:11:21 PM PDT 24 2072362059 ps
T285 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1959240562 Aug 09 05:11:14 PM PDT 24 Aug 09 05:11:18 PM PDT 24 2148275837 ps
T844 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1332021149 Aug 09 05:11:43 PM PDT 24 Aug 09 05:11:45 PM PDT 24 2026012950 ps
T845 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.976245747 Aug 09 05:11:20 PM PDT 24 Aug 09 05:11:23 PM PDT 24 2294059243 ps
T846 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.340131234 Aug 09 05:10:56 PM PDT 24 Aug 09 05:11:02 PM PDT 24 7930308617 ps
T847 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2981394301 Aug 09 05:11:30 PM PDT 24 Aug 09 05:11:34 PM PDT 24 2110822622 ps
T848 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3524131472 Aug 09 05:11:14 PM PDT 24 Aug 09 05:12:13 PM PDT 24 42500232788 ps
T322 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.3065083207 Aug 09 05:11:09 PM PDT 24 Aug 09 05:11:15 PM PDT 24 4045161594 ps
T323 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.81347797 Aug 09 05:11:11 PM PDT 24 Aug 09 05:11:15 PM PDT 24 2033368463 ps
T849 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.255222667 Aug 09 05:11:50 PM PDT 24 Aug 09 05:11:53 PM PDT 24 2020472154 ps
T850 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2393209216 Aug 09 05:11:11 PM PDT 24 Aug 09 05:11:15 PM PDT 24 2375114791 ps
T851 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.3570299454 Aug 09 05:11:15 PM PDT 24 Aug 09 05:11:22 PM PDT 24 8553240357 ps
T852 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.285451131 Aug 09 05:11:21 PM PDT 24 Aug 09 05:11:24 PM PDT 24 2056228344 ps
T853 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.1497973018 Aug 09 05:11:34 PM PDT 24 Aug 09 05:11:36 PM PDT 24 2032679762 ps
T854 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1914116139 Aug 09 05:11:21 PM PDT 24 Aug 09 05:12:13 PM PDT 24 22221612721 ps
T855 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.192337467 Aug 09 05:11:15 PM PDT 24 Aug 09 05:11:17 PM PDT 24 2039355479 ps
T856 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.2509013066 Aug 09 05:11:04 PM PDT 24 Aug 09 05:11:07 PM PDT 24 2019172059 ps
T324 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3464355640 Aug 09 05:11:27 PM PDT 24 Aug 09 05:11:29 PM PDT 24 2103725097 ps
T857 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.985033209 Aug 09 05:11:27 PM PDT 24 Aug 09 05:11:43 PM PDT 24 22248192817 ps
T325 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.238814513 Aug 09 05:11:05 PM PDT 24 Aug 09 05:11:10 PM PDT 24 2996911827 ps
T858 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3053884843 Aug 09 05:11:23 PM PDT 24 Aug 09 05:12:53 PM PDT 24 42449067651 ps
T859 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2730633655 Aug 09 05:11:21 PM PDT 24 Aug 09 05:11:25 PM PDT 24 2025532282 ps
T860 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.361367638 Aug 09 05:11:06 PM PDT 24 Aug 09 05:11:08 PM PDT 24 2039259573 ps
T861 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3539467114 Aug 09 05:11:28 PM PDT 24 Aug 09 05:11:33 PM PDT 24 2014797247 ps
T862 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1451037267 Aug 09 05:11:15 PM PDT 24 Aug 09 05:11:20 PM PDT 24 2092568431 ps
T863 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.750568442 Aug 09 05:10:58 PM PDT 24 Aug 09 05:11:04 PM PDT 24 2012590826 ps
T864 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1621087698 Aug 09 05:11:23 PM PDT 24 Aug 09 05:11:25 PM PDT 24 2430884842 ps
T865 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.832717967 Aug 09 05:11:15 PM PDT 24 Aug 09 05:11:16 PM PDT 24 2072332334 ps
T866 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1463278190 Aug 09 05:11:41 PM PDT 24 Aug 09 05:11:47 PM PDT 24 2012813713 ps
T867 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.657151769 Aug 09 05:11:14 PM PDT 24 Aug 09 05:11:22 PM PDT 24 2044598300 ps
T868 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3799345630 Aug 09 05:11:19 PM PDT 24 Aug 09 05:11:31 PM PDT 24 22500339878 ps
T869 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2523809776 Aug 09 05:11:22 PM PDT 24 Aug 09 05:11:56 PM PDT 24 9511575768 ps
T870 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3977723214 Aug 09 05:11:15 PM PDT 24 Aug 09 05:11:19 PM PDT 24 4909182118 ps
T871 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.465590222 Aug 09 05:11:19 PM PDT 24 Aug 09 05:11:25 PM PDT 24 2050032021 ps
T872 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1741113512 Aug 09 05:11:42 PM PDT 24 Aug 09 05:11:43 PM PDT 24 2043152003 ps
T873 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2565186118 Aug 09 05:11:33 PM PDT 24 Aug 09 05:11:36 PM PDT 24 5299138475 ps
T874 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.233672815 Aug 09 05:11:30 PM PDT 24 Aug 09 05:12:29 PM PDT 24 22229795827 ps
T875 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.911454118 Aug 09 05:11:34 PM PDT 24 Aug 09 05:11:39 PM PDT 24 2011871444 ps
T876 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.4190546785 Aug 09 05:10:58 PM PDT 24 Aug 09 05:11:02 PM PDT 24 2041971111 ps
T877 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1021230711 Aug 09 05:11:37 PM PDT 24 Aug 09 05:11:43 PM PDT 24 2016091633 ps
T878 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3310044875 Aug 09 05:11:19 PM PDT 24 Aug 09 05:11:22 PM PDT 24 2096790009 ps
T879 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.4054669480 Aug 09 05:11:27 PM PDT 24 Aug 09 05:11:30 PM PDT 24 2051168317 ps
T880 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.1680372092 Aug 09 05:11:13 PM PDT 24 Aug 09 05:11:15 PM PDT 24 2049687123 ps
T881 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.917695639 Aug 09 05:11:27 PM PDT 24 Aug 09 05:11:29 PM PDT 24 2343219552 ps
T882 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1040709822 Aug 09 05:11:29 PM PDT 24 Aug 09 05:11:33 PM PDT 24 2165126284 ps
T883 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.624118599 Aug 09 05:11:12 PM PDT 24 Aug 09 05:11:41 PM PDT 24 42550428038 ps
T884 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.592364556 Aug 09 05:11:20 PM PDT 24 Aug 09 05:11:24 PM PDT 24 2107994900 ps
T885 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.495689471 Aug 09 05:11:30 PM PDT 24 Aug 09 05:12:17 PM PDT 24 22178308723 ps
T332 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1433943230 Aug 09 05:11:04 PM PDT 24 Aug 09 05:11:15 PM PDT 24 4028940776 ps
T886 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3118136116 Aug 09 05:11:15 PM PDT 24 Aug 09 05:11:18 PM PDT 24 2085338712 ps
T887 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.3592197119 Aug 09 05:11:14 PM PDT 24 Aug 09 05:11:20 PM PDT 24 2013135316 ps
T888 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2902593335 Aug 09 05:10:58 PM PDT 24 Aug 09 05:11:11 PM PDT 24 22525903432 ps
T889 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3761817768 Aug 09 05:11:19 PM PDT 24 Aug 09 05:11:21 PM PDT 24 2046052596 ps
T890 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3164647008 Aug 09 05:11:40 PM PDT 24 Aug 09 05:11:43 PM PDT 24 2039030849 ps
T891 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3164389247 Aug 09 05:10:59 PM PDT 24 Aug 09 05:11:03 PM PDT 24 2546582088 ps
T892 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3850737796 Aug 09 05:11:05 PM PDT 24 Aug 09 05:11:10 PM PDT 24 2693551728 ps
T893 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2884367581 Aug 09 05:11:04 PM PDT 24 Aug 09 05:11:22 PM PDT 24 4767736384 ps
T894 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.3517097424 Aug 09 05:11:36 PM PDT 24 Aug 09 05:11:41 PM PDT 24 2012440757 ps
T895 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.361000516 Aug 09 05:11:02 PM PDT 24 Aug 09 05:11:07 PM PDT 24 6065508830 ps
T896 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2142169530 Aug 09 05:11:20 PM PDT 24 Aug 09 05:11:30 PM PDT 24 10493998265 ps
T897 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3800749738 Aug 09 05:11:31 PM PDT 24 Aug 09 05:11:37 PM PDT 24 2013772044 ps
T898 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2662518785 Aug 09 05:10:58 PM PDT 24 Aug 09 05:11:08 PM PDT 24 10494770508 ps
T899 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1739464107 Aug 09 05:11:04 PM PDT 24 Aug 09 05:11:16 PM PDT 24 4016610779 ps
T900 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.188570845 Aug 09 05:11:15 PM PDT 24 Aug 09 05:11:21 PM PDT 24 2010023933 ps
T901 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2238903991 Aug 09 05:11:19 PM PDT 24 Aug 09 05:11:21 PM PDT 24 2116691892 ps
T902 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2108400968 Aug 09 05:11:20 PM PDT 24 Aug 09 05:11:26 PM PDT 24 2136173584 ps
T903 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.568598861 Aug 09 05:11:27 PM PDT 24 Aug 09 05:11:31 PM PDT 24 2066487371 ps
T904 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1477660201 Aug 09 05:11:14 PM PDT 24 Aug 09 05:11:28 PM PDT 24 9786050560 ps
T905 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.4224209181 Aug 09 05:11:14 PM PDT 24 Aug 09 05:11:23 PM PDT 24 2131840896 ps
T906 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3174386574 Aug 09 05:11:35 PM PDT 24 Aug 09 05:11:41 PM PDT 24 2013310298 ps
T907 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1353529146 Aug 09 05:11:36 PM PDT 24 Aug 09 05:11:52 PM PDT 24 4875924856 ps
T908 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.3895065988 Aug 09 05:11:12 PM PDT 24 Aug 09 05:11:19 PM PDT 24 2082428855 ps
T909 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.211609578 Aug 09 05:10:57 PM PDT 24 Aug 09 05:12:31 PM PDT 24 39055740396 ps
T353 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3346892785 Aug 09 05:11:28 PM PDT 24 Aug 09 05:11:58 PM PDT 24 22294760877 ps
T910 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2858024050 Aug 09 05:11:30 PM PDT 24 Aug 09 05:11:33 PM PDT 24 2070994511 ps
T911 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.715527182 Aug 09 05:11:04 PM PDT 24 Aug 09 05:11:44 PM PDT 24 64949914132 ps
T912 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1325975342 Aug 09 05:11:02 PM PDT 24 Aug 09 05:11:03 PM PDT 24 2037726593 ps
T913 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.1052554959 Aug 09 05:11:49 PM PDT 24 Aug 09 05:11:52 PM PDT 24 2020944303 ps

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.2207702743
Short name T1
Test name
Test status
Simulation time 87610386725 ps
CPU time 198.5 seconds
Started Aug 09 05:14:22 PM PDT 24
Finished Aug 09 05:17:40 PM PDT 24
Peak memory 217476 kb
Host smart-d31ec2e5-2b77-4fe0-a267-230e431c9b06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207702743 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.2207702743
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.449056471
Short name T9
Test name
Test status
Simulation time 322747260827 ps
CPU time 36.88 seconds
Started Aug 09 05:13:25 PM PDT 24
Finished Aug 09 05:14:02 PM PDT 24
Peak memory 209472 kb
Host smart-58630d88-113a-4ac3-bbba-57e5ad084aca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449056471 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.449056471
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1481015753
Short name T30
Test name
Test status
Simulation time 64426016076 ps
CPU time 25.72 seconds
Started Aug 09 05:12:46 PM PDT 24
Finished Aug 09 05:13:12 PM PDT 24
Peak memory 201108 kb
Host smart-d9f8dc2f-3634-4284-b1b8-dcf58a85b91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481015753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.1481015753
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.2859333564
Short name T31
Test name
Test status
Simulation time 177198716050 ps
CPU time 110.33 seconds
Started Aug 09 05:14:25 PM PDT 24
Finished Aug 09 05:16:16 PM PDT 24
Peak memory 209436 kb
Host smart-5c7f2895-719a-436d-b035-4a604c8388aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859333564 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.2859333564
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.3365835413
Short name T74
Test name
Test status
Simulation time 29929702127 ps
CPU time 79.56 seconds
Started Aug 09 05:12:35 PM PDT 24
Finished Aug 09 05:13:55 PM PDT 24
Peak memory 200752 kb
Host smart-59af6f84-9693-4dde-b4eb-5d534f9e371c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365835413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.3365835413
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.1242951239
Short name T29
Test name
Test status
Simulation time 167639551223 ps
CPU time 121.41 seconds
Started Aug 09 05:12:56 PM PDT 24
Finished Aug 09 05:14:57 PM PDT 24
Peak memory 201084 kb
Host smart-08e83732-d93c-4086-9477-c19d260f50f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242951239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.1242951239
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3631000596
Short name T28
Test name
Test status
Simulation time 42750549409 ps
CPU time 34.38 seconds
Started Aug 09 05:10:57 PM PDT 24
Finished Aug 09 05:11:32 PM PDT 24
Peak memory 201608 kb
Host smart-a2f02a2b-8a9c-4c0a-83c2-3fafbf5913b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631000596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.3631000596
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2117024980
Short name T20
Test name
Test status
Simulation time 88919753774 ps
CPU time 46.43 seconds
Started Aug 09 05:14:43 PM PDT 24
Finished Aug 09 05:15:30 PM PDT 24
Peak memory 209372 kb
Host smart-1a217d82-849a-46a7-8145-3d063cd90056
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117024980 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.2117024980
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.2960737065
Short name T36
Test name
Test status
Simulation time 142338816574 ps
CPU time 85.07 seconds
Started Aug 09 05:13:50 PM PDT 24
Finished Aug 09 05:15:15 PM PDT 24
Peak memory 217516 kb
Host smart-ca874764-8a0c-4384-8a2f-308bae518826
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960737065 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.2960737065
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.274349230
Short name T34
Test name
Test status
Simulation time 133447251055 ps
CPU time 181.15 seconds
Started Aug 09 05:13:47 PM PDT 24
Finished Aug 09 05:16:48 PM PDT 24
Peak memory 201112 kb
Host smart-01274e0e-e979-46b2-97ff-9a25380bbc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274349230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_wi
th_pre_cond.274349230
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3609593248
Short name T86
Test name
Test status
Simulation time 74726149957 ps
CPU time 163.68 seconds
Started Aug 09 05:14:59 PM PDT 24
Finished Aug 09 05:17:43 PM PDT 24
Peak memory 212920 kb
Host smart-9f13f96e-7f39-4ca0-9c7a-b4c5b3a26aa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609593248 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.3609593248
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.751311186
Short name T48
Test name
Test status
Simulation time 22042656425 ps
CPU time 16.07 seconds
Started Aug 09 05:12:49 PM PDT 24
Finished Aug 09 05:13:05 PM PDT 24
Peak memory 220308 kb
Host smart-89d940d1-e75c-4744-bdb1-e08ca7b64fa5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751311186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.751311186
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2707413857
Short name T140
Test name
Test status
Simulation time 51080745393 ps
CPU time 25.28 seconds
Started Aug 09 05:13:58 PM PDT 24
Finished Aug 09 05:14:24 PM PDT 24
Peak memory 217580 kb
Host smart-79fbc2e6-26a4-48e6-a73f-d3ec382fbbae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707413857 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.2707413857
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2166993504
Short name T277
Test name
Test status
Simulation time 2145334710 ps
CPU time 3.3 seconds
Started Aug 09 05:11:20 PM PDT 24
Finished Aug 09 05:11:23 PM PDT 24
Peak memory 201372 kb
Host smart-e703125f-6c39-4305-883e-16636861f268
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166993504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_erro
rs.2166993504
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.2041813731
Short name T196
Test name
Test status
Simulation time 225530535861 ps
CPU time 46.54 seconds
Started Aug 09 05:13:25 PM PDT 24
Finished Aug 09 05:14:12 PM PDT 24
Peak memory 200948 kb
Host smart-ea9f3ac0-93c6-481f-a9c3-efb05764ceb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041813731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.2041813731
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.270621015
Short name T143
Test name
Test status
Simulation time 3241067752 ps
CPU time 2.4 seconds
Started Aug 09 05:13:36 PM PDT 24
Finished Aug 09 05:13:39 PM PDT 24
Peak memory 200784 kb
Host smart-1f555fce-49f4-4670-82e7-77ac8256a012
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270621015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctr
l_edge_detect.270621015
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2710766155
Short name T363
Test name
Test status
Simulation time 86114330024 ps
CPU time 52.06 seconds
Started Aug 09 05:15:29 PM PDT 24
Finished Aug 09 05:16:21 PM PDT 24
Peak memory 201156 kb
Host smart-70795ce1-b775-4ae3-ad31-59b9648842c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710766155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.2710766155
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2561955449
Short name T8
Test name
Test status
Simulation time 5627459138 ps
CPU time 2.24 seconds
Started Aug 09 05:12:55 PM PDT 24
Finished Aug 09 05:12:57 PM PDT 24
Peak memory 200792 kb
Host smart-4d47a0f9-b56d-4333-9afe-da32938212fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561955449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ultra_low_pwr.2561955449
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.2369215715
Short name T3
Test name
Test status
Simulation time 69139874671 ps
CPU time 46.39 seconds
Started Aug 09 05:13:57 PM PDT 24
Finished Aug 09 05:14:44 PM PDT 24
Peak memory 201052 kb
Host smart-903be688-5ca2-4ed3-a011-9e6537588a92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369215715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.2369215715
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.514436441
Short name T245
Test name
Test status
Simulation time 33266352645 ps
CPU time 15.26 seconds
Started Aug 09 05:14:36 PM PDT 24
Finished Aug 09 05:14:51 PM PDT 24
Peak memory 201156 kb
Host smart-24ef6ab2-d7e0-4f36-b751-522512e28974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514436441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_wi
th_pre_cond.514436441
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.581585690
Short name T19
Test name
Test status
Simulation time 2044448564 ps
CPU time 6.4 seconds
Started Aug 09 05:11:29 PM PDT 24
Finished Aug 09 05:11:35 PM PDT 24
Peak memory 201376 kb
Host smart-770c770d-636b-4330-acd9-f109399e0fd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581585690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_r
w.581585690
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2049319328
Short name T37
Test name
Test status
Simulation time 47940904729 ps
CPU time 121.17 seconds
Started Aug 09 05:14:58 PM PDT 24
Finished Aug 09 05:16:59 PM PDT 24
Peak memory 217620 kb
Host smart-70686335-310f-49ac-90a9-ce01c314133e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049319328 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.2049319328
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3747423544
Short name T173
Test name
Test status
Simulation time 39442636606 ps
CPU time 86.35 seconds
Started Aug 09 05:13:46 PM PDT 24
Finished Aug 09 05:15:12 PM PDT 24
Peak memory 209460 kb
Host smart-bb67209a-f365-47c9-acba-21a87deb27fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747423544 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.3747423544
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.587128241
Short name T134
Test name
Test status
Simulation time 2646045411 ps
CPU time 3.88 seconds
Started Aug 09 05:15:09 PM PDT 24
Finished Aug 09 05:15:13 PM PDT 24
Peak memory 200784 kb
Host smart-0f19dc81-552c-4e97-9c87-3d015eafe0e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587128241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctr
l_edge_detect.587128241
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2378147701
Short name T67
Test name
Test status
Simulation time 199348486863 ps
CPU time 182.76 seconds
Started Aug 09 05:15:28 PM PDT 24
Finished Aug 09 05:18:30 PM PDT 24
Peak memory 201148 kb
Host smart-4ba8798b-422c-4660-b1f9-cb151e3fa558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378147701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.2378147701
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.4000381227
Short name T213
Test name
Test status
Simulation time 3615844715 ps
CPU time 1.64 seconds
Started Aug 09 05:13:41 PM PDT 24
Finished Aug 09 05:13:42 PM PDT 24
Peak memory 200888 kb
Host smart-f60b70f2-cbd5-4993-ac63-c4f1e97caff0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000381227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_edge_detect.4000381227
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2300794110
Short name T135
Test name
Test status
Simulation time 57018556932 ps
CPU time 129.26 seconds
Started Aug 09 05:12:41 PM PDT 24
Finished Aug 09 05:14:51 PM PDT 24
Peak memory 209364 kb
Host smart-62379286-c9e8-4266-af9b-7eb97978ed05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300794110 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.2300794110
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.1191030451
Short name T340
Test name
Test status
Simulation time 194519204676 ps
CPU time 268.63 seconds
Started Aug 09 05:12:55 PM PDT 24
Finished Aug 09 05:17:24 PM PDT 24
Peak memory 201032 kb
Host smart-c9c492c4-eb5f-44ff-b5bf-b38347795d37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191030451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.1191030451
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.4294800238
Short name T379
Test name
Test status
Simulation time 217630132885 ps
CPU time 43.27 seconds
Started Aug 09 05:15:19 PM PDT 24
Finished Aug 09 05:16:03 PM PDT 24
Peak memory 209396 kb
Host smart-ceb78c63-a45c-4700-833b-3678dd3b8c82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294800238 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.4294800238
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.1225146296
Short name T54
Test name
Test status
Simulation time 2021918899 ps
CPU time 2.4 seconds
Started Aug 09 05:13:40 PM PDT 24
Finished Aug 09 05:13:43 PM PDT 24
Peak memory 200768 kb
Host smart-e11e6ba4-7055-4a0e-a99d-48ea0a67fb00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225146296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.1225146296
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.587011266
Short name T334
Test name
Test status
Simulation time 75522965614 ps
CPU time 33.42 seconds
Started Aug 09 05:14:34 PM PDT 24
Finished Aug 09 05:15:08 PM PDT 24
Peak memory 201048 kb
Host smart-c2a2d16c-6073-44a3-877e-1adf9b72cd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587011266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_wi
th_pre_cond.587011266
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.2147950178
Short name T261
Test name
Test status
Simulation time 9528894222 ps
CPU time 26.25 seconds
Started Aug 09 05:14:23 PM PDT 24
Finished Aug 09 05:14:50 PM PDT 24
Peak memory 200864 kb
Host smart-5e26f32b-50f7-4a2d-b423-5165f9b1c990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147950178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.2147950178
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.115975299
Short name T218
Test name
Test status
Simulation time 96506006695 ps
CPU time 64.44 seconds
Started Aug 09 05:15:19 PM PDT 24
Finished Aug 09 05:16:24 PM PDT 24
Peak memory 201164 kb
Host smart-6ea0e517-f939-410f-a88d-ac44879c00ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115975299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_wi
th_pre_cond.115975299
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3157584849
Short name T24
Test name
Test status
Simulation time 65010814389 ps
CPU time 154.55 seconds
Started Aug 09 05:10:59 PM PDT 24
Finished Aug 09 05:13:34 PM PDT 24
Peak memory 201540 kb
Host smart-1867e4cc-69a1-4efc-9676-a6d1b7a93558
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157584849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_bit_bash.3157584849
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2971788476
Short name T347
Test name
Test status
Simulation time 90493907501 ps
CPU time 224.49 seconds
Started Aug 09 05:15:31 PM PDT 24
Finished Aug 09 05:19:16 PM PDT 24
Peak memory 201376 kb
Host smart-05d5603b-8549-4d94-b91c-80a291fac19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971788476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w
ith_pre_cond.2971788476
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.507312265
Short name T339
Test name
Test status
Simulation time 82850131755 ps
CPU time 214.38 seconds
Started Aug 09 05:14:36 PM PDT 24
Finished Aug 09 05:18:10 PM PDT 24
Peak memory 200968 kb
Host smart-6e9830c4-ab68-4042-806b-f4c0b35f34d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507312265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_wi
th_pre_cond.507312265
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.1825685917
Short name T79
Test name
Test status
Simulation time 52211952342 ps
CPU time 8.36 seconds
Started Aug 09 05:14:23 PM PDT 24
Finished Aug 09 05:14:32 PM PDT 24
Peak memory 201084 kb
Host smart-99ab3080-af3d-4fc5-ad4a-b112fef98c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825685917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.1825685917
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.2553354852
Short name T343
Test name
Test status
Simulation time 175210917466 ps
CPU time 107.5 seconds
Started Aug 09 05:14:32 PM PDT 24
Finished Aug 09 05:16:19 PM PDT 24
Peak memory 201024 kb
Host smart-473a2e70-7e73-4b80-bf8a-3db863a450ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553354852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_combo_detect.2553354852
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.104600130
Short name T100
Test name
Test status
Simulation time 403791415863 ps
CPU time 114.89 seconds
Started Aug 09 05:14:52 PM PDT 24
Finished Aug 09 05:16:47 PM PDT 24
Peak memory 214708 kb
Host smart-f29ac5b3-b5ba-4784-877a-a721461a23f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104600130 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.104600130
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.137194763
Short name T12
Test name
Test status
Simulation time 2558776087 ps
CPU time 2.02 seconds
Started Aug 09 05:13:16 PM PDT 24
Finished Aug 09 05:13:18 PM PDT 24
Peak memory 200752 kb
Host smart-578c0866-ebb8-41e4-987b-63f11758659c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137194763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctr
l_edge_detect.137194763
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.267709996
Short name T627
Test name
Test status
Simulation time 68366087176 ps
CPU time 82.2 seconds
Started Aug 09 05:12:40 PM PDT 24
Finished Aug 09 05:14:02 PM PDT 24
Peak memory 201104 kb
Host smart-f92407c7-2c0c-4241-83c7-1b149a853ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267709996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wit
h_pre_cond.267709996
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.4227163253
Short name T115
Test name
Test status
Simulation time 448683873309 ps
CPU time 17.99 seconds
Started Aug 09 05:12:41 PM PDT 24
Finished Aug 09 05:12:59 PM PDT 24
Peak memory 209316 kb
Host smart-78bd3a5a-36df-4422-b715-d6203cbb1ebf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227163253 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.4227163253
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.1422875574
Short name T68
Test name
Test status
Simulation time 96218944174 ps
CPU time 116.62 seconds
Started Aug 09 05:13:41 PM PDT 24
Finished Aug 09 05:15:37 PM PDT 24
Peak memory 201096 kb
Host smart-bd376603-6c98-4b11-805a-3285ad75be6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422875574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_w
ith_pre_cond.1422875574
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.3195723729
Short name T346
Test name
Test status
Simulation time 125375549540 ps
CPU time 88.44 seconds
Started Aug 09 05:15:20 PM PDT 24
Finished Aug 09 05:16:49 PM PDT 24
Peak memory 201176 kb
Host smart-e849ddad-e113-414f-934a-60ea714ef08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195723729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.3195723729
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2026201293
Short name T284
Test name
Test status
Simulation time 2030527135 ps
CPU time 7.02 seconds
Started Aug 09 05:11:00 PM PDT 24
Finished Aug 09 05:11:07 PM PDT 24
Peak memory 201364 kb
Host smart-0f97c6f1-620a-4e7e-ace4-1100d558f77f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026201293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.2026201293
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2769086408
Short name T142
Test name
Test status
Simulation time 822938078448 ps
CPU time 90.56 seconds
Started Aug 09 05:14:33 PM PDT 24
Finished Aug 09 05:16:03 PM PDT 24
Peak memory 209404 kb
Host smart-dd0add7b-abdc-4ddc-ac6c-c2919c69baea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769086408 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.2769086408
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.2331938058
Short name T202
Test name
Test status
Simulation time 3260867553 ps
CPU time 7.6 seconds
Started Aug 09 05:14:36 PM PDT 24
Finished Aug 09 05:14:43 PM PDT 24
Peak memory 200736 kb
Host smart-0a63f1a2-6a2c-4d7e-bbf1-14c5ef4a0084
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331938058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.2331938058
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.4135028202
Short name T172
Test name
Test status
Simulation time 11244415604 ps
CPU time 6.51 seconds
Started Aug 09 05:15:01 PM PDT 24
Finished Aug 09 05:15:08 PM PDT 24
Peak memory 200752 kb
Host smart-640ba0af-e640-4b2a-9bfb-bde32862305c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135028202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.4135028202
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3346892785
Short name T353
Test name
Test status
Simulation time 22294760877 ps
CPU time 29.49 seconds
Started Aug 09 05:11:28 PM PDT 24
Finished Aug 09 05:11:58 PM PDT 24
Peak memory 201500 kb
Host smart-c675a7b2-5442-4bc1-8abf-6ed1abd3e7f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346892785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.3346892785
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1433943230
Short name T332
Test name
Test status
Simulation time 4028940776 ps
CPU time 10.59 seconds
Started Aug 09 05:11:04 PM PDT 24
Finished Aug 09 05:11:15 PM PDT 24
Peak memory 201268 kb
Host smart-0442ac91-7880-42c4-b09e-183b30a6e26f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433943230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.1433943230
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.1082836818
Short name T355
Test name
Test status
Simulation time 22216951822 ps
CPU time 59.11 seconds
Started Aug 09 05:11:06 PM PDT 24
Finished Aug 09 05:12:05 PM PDT 24
Peak memory 201520 kb
Host smart-d6d9b7de-9993-492f-a3b7-a723adf2b25d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082836818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_tl_intg_err.1082836818
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.834752929
Short name T388
Test name
Test status
Simulation time 2587138791448 ps
CPU time 178.07 seconds
Started Aug 09 05:12:37 PM PDT 24
Finished Aug 09 05:15:35 PM PDT 24
Peak memory 200960 kb
Host smart-5190c1e7-73d3-4502-9557-9036f59b2138
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834752929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_ultra_low_pwr.834752929
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.668777673
Short name T90
Test name
Test status
Simulation time 44441354044 ps
CPU time 23.55 seconds
Started Aug 09 05:13:09 PM PDT 24
Finished Aug 09 05:13:33 PM PDT 24
Peak memory 200996 kb
Host smart-a435b5d3-9d29-419f-ab7f-9e1ae87536dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668777673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_combo_detect.668777673
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.1996686339
Short name T364
Test name
Test status
Simulation time 129731167736 ps
CPU time 30.25 seconds
Started Aug 09 05:13:10 PM PDT 24
Finished Aug 09 05:13:40 PM PDT 24
Peak memory 201076 kb
Host smart-c1f2ac3d-bd77-4c2b-adc4-ba07ef53f7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996686339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_w
ith_pre_cond.1996686339
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.4135250583
Short name T793
Test name
Test status
Simulation time 91299532904 ps
CPU time 58.03 seconds
Started Aug 09 05:13:25 PM PDT 24
Finished Aug 09 05:14:23 PM PDT 24
Peak memory 201052 kb
Host smart-503af097-416c-4c03-ad7f-dc0243211da8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135250583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.4135250583
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2014480021
Short name T359
Test name
Test status
Simulation time 40330429822 ps
CPU time 56.31 seconds
Started Aug 09 05:13:23 PM PDT 24
Finished Aug 09 05:14:20 PM PDT 24
Peak memory 201096 kb
Host smart-63b9a1ad-18a0-4913-8eb8-5d4365cd66dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014480021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_w
ith_pre_cond.2014480021
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.3155439862
Short name T376
Test name
Test status
Simulation time 50719680613 ps
CPU time 125.75 seconds
Started Aug 09 05:13:42 PM PDT 24
Finished Aug 09 05:15:48 PM PDT 24
Peak memory 201308 kb
Host smart-3fea75ff-ea40-49ed-a3f6-e3be8fcb735a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155439862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.3155439862
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1278906587
Short name T56
Test name
Test status
Simulation time 21558435419 ps
CPU time 48.68 seconds
Started Aug 09 05:13:38 PM PDT 24
Finished Aug 09 05:14:27 PM PDT 24
Peak memory 209432 kb
Host smart-f635b775-9823-4070-a107-be672f64f249
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278906587 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.1278906587
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2346515322
Short name T358
Test name
Test status
Simulation time 80594042709 ps
CPU time 27.85 seconds
Started Aug 09 05:14:52 PM PDT 24
Finished Aug 09 05:15:20 PM PDT 24
Peak memory 201068 kb
Host smart-3b351d11-76a3-42d0-9a6d-aec59899565c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346515322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.2346515322
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.316715094
Short name T384
Test name
Test status
Simulation time 26333751158 ps
CPU time 32.59 seconds
Started Aug 09 05:15:02 PM PDT 24
Finished Aug 09 05:15:35 PM PDT 24
Peak memory 201096 kb
Host smart-96423df6-bf4a-4c8a-8188-57773fd02668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316715094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_wi
th_pre_cond.316715094
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2074763341
Short name T365
Test name
Test status
Simulation time 107052249997 ps
CPU time 65.45 seconds
Started Aug 09 05:15:19 PM PDT 24
Finished Aug 09 05:16:24 PM PDT 24
Peak memory 201084 kb
Host smart-e8c00f92-2294-418f-b300-ccb6ae991a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074763341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.2074763341
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2510267611
Short name T349
Test name
Test status
Simulation time 145999068520 ps
CPU time 120.94 seconds
Started Aug 09 05:15:20 PM PDT 24
Finished Aug 09 05:17:21 PM PDT 24
Peak memory 201024 kb
Host smart-9451dc31-7c05-40af-96a8-34855154ca90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510267611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.2510267611
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2181310302
Short name T263
Test name
Test status
Simulation time 70282768498 ps
CPU time 41.01 seconds
Started Aug 09 05:15:29 PM PDT 24
Finished Aug 09 05:16:10 PM PDT 24
Peak memory 201048 kb
Host smart-10b22b42-5843-49f9-bb92-be8c16a80607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181310302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.2181310302
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1917960018
Short name T368
Test name
Test status
Simulation time 50981789791 ps
CPU time 96.89 seconds
Started Aug 09 05:15:29 PM PDT 24
Finished Aug 09 05:17:06 PM PDT 24
Peak memory 201120 kb
Host smart-7e23f9ea-6974-4ff0-b2fe-b030fe13ce08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917960018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_w
ith_pre_cond.1917960018
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.45350345
Short name T366
Test name
Test status
Simulation time 110881293463 ps
CPU time 138.53 seconds
Started Aug 09 05:15:29 PM PDT 24
Finished Aug 09 05:17:48 PM PDT 24
Peak memory 201064 kb
Host smart-feb06e7c-9e15-4547-ae47-907d743e771f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45350345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_wit
h_pre_cond.45350345
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.3437454991
Short name T256
Test name
Test status
Simulation time 82137214347 ps
CPU time 219.55 seconds
Started Aug 09 05:15:18 PM PDT 24
Finished Aug 09 05:18:57 PM PDT 24
Peak memory 201028 kb
Host smart-c2b4d1e7-2f06-4c3f-92b1-b484e07bef8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437454991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w
ith_pre_cond.3437454991
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.3844734590
Short name T80
Test name
Test status
Simulation time 68786795386 ps
CPU time 170.94 seconds
Started Aug 09 05:15:18 PM PDT 24
Finished Aug 09 05:18:09 PM PDT 24
Peak memory 201112 kb
Host smart-c233370c-a403-4b44-980b-0a9f8c94deea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844734590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.3844734590
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3164389247
Short name T891
Test name
Test status
Simulation time 2546582088 ps
CPU time 3.72 seconds
Started Aug 09 05:10:59 PM PDT 24
Finished Aug 09 05:11:03 PM PDT 24
Peak memory 201508 kb
Host smart-5751084f-4aac-48c9-a33e-8143edf870f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164389247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.3164389247
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.211609578
Short name T909
Test name
Test status
Simulation time 39055740396 ps
CPU time 93.75 seconds
Started Aug 09 05:10:57 PM PDT 24
Finished Aug 09 05:12:31 PM PDT 24
Peak memory 201524 kb
Host smart-88d3befd-a217-4e9d-a408-f22a74617672
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211609578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_
csr_bit_bash.211609578
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.361000516
Short name T895
Test name
Test status
Simulation time 6065508830 ps
CPU time 4.69 seconds
Started Aug 09 05:11:02 PM PDT 24
Finished Aug 09 05:11:07 PM PDT 24
Peak memory 201312 kb
Host smart-7b6c6a55-662a-4cee-ae3f-b62446d47412
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361000516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_
csr_hw_reset.361000516
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2998958094
Short name T830
Test name
Test status
Simulation time 2105663419 ps
CPU time 2.14 seconds
Started Aug 09 05:10:58 PM PDT 24
Finished Aug 09 05:11:00 PM PDT 24
Peak memory 201236 kb
Host smart-b8149fea-9cf8-4fe0-bf0f-2a3e9b09fb63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998958094 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2998958094
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2229869393
Short name T816
Test name
Test status
Simulation time 2079685716 ps
CPU time 1.77 seconds
Started Aug 09 05:11:00 PM PDT 24
Finished Aug 09 05:11:02 PM PDT 24
Peak memory 201240 kb
Host smart-18e2f701-b641-4d04-9a87-29323fdfed95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229869393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.2229869393
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1325975342
Short name T912
Test name
Test status
Simulation time 2037726593 ps
CPU time 1.88 seconds
Started Aug 09 05:11:02 PM PDT 24
Finished Aug 09 05:11:03 PM PDT 24
Peak memory 200992 kb
Host smart-ce1b3e59-badc-4dfb-8171-6ea752855210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325975342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.1325975342
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.340131234
Short name T846
Test name
Test status
Simulation time 7930308617 ps
CPU time 6.04 seconds
Started Aug 09 05:10:56 PM PDT 24
Finished Aug 09 05:11:02 PM PDT 24
Peak memory 201488 kb
Host smart-bd802353-e758-498d-9ff9-8c6186222d54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340131234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
sysrst_ctrl_same_csr_outstanding.340131234
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.4063915426
Short name T288
Test name
Test status
Simulation time 2046565370 ps
CPU time 6.68 seconds
Started Aug 09 05:10:59 PM PDT 24
Finished Aug 09 05:11:05 PM PDT 24
Peak memory 201376 kb
Host smart-006777b8-dce3-41e9-927b-1050d08d275c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063915426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.4063915426
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1456579740
Short name T350
Test name
Test status
Simulation time 42362461076 ps
CPU time 112.91 seconds
Started Aug 09 05:10:59 PM PDT 24
Finished Aug 09 05:12:52 PM PDT 24
Peak memory 201448 kb
Host smart-7f8c2a4f-9c9f-4f09-bd1f-2e46c07eee43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456579740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.1456579740
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3805347921
Short name T317
Test name
Test status
Simulation time 2613306666 ps
CPU time 10.6 seconds
Started Aug 09 05:11:01 PM PDT 24
Finished Aug 09 05:11:11 PM PDT 24
Peak memory 201456 kb
Host smart-3604c583-37e7-4abf-b429-5c9fde6874ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805347921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.3805347921
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.438407056
Short name T819
Test name
Test status
Simulation time 4056683948 ps
CPU time 3.09 seconds
Started Aug 09 05:10:57 PM PDT 24
Finished Aug 09 05:11:00 PM PDT 24
Peak memory 201408 kb
Host smart-985bd554-9bad-47cf-8740-ef6e34629d3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438407056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_
csr_hw_reset.438407056
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.4190546785
Short name T876
Test name
Test status
Simulation time 2041971111 ps
CPU time 3.57 seconds
Started Aug 09 05:10:58 PM PDT 24
Finished Aug 09 05:11:02 PM PDT 24
Peak memory 201320 kb
Host smart-2b297327-f65d-4089-8af2-f623c979f1d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190546785 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.4190546785
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3018865701
Short name T320
Test name
Test status
Simulation time 2050443328 ps
CPU time 3.4 seconds
Started Aug 09 05:10:58 PM PDT 24
Finished Aug 09 05:11:01 PM PDT 24
Peak memory 201140 kb
Host smart-41ceee61-1d1a-48a1-979d-e4a054858ee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018865701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.3018865701
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.750568442
Short name T863
Test name
Test status
Simulation time 2012590826 ps
CPU time 5.71 seconds
Started Aug 09 05:10:58 PM PDT 24
Finished Aug 09 05:11:04 PM PDT 24
Peak memory 200968 kb
Host smart-6da29f99-e77f-453b-a99d-b39b11a47871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750568442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test
.750568442
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2662518785
Short name T898
Test name
Test status
Simulation time 10494770508 ps
CPU time 9.96 seconds
Started Aug 09 05:10:58 PM PDT 24
Finished Aug 09 05:11:08 PM PDT 24
Peak memory 201536 kb
Host smart-49a834e1-2e34-415d-ae66-7107149af65a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662518785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.2662518785
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2249147847
Short name T832
Test name
Test status
Simulation time 2079374778 ps
CPU time 5.97 seconds
Started Aug 09 05:11:23 PM PDT 24
Finished Aug 09 05:11:29 PM PDT 24
Peak memory 201400 kb
Host smart-df3c9a00-96c2-4e10-8017-b3d5bea55ce0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249147847 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2249147847
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2901884297
Short name T331
Test name
Test status
Simulation time 2035403067 ps
CPU time 3.94 seconds
Started Aug 09 05:11:19 PM PDT 24
Finished Aug 09 05:11:23 PM PDT 24
Peak memory 201320 kb
Host smart-e6d65fc5-e7a2-44a1-ac19-789af0559f46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901884297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.2901884297
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2730633655
Short name T859
Test name
Test status
Simulation time 2025532282 ps
CPU time 3.15 seconds
Started Aug 09 05:11:21 PM PDT 24
Finished Aug 09 05:11:25 PM PDT 24
Peak memory 201116 kb
Host smart-5c6ae9c7-e831-419c-95be-897490b917ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730633655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.2730633655
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2523809776
Short name T869
Test name
Test status
Simulation time 9511575768 ps
CPU time 34.05 seconds
Started Aug 09 05:11:22 PM PDT 24
Finished Aug 09 05:11:56 PM PDT 24
Peak memory 201628 kb
Host smart-140d7335-9e3a-458e-82b9-32165f61125f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523809776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.2523809776
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.592364556
Short name T884
Test name
Test status
Simulation time 2107994900 ps
CPU time 3.95 seconds
Started Aug 09 05:11:20 PM PDT 24
Finished Aug 09 05:11:24 PM PDT 24
Peak memory 201520 kb
Host smart-b008279f-dc64-4be9-99aa-4cfba19303e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592364556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_error
s.592364556
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.250758099
Short name T817
Test name
Test status
Simulation time 22220846578 ps
CPU time 54.06 seconds
Started Aug 09 05:11:21 PM PDT 24
Finished Aug 09 05:12:15 PM PDT 24
Peak memory 201648 kb
Host smart-c15b036d-04f9-41ff-8b02-b72130389ba6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250758099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_tl_intg_err.250758099
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.285451131
Short name T852
Test name
Test status
Simulation time 2056228344 ps
CPU time 3.52 seconds
Started Aug 09 05:11:21 PM PDT 24
Finished Aug 09 05:11:24 PM PDT 24
Peak memory 201304 kb
Host smart-f08c99f1-f80e-4789-a743-afcd85be1294
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285451131 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.285451131
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1865384381
Short name T326
Test name
Test status
Simulation time 2045196293 ps
CPU time 3.3 seconds
Started Aug 09 05:11:20 PM PDT 24
Finished Aug 09 05:11:24 PM PDT 24
Peak memory 201236 kb
Host smart-41100703-323a-4233-a426-15d136d7f471
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865384381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.1865384381
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2411268296
Short name T810
Test name
Test status
Simulation time 2014182449 ps
CPU time 5.67 seconds
Started Aug 09 05:11:21 PM PDT 24
Finished Aug 09 05:11:26 PM PDT 24
Peak memory 201076 kb
Host smart-df6abb69-0b50-4108-bc19-2aecb066970d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411268296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_te
st.2411268296
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.3073488668
Short name T329
Test name
Test status
Simulation time 8064680036 ps
CPU time 10.2 seconds
Started Aug 09 05:11:20 PM PDT 24
Finished Aug 09 05:11:30 PM PDT 24
Peak memory 201564 kb
Host smart-7bf5c594-da02-4f58-b4f1-60ab9c2da424
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073488668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.3073488668
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2108400968
Short name T902
Test name
Test status
Simulation time 2136173584 ps
CPU time 6.15 seconds
Started Aug 09 05:11:20 PM PDT 24
Finished Aug 09 05:11:26 PM PDT 24
Peak memory 201392 kb
Host smart-e0cee047-b270-41ef-b370-18c1e6af7fee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108400968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro
rs.2108400968
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3799345630
Short name T868
Test name
Test status
Simulation time 22500339878 ps
CPU time 12.18 seconds
Started Aug 09 05:11:19 PM PDT 24
Finished Aug 09 05:11:31 PM PDT 24
Peak memory 201504 kb
Host smart-d9118603-38b3-421d-933b-25a70f58ed0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799345630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.3799345630
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3965699473
Short name T809
Test name
Test status
Simulation time 2151065380 ps
CPU time 2.4 seconds
Started Aug 09 05:11:23 PM PDT 24
Finished Aug 09 05:11:25 PM PDT 24
Peak memory 201460 kb
Host smart-5caa9022-f9af-43a3-a087-b73c7fbb65aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965699473 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3965699473
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2238903991
Short name T901
Test name
Test status
Simulation time 2116691892 ps
CPU time 2.03 seconds
Started Aug 09 05:11:19 PM PDT 24
Finished Aug 09 05:11:21 PM PDT 24
Peak memory 201264 kb
Host smart-0b7a35bb-2992-461b-b7db-8a7c251307dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238903991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_
rw.2238903991
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1096621655
Short name T843
Test name
Test status
Simulation time 2072362059 ps
CPU time 1.53 seconds
Started Aug 09 05:11:20 PM PDT 24
Finished Aug 09 05:11:21 PM PDT 24
Peak memory 201048 kb
Host smart-b7c0d2a6-9cca-4281-9612-474c7bc74b55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096621655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.1096621655
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2142169530
Short name T896
Test name
Test status
Simulation time 10493998265 ps
CPU time 9.76 seconds
Started Aug 09 05:11:20 PM PDT 24
Finished Aug 09 05:11:30 PM PDT 24
Peak memory 201652 kb
Host smart-236cea3c-e14b-40b7-b1d7-e5d5c4c348b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142169530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.2142169530
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1621087698
Short name T864
Test name
Test status
Simulation time 2430884842 ps
CPU time 2.38 seconds
Started Aug 09 05:11:23 PM PDT 24
Finished Aug 09 05:11:25 PM PDT 24
Peak memory 201536 kb
Host smart-09009ce4-a5f7-43db-bfbe-bf4c8785a12e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621087698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.1621087698
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3053884843
Short name T858
Test name
Test status
Simulation time 42449067651 ps
CPU time 90.58 seconds
Started Aug 09 05:11:23 PM PDT 24
Finished Aug 09 05:12:53 PM PDT 24
Peak memory 201832 kb
Host smart-182d133a-1950-4c8a-b648-84a893462887
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053884843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.3053884843
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.869441936
Short name T833
Test name
Test status
Simulation time 2184583787 ps
CPU time 2.7 seconds
Started Aug 09 05:11:20 PM PDT 24
Finished Aug 09 05:11:23 PM PDT 24
Peak memory 201572 kb
Host smart-c85957cf-15bb-4a45-ba99-6387c28cee01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869441936 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.869441936
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.6763169
Short name T821
Test name
Test status
Simulation time 2033214413 ps
CPU time 5.74 seconds
Started Aug 09 05:11:18 PM PDT 24
Finished Aug 09 05:11:24 PM PDT 24
Peak memory 201236 kb
Host smart-46897377-8ded-4627-84f3-c40f626af5fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6763169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_rw.6763169
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.584690801
Short name T795
Test name
Test status
Simulation time 2011679954 ps
CPU time 5.95 seconds
Started Aug 09 05:11:21 PM PDT 24
Finished Aug 09 05:11:27 PM PDT 24
Peak memory 201244 kb
Host smart-6e166c4b-a2ab-4714-b7de-6a13fa874c73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584690801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_tes
t.584690801
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2079131918
Short name T842
Test name
Test status
Simulation time 4595879161 ps
CPU time 4.56 seconds
Started Aug 09 05:11:21 PM PDT 24
Finished Aug 09 05:11:26 PM PDT 24
Peak memory 201548 kb
Host smart-dad21b01-aeb8-4c4b-95c3-395cb40a14f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079131918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.2079131918
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.856361472
Short name T838
Test name
Test status
Simulation time 22263545983 ps
CPU time 15.51 seconds
Started Aug 09 05:11:24 PM PDT 24
Finished Aug 09 05:11:39 PM PDT 24
Peak memory 201620 kb
Host smart-a1585d76-7271-4d85-87a4-b5ddf07e1de8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856361472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_tl_intg_err.856361472
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.966219865
Short name T290
Test name
Test status
Simulation time 2074343527 ps
CPU time 6.29 seconds
Started Aug 09 05:11:29 PM PDT 24
Finished Aug 09 05:11:35 PM PDT 24
Peak memory 201284 kb
Host smart-c0a64363-0cd3-45fa-89fc-30ef032477c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966219865 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.966219865
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.465590222
Short name T871
Test name
Test status
Simulation time 2050032021 ps
CPU time 5.68 seconds
Started Aug 09 05:11:19 PM PDT 24
Finished Aug 09 05:11:25 PM PDT 24
Peak memory 201272 kb
Host smart-49528c40-98ed-4e36-b3ca-bd7118487753
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465590222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_r
w.465590222
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3761817768
Short name T889
Test name
Test status
Simulation time 2046052596 ps
CPU time 1.89 seconds
Started Aug 09 05:11:19 PM PDT 24
Finished Aug 09 05:11:21 PM PDT 24
Peak memory 200988 kb
Host smart-d4cf1786-8db5-4bdc-a9e9-b879f4c8607f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761817768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.3761817768
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2537462534
Short name T327
Test name
Test status
Simulation time 8251982802 ps
CPU time 6.55 seconds
Started Aug 09 05:11:29 PM PDT 24
Finished Aug 09 05:11:35 PM PDT 24
Peak memory 201556 kb
Host smart-48f54a78-5275-47d3-b351-8ee92898999d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537462534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.2537462534
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.976245747
Short name T845
Test name
Test status
Simulation time 2294059243 ps
CPU time 3.23 seconds
Started Aug 09 05:11:20 PM PDT 24
Finished Aug 09 05:11:23 PM PDT 24
Peak memory 201504 kb
Host smart-939dc660-3e1b-4a17-8f68-0524b2d0c55a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976245747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_error
s.976245747
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1914116139
Short name T854
Test name
Test status
Simulation time 22221612721 ps
CPU time 52.61 seconds
Started Aug 09 05:11:21 PM PDT 24
Finished Aug 09 05:12:13 PM PDT 24
Peak memory 201552 kb
Host smart-26d1109c-f7a1-4003-9ac1-a8294716a850
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914116139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.1914116139
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.292662890
Short name T827
Test name
Test status
Simulation time 2246536645 ps
CPU time 1.85 seconds
Started Aug 09 05:11:25 PM PDT 24
Finished Aug 09 05:11:27 PM PDT 24
Peak memory 201476 kb
Host smart-f3d4b699-ad11-49a1-99d5-294263e5d90e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292662890 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.292662890
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.568598861
Short name T903
Test name
Test status
Simulation time 2066487371 ps
CPU time 3.35 seconds
Started Aug 09 05:11:27 PM PDT 24
Finished Aug 09 05:11:31 PM PDT 24
Peak memory 201212 kb
Host smart-b799f96a-04e3-45c8-8e26-c94785c1e3b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568598861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_r
w.568598861
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.4286408346
Short name T803
Test name
Test status
Simulation time 2043335729 ps
CPU time 1.87 seconds
Started Aug 09 05:11:27 PM PDT 24
Finished Aug 09 05:11:29 PM PDT 24
Peak memory 201028 kb
Host smart-c131be53-1d61-4732-8489-415442a88a89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286408346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.4286408346
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2952355931
Short name T17
Test name
Test status
Simulation time 8126872366 ps
CPU time 22.12 seconds
Started Aug 09 05:11:31 PM PDT 24
Finished Aug 09 05:11:53 PM PDT 24
Peak memory 201596 kb
Host smart-4cf39b3b-3dc8-453a-98c2-c0638dbec3dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952355931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.2952355931
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3502406903
Short name T278
Test name
Test status
Simulation time 2128527087 ps
CPU time 8.34 seconds
Started Aug 09 05:11:29 PM PDT 24
Finished Aug 09 05:11:37 PM PDT 24
Peak memory 209564 kb
Host smart-b8e7fc50-b944-4b33-a291-581267569a0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502406903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.3502406903
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.233672815
Short name T874
Test name
Test status
Simulation time 22229795827 ps
CPU time 58.77 seconds
Started Aug 09 05:11:30 PM PDT 24
Finished Aug 09 05:12:29 PM PDT 24
Peak memory 201524 kb
Host smart-6d564467-0aab-4974-b152-947fea5a1df2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233672815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_tl_intg_err.233672815
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2981394301
Short name T847
Test name
Test status
Simulation time 2110822622 ps
CPU time 3.7 seconds
Started Aug 09 05:11:30 PM PDT 24
Finished Aug 09 05:11:34 PM PDT 24
Peak memory 201320 kb
Host smart-e111265d-ba4b-48d7-86c0-9d9ae1db73a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981394301 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2981394301
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3464355640
Short name T324
Test name
Test status
Simulation time 2103725097 ps
CPU time 2.15 seconds
Started Aug 09 05:11:27 PM PDT 24
Finished Aug 09 05:11:29 PM PDT 24
Peak memory 201148 kb
Host smart-c7abb560-02e7-481e-b42d-ae9b8166d99a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464355640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.3464355640
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2574822856
Short name T811
Test name
Test status
Simulation time 2071964092 ps
CPU time 1.24 seconds
Started Aug 09 05:11:31 PM PDT 24
Finished Aug 09 05:11:32 PM PDT 24
Peak memory 200668 kb
Host smart-1be2d01b-201c-4557-bf5a-38cfed822730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574822856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.2574822856
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2067394128
Short name T18
Test name
Test status
Simulation time 10438704091 ps
CPU time 32.8 seconds
Started Aug 09 05:11:29 PM PDT 24
Finished Aug 09 05:12:02 PM PDT 24
Peak memory 201596 kb
Host smart-6043825a-097e-4678-ae14-353fe9f2fd17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067394128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.2067394128
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.4212018077
Short name T276
Test name
Test status
Simulation time 2028095027 ps
CPU time 6.93 seconds
Started Aug 09 05:11:26 PM PDT 24
Finished Aug 09 05:11:33 PM PDT 24
Peak memory 201340 kb
Host smart-cf28db6d-f6e7-4920-a52d-d007cad3eaae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212018077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.4212018077
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.4054669480
Short name T879
Test name
Test status
Simulation time 2051168317 ps
CPU time 3.28 seconds
Started Aug 09 05:11:27 PM PDT 24
Finished Aug 09 05:11:30 PM PDT 24
Peak memory 201316 kb
Host smart-dc871b62-6dab-4779-9a7f-d4b5a75c142d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054669480 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.4054669480
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3800749738
Short name T897
Test name
Test status
Simulation time 2013772044 ps
CPU time 5.49 seconds
Started Aug 09 05:11:31 PM PDT 24
Finished Aug 09 05:11:37 PM PDT 24
Peak memory 200424 kb
Host smart-6b87846d-bde2-4dc2-84c2-57aac1a7967b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800749738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.3800749738
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1012875424
Short name T814
Test name
Test status
Simulation time 8007321303 ps
CPU time 33.04 seconds
Started Aug 09 05:11:28 PM PDT 24
Finished Aug 09 05:12:01 PM PDT 24
Peak memory 201552 kb
Host smart-2cdf7b89-317a-4102-8f09-56fdf38a41e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012875424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_same_csr_outstanding.1012875424
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1040709822
Short name T882
Test name
Test status
Simulation time 2165126284 ps
CPU time 3.78 seconds
Started Aug 09 05:11:29 PM PDT 24
Finished Aug 09 05:11:33 PM PDT 24
Peak memory 201540 kb
Host smart-87432c37-ba38-4975-8e83-73b2f776bd8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040709822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.1040709822
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.985033209
Short name T857
Test name
Test status
Simulation time 22248192817 ps
CPU time 15.71 seconds
Started Aug 09 05:11:27 PM PDT 24
Finished Aug 09 05:11:43 PM PDT 24
Peak memory 201576 kb
Host smart-a2a1b230-23bc-40a6-b495-5b8013bf2d67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985033209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_tl_intg_err.985033209
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2632396148
Short name T26
Test name
Test status
Simulation time 2115985182 ps
CPU time 2.23 seconds
Started Aug 09 05:11:35 PM PDT 24
Finished Aug 09 05:11:37 PM PDT 24
Peak memory 201196 kb
Host smart-f7b92cf9-2d33-4912-8cea-6cd8427a1bc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632396148 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2632396148
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2858024050
Short name T910
Test name
Test status
Simulation time 2070994511 ps
CPU time 3.22 seconds
Started Aug 09 05:11:30 PM PDT 24
Finished Aug 09 05:11:33 PM PDT 24
Peak memory 201296 kb
Host smart-2240539d-1cdf-4abc-ba6c-8a64c19c54ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858024050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.2858024050
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3539467114
Short name T861
Test name
Test status
Simulation time 2014797247 ps
CPU time 5.32 seconds
Started Aug 09 05:11:28 PM PDT 24
Finished Aug 09 05:11:33 PM PDT 24
Peak memory 201252 kb
Host smart-969cdc08-b26a-4b24-bc9d-079d0429f98c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539467114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.3539467114
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1353529146
Short name T907
Test name
Test status
Simulation time 4875924856 ps
CPU time 16.35 seconds
Started Aug 09 05:11:36 PM PDT 24
Finished Aug 09 05:11:52 PM PDT 24
Peak memory 201424 kb
Host smart-2ed29618-0062-4c97-9180-5560d6b65691
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353529146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.1353529146
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.917695639
Short name T881
Test name
Test status
Simulation time 2343219552 ps
CPU time 2.59 seconds
Started Aug 09 05:11:27 PM PDT 24
Finished Aug 09 05:11:29 PM PDT 24
Peak memory 201544 kb
Host smart-0d3f4fd7-1ba1-430c-a5a9-8f76bdc7a8ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917695639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_error
s.917695639
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.495689471
Short name T885
Test name
Test status
Simulation time 22178308723 ps
CPU time 47.23 seconds
Started Aug 09 05:11:30 PM PDT 24
Finished Aug 09 05:12:17 PM PDT 24
Peak memory 201576 kb
Host smart-89cf498d-25b8-4b64-831e-6287f3fd11ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495689471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_tl_intg_err.495689471
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.881535455
Short name T815
Test name
Test status
Simulation time 2042790398 ps
CPU time 5.91 seconds
Started Aug 09 05:11:34 PM PDT 24
Finished Aug 09 05:11:40 PM PDT 24
Peak memory 201296 kb
Host smart-7027d2c2-68ba-43cf-bf40-c8139a0ed4ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881535455 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.881535455
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3910503804
Short name T826
Test name
Test status
Simulation time 2039911946 ps
CPU time 3.19 seconds
Started Aug 09 05:11:34 PM PDT 24
Finished Aug 09 05:11:38 PM PDT 24
Peak memory 201280 kb
Host smart-c4c5ecb0-4928-4dd2-88b7-896a171e7918
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910503804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.3910503804
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3174386574
Short name T906
Test name
Test status
Simulation time 2013310298 ps
CPU time 5.59 seconds
Started Aug 09 05:11:35 PM PDT 24
Finished Aug 09 05:11:41 PM PDT 24
Peak memory 201088 kb
Host smart-6a720501-4a0e-4eca-86f6-83c13c2c3d32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174386574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.3174386574
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2565186118
Short name T873
Test name
Test status
Simulation time 5299138475 ps
CPU time 2.77 seconds
Started Aug 09 05:11:33 PM PDT 24
Finished Aug 09 05:11:36 PM PDT 24
Peak memory 201580 kb
Host smart-cd43eb72-7fa5-4d64-8068-fd177b250757
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565186118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.2565186118
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3668912229
Short name T828
Test name
Test status
Simulation time 2141389958 ps
CPU time 4.28 seconds
Started Aug 09 05:11:35 PM PDT 24
Finished Aug 09 05:11:39 PM PDT 24
Peak memory 201296 kb
Host smart-064be8b5-7dc3-4f1f-b345-8a7726f13fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668912229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.3668912229
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1626059193
Short name T354
Test name
Test status
Simulation time 22234662504 ps
CPU time 54.74 seconds
Started Aug 09 05:11:33 PM PDT 24
Finished Aug 09 05:12:28 PM PDT 24
Peak memory 201592 kb
Host smart-2c29fd35-62ad-4c86-a5e1-ee14f5a73349
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626059193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.1626059193
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3021334759
Short name T319
Test name
Test status
Simulation time 3121427778 ps
CPU time 6 seconds
Started Aug 09 05:11:06 PM PDT 24
Finished Aug 09 05:11:12 PM PDT 24
Peak memory 201528 kb
Host smart-4c8c4b05-1a85-4c8a-9ef5-77e76e8b2c69
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021334759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.3021334759
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.715527182
Short name T911
Test name
Test status
Simulation time 64949914132 ps
CPU time 40.35 seconds
Started Aug 09 05:11:04 PM PDT 24
Finished Aug 09 05:11:44 PM PDT 24
Peak memory 201500 kb
Host smart-e9815f46-3a1e-4c9c-9fdd-3c81893aeade
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715527182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_
csr_bit_bash.715527182
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1739464107
Short name T899
Test name
Test status
Simulation time 4016610779 ps
CPU time 11.42 seconds
Started Aug 09 05:11:04 PM PDT 24
Finished Aug 09 05:11:16 PM PDT 24
Peak memory 201172 kb
Host smart-f5da5c00-a215-483a-8cd2-350986d96315
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739464107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.1739464107
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2869001128
Short name T806
Test name
Test status
Simulation time 2069529921 ps
CPU time 3.26 seconds
Started Aug 09 05:11:06 PM PDT 24
Finished Aug 09 05:11:09 PM PDT 24
Peak memory 201204 kb
Host smart-a371c2c2-b67e-4eb0-9ab2-c2ff7e6f6f08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869001128 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2869001128
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.600289903
Short name T321
Test name
Test status
Simulation time 2028899766 ps
CPU time 4.56 seconds
Started Aug 09 05:11:06 PM PDT 24
Finished Aug 09 05:11:10 PM PDT 24
Peak memory 201348 kb
Host smart-5f3bb098-3b45-4214-9b5a-694d77d4b078
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600289903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw
.600289903
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.361367638
Short name T860
Test name
Test status
Simulation time 2039259573 ps
CPU time 2.09 seconds
Started Aug 09 05:11:06 PM PDT 24
Finished Aug 09 05:11:08 PM PDT 24
Peak memory 201008 kb
Host smart-f5b56ac7-66d7-4636-bdef-57980fba5357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361367638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test
.361367638
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1747874522
Short name T831
Test name
Test status
Simulation time 4931441099 ps
CPU time 10.07 seconds
Started Aug 09 05:11:05 PM PDT 24
Finished Aug 09 05:11:15 PM PDT 24
Peak memory 201508 kb
Host smart-85bb6282-dd13-452d-a1e0-d81bdd4f12e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747874522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.1747874522
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1669519258
Short name T289
Test name
Test status
Simulation time 2581824736 ps
CPU time 4.23 seconds
Started Aug 09 05:10:58 PM PDT 24
Finished Aug 09 05:11:02 PM PDT 24
Peak memory 201536 kb
Host smart-93a12807-bb84-4db5-b1f3-afaa06954852
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669519258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.1669519258
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2902593335
Short name T888
Test name
Test status
Simulation time 22525903432 ps
CPU time 13.37 seconds
Started Aug 09 05:10:58 PM PDT 24
Finished Aug 09 05:11:11 PM PDT 24
Peak memory 201616 kb
Host smart-505d22dc-1d51-4291-b257-6b6059e7d59f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902593335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.2902593335
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2593493162
Short name T800
Test name
Test status
Simulation time 2010899827 ps
CPU time 5.42 seconds
Started Aug 09 05:11:34 PM PDT 24
Finished Aug 09 05:11:39 PM PDT 24
Peak memory 201016 kb
Host smart-c4f2157d-7312-4703-b9c7-b45f5e81c1c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593493162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.2593493162
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.4236036786
Short name T824
Test name
Test status
Simulation time 2011398435 ps
CPU time 5.41 seconds
Started Aug 09 05:11:33 PM PDT 24
Finished Aug 09 05:11:39 PM PDT 24
Peak memory 201048 kb
Host smart-16ae5f1e-411a-4adb-9ac6-726b587110f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236036786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.4236036786
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2275411347
Short name T839
Test name
Test status
Simulation time 2026301931 ps
CPU time 3.29 seconds
Started Aug 09 05:11:39 PM PDT 24
Finished Aug 09 05:11:42 PM PDT 24
Peak memory 201052 kb
Host smart-175a2cde-37d1-44fa-a3ec-045dbe2c4f57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275411347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.2275411347
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1021230711
Short name T877
Test name
Test status
Simulation time 2016091633 ps
CPU time 5.75 seconds
Started Aug 09 05:11:37 PM PDT 24
Finished Aug 09 05:11:43 PM PDT 24
Peak memory 201216 kb
Host smart-05792182-b44b-4f8e-b639-a0df9e5acdf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021230711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.1021230711
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.820751973
Short name T804
Test name
Test status
Simulation time 2062772418 ps
CPU time 1.04 seconds
Started Aug 09 05:11:37 PM PDT 24
Finished Aug 09 05:11:38 PM PDT 24
Peak memory 201068 kb
Host smart-76417c62-b25e-4c13-971a-035b67faab17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820751973 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_tes
t.820751973
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1120908960
Short name T820
Test name
Test status
Simulation time 2012819278 ps
CPU time 5.28 seconds
Started Aug 09 05:11:35 PM PDT 24
Finished Aug 09 05:11:40 PM PDT 24
Peak memory 201232 kb
Host smart-b8702597-294c-440c-86af-094a639778a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120908960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.1120908960
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3302693482
Short name T825
Test name
Test status
Simulation time 2010947303 ps
CPU time 5.43 seconds
Started Aug 09 05:11:38 PM PDT 24
Finished Aug 09 05:11:44 PM PDT 24
Peak memory 201040 kb
Host smart-fb40be41-1c6d-4fd3-8492-c3c1da099c40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302693482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.3302693482
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3659655845
Short name T829
Test name
Test status
Simulation time 2011815018 ps
CPU time 5.49 seconds
Started Aug 09 05:11:33 PM PDT 24
Finished Aug 09 05:11:39 PM PDT 24
Peak memory 201208 kb
Host smart-beaacb62-ce7a-43f0-bd45-c93464476cdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659655845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.3659655845
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2486857377
Short name T840
Test name
Test status
Simulation time 2017412813 ps
CPU time 3.08 seconds
Started Aug 09 05:11:34 PM PDT 24
Finished Aug 09 05:11:38 PM PDT 24
Peak memory 200960 kb
Host smart-59c61bd3-5715-4339-8726-5962ec38cc39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486857377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te
st.2486857377
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1753372887
Short name T834
Test name
Test status
Simulation time 2038892219 ps
CPU time 2.23 seconds
Started Aug 09 05:11:38 PM PDT 24
Finished Aug 09 05:11:41 PM PDT 24
Peak memory 201048 kb
Host smart-e6987dbe-3099-4165-ba92-b73fddb475e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753372887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.1753372887
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.238814513
Short name T325
Test name
Test status
Simulation time 2996911827 ps
CPU time 5.5 seconds
Started Aug 09 05:11:05 PM PDT 24
Finished Aug 09 05:11:10 PM PDT 24
Peak memory 201520 kb
Host smart-fb19213e-d335-40ca-8b01-60bbf1bdb754
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238814513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_aliasing.238814513
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3559306123
Short name T315
Test name
Test status
Simulation time 34791307664 ps
CPU time 28.15 seconds
Started Aug 09 05:11:07 PM PDT 24
Finished Aug 09 05:11:35 PM PDT 24
Peak memory 201492 kb
Host smart-5303ee50-79dd-46aa-a4e2-f914a04f4fa9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559306123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.3559306123
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3659472409
Short name T807
Test name
Test status
Simulation time 2121632495 ps
CPU time 2.48 seconds
Started Aug 09 05:11:04 PM PDT 24
Finished Aug 09 05:11:07 PM PDT 24
Peak memory 209684 kb
Host smart-222b4dd7-680a-4cc3-9f81-6fbc9b95c79c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659472409 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3659472409
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1629191024
Short name T330
Test name
Test status
Simulation time 2064428751 ps
CPU time 5.88 seconds
Started Aug 09 05:11:05 PM PDT 24
Finished Aug 09 05:11:11 PM PDT 24
Peak memory 201340 kb
Host smart-35daaf41-9458-4aba-9e22-6c60ea90fc6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629191024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.1629191024
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1097673531
Short name T808
Test name
Test status
Simulation time 2103831806 ps
CPU time 1.04 seconds
Started Aug 09 05:11:06 PM PDT 24
Finished Aug 09 05:11:07 PM PDT 24
Peak memory 201016 kb
Host smart-5f8c54aa-c138-4c2b-bfff-c59d0a80a854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097673531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.1097673531
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2884367581
Short name T893
Test name
Test status
Simulation time 4767736384 ps
CPU time 17.61 seconds
Started Aug 09 05:11:04 PM PDT 24
Finished Aug 09 05:11:22 PM PDT 24
Peak memory 201576 kb
Host smart-b4a91943-63cf-4e50-b4af-c71623bcf26d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884367581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.2884367581
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3138819517
Short name T287
Test name
Test status
Simulation time 2048870904 ps
CPU time 3.88 seconds
Started Aug 09 05:11:06 PM PDT 24
Finished Aug 09 05:11:10 PM PDT 24
Peak memory 201444 kb
Host smart-b78db380-e5ae-48f0-9699-34e5d93c6dce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138819517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.3138819517
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.789485615
Short name T351
Test name
Test status
Simulation time 42390721036 ps
CPU time 107.97 seconds
Started Aug 09 05:11:07 PM PDT 24
Finished Aug 09 05:12:55 PM PDT 24
Peak memory 201488 kb
Host smart-55956319-d958-4bab-8f14-8fcf1d5534b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789485615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_tl_intg_err.789485615
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.537631059
Short name T794
Test name
Test status
Simulation time 2012318790 ps
CPU time 5.52 seconds
Started Aug 09 05:11:35 PM PDT 24
Finished Aug 09 05:11:40 PM PDT 24
Peak memory 201176 kb
Host smart-23fe6e27-ce2c-495d-b884-9bdfe59e033f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537631059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_tes
t.537631059
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2164819801
Short name T798
Test name
Test status
Simulation time 2024580199 ps
CPU time 2.39 seconds
Started Aug 09 05:11:33 PM PDT 24
Finished Aug 09 05:11:36 PM PDT 24
Peak memory 201164 kb
Host smart-f5ce1f44-828d-4e00-8e41-3a0c916c708b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164819801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.2164819801
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.911454118
Short name T875
Test name
Test status
Simulation time 2011871444 ps
CPU time 5.7 seconds
Started Aug 09 05:11:34 PM PDT 24
Finished Aug 09 05:11:39 PM PDT 24
Peak memory 201024 kb
Host smart-670f6298-196c-49d5-9bf6-e189278b7756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911454118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_tes
t.911454118
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.3632328611
Short name T812
Test name
Test status
Simulation time 2012146091 ps
CPU time 5.46 seconds
Started Aug 09 05:11:33 PM PDT 24
Finished Aug 09 05:11:39 PM PDT 24
Peak memory 201136 kb
Host smart-8ec334ea-0bf7-426d-ada2-8c9f229d7d28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632328611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.3632328611
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3619534110
Short name T797
Test name
Test status
Simulation time 2013591581 ps
CPU time 6.02 seconds
Started Aug 09 05:11:35 PM PDT 24
Finished Aug 09 05:11:42 PM PDT 24
Peak memory 201068 kb
Host smart-743f62af-c56b-4fd4-856e-e13a943b28e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619534110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.3619534110
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3776725058
Short name T818
Test name
Test status
Simulation time 2013714428 ps
CPU time 6.08 seconds
Started Aug 09 05:11:35 PM PDT 24
Finished Aug 09 05:11:41 PM PDT 24
Peak memory 201004 kb
Host smart-3b0b35f9-000a-4bf7-8052-050915e2c662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776725058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.3776725058
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.3517097424
Short name T894
Test name
Test status
Simulation time 2012440757 ps
CPU time 5.35 seconds
Started Aug 09 05:11:36 PM PDT 24
Finished Aug 09 05:11:41 PM PDT 24
Peak memory 201220 kb
Host smart-6f644eb4-dc4f-4579-9ab7-2ef257d0a18d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517097424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.3517097424
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.92848951
Short name T835
Test name
Test status
Simulation time 2139212264 ps
CPU time 0.94 seconds
Started Aug 09 05:11:33 PM PDT 24
Finished Aug 09 05:11:34 PM PDT 24
Peak memory 201092 kb
Host smart-806b7fd0-7016-4c6d-9052-aa73f9ed74d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92848951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_test
.92848951
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3320942715
Short name T796
Test name
Test status
Simulation time 2016500314 ps
CPU time 3.14 seconds
Started Aug 09 05:11:33 PM PDT 24
Finished Aug 09 05:11:37 PM PDT 24
Peak memory 201104 kb
Host smart-0b209e69-10b8-435f-aea1-0c478e3de047
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320942715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te
st.3320942715
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.1497973018
Short name T853
Test name
Test status
Simulation time 2032679762 ps
CPU time 1.92 seconds
Started Aug 09 05:11:34 PM PDT 24
Finished Aug 09 05:11:36 PM PDT 24
Peak memory 201156 kb
Host smart-cfac175c-f9d6-4342-812a-9b12c8a1e252
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497973018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.1497973018
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3850737796
Short name T892
Test name
Test status
Simulation time 2693551728 ps
CPU time 4.61 seconds
Started Aug 09 05:11:05 PM PDT 24
Finished Aug 09 05:11:10 PM PDT 24
Peak memory 201528 kb
Host smart-d6138f43-3070-42a3-8857-71373ec6b3b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850737796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_aliasing.3850737796
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1535845734
Short name T316
Test name
Test status
Simulation time 70260809433 ps
CPU time 76.55 seconds
Started Aug 09 05:11:09 PM PDT 24
Finished Aug 09 05:12:25 PM PDT 24
Peak memory 201868 kb
Host smart-4a552a36-4e46-4721-8b1e-a1c960414307
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535845734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.1535845734
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.3065083207
Short name T322
Test name
Test status
Simulation time 4045161594 ps
CPU time 6.03 seconds
Started Aug 09 05:11:09 PM PDT 24
Finished Aug 09 05:11:15 PM PDT 24
Peak memory 201636 kb
Host smart-c6511e60-f282-4843-844d-ff94f9a02003
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065083207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_hw_reset.3065083207
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1451037267
Short name T862
Test name
Test status
Simulation time 2092568431 ps
CPU time 4.75 seconds
Started Aug 09 05:11:15 PM PDT 24
Finished Aug 09 05:11:20 PM PDT 24
Peak memory 201164 kb
Host smart-73ce557b-938e-4988-9e73-cef83f0f6015
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451037267 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1451037267
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2536161384
Short name T837
Test name
Test status
Simulation time 2044885044 ps
CPU time 2 seconds
Started Aug 09 05:11:05 PM PDT 24
Finished Aug 09 05:11:07 PM PDT 24
Peak memory 201380 kb
Host smart-f1dd5830-c73b-452e-8b7d-2be178c7f3f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536161384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.2536161384
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.2509013066
Short name T856
Test name
Test status
Simulation time 2019172059 ps
CPU time 3.02 seconds
Started Aug 09 05:11:04 PM PDT 24
Finished Aug 09 05:11:07 PM PDT 24
Peak memory 201064 kb
Host smart-09eb856d-dbbf-4548-accd-30452e4a15f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509013066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.2509013066
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.3570299454
Short name T851
Test name
Test status
Simulation time 8553240357 ps
CPU time 7.02 seconds
Started Aug 09 05:11:15 PM PDT 24
Finished Aug 09 05:11:22 PM PDT 24
Peak memory 201572 kb
Host smart-7ba89bf2-4563-4740-a210-8f23cb587a2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570299454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.3570299454
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3514917939
Short name T283
Test name
Test status
Simulation time 2075494694 ps
CPU time 6.81 seconds
Started Aug 09 05:11:06 PM PDT 24
Finished Aug 09 05:11:13 PM PDT 24
Peak memory 201460 kb
Host smart-8e089889-67e3-4f11-9369-c6442d3987fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514917939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.3514917939
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.2687311168
Short name T805
Test name
Test status
Simulation time 2013792420 ps
CPU time 6.14 seconds
Started Aug 09 05:11:36 PM PDT 24
Finished Aug 09 05:11:42 PM PDT 24
Peak memory 201180 kb
Host smart-a4515d02-6875-44fd-8994-7baddc9a6832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687311168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.2687311168
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.1052554959
Short name T913
Test name
Test status
Simulation time 2020944303 ps
CPU time 2.2 seconds
Started Aug 09 05:11:49 PM PDT 24
Finished Aug 09 05:11:52 PM PDT 24
Peak memory 200976 kb
Host smart-d0f45386-d69f-4273-b36d-499bbb6ea1d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052554959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.1052554959
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.3327952590
Short name T801
Test name
Test status
Simulation time 2010598099 ps
CPU time 5.82 seconds
Started Aug 09 05:11:39 PM PDT 24
Finished Aug 09 05:11:45 PM PDT 24
Peak memory 201108 kb
Host smart-cf4058cc-0ea0-46a6-be6a-4ee7d2f45f54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327952590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.3327952590
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.255222667
Short name T849
Test name
Test status
Simulation time 2020472154 ps
CPU time 3.29 seconds
Started Aug 09 05:11:50 PM PDT 24
Finished Aug 09 05:11:53 PM PDT 24
Peak memory 200968 kb
Host smart-46f6e291-6159-40a2-9e9d-2c10893b7e7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255222667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_tes
t.255222667
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2608705483
Short name T799
Test name
Test status
Simulation time 2023131848 ps
CPU time 2.31 seconds
Started Aug 09 05:11:41 PM PDT 24
Finished Aug 09 05:11:43 PM PDT 24
Peak memory 201148 kb
Host smart-58f21ef4-9c72-4b01-ba62-e0eac914405a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608705483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.2608705483
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1463278190
Short name T866
Test name
Test status
Simulation time 2012813713 ps
CPU time 5.76 seconds
Started Aug 09 05:11:41 PM PDT 24
Finished Aug 09 05:11:47 PM PDT 24
Peak memory 201116 kb
Host smart-7190b984-d656-4cdd-8c20-178146a894b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463278190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.1463278190
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1741113512
Short name T872
Test name
Test status
Simulation time 2043152003 ps
CPU time 1.55 seconds
Started Aug 09 05:11:42 PM PDT 24
Finished Aug 09 05:11:43 PM PDT 24
Peak memory 201160 kb
Host smart-cc84a44f-c211-4fe2-b991-c3608294a003
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741113512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.1741113512
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.486231448
Short name T802
Test name
Test status
Simulation time 2019680580 ps
CPU time 3.12 seconds
Started Aug 09 05:11:42 PM PDT 24
Finished Aug 09 05:11:45 PM PDT 24
Peak memory 201240 kb
Host smart-f3c6048e-462d-4501-9cd0-328ab59f8fa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486231448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_tes
t.486231448
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1332021149
Short name T844
Test name
Test status
Simulation time 2026012950 ps
CPU time 2.23 seconds
Started Aug 09 05:11:43 PM PDT 24
Finished Aug 09 05:11:45 PM PDT 24
Peak memory 200940 kb
Host smart-25ed87f1-e6ed-49a7-a660-8667fbb119e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332021149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.1332021149
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3164647008
Short name T890
Test name
Test status
Simulation time 2039030849 ps
CPU time 1.95 seconds
Started Aug 09 05:11:40 PM PDT 24
Finished Aug 09 05:11:43 PM PDT 24
Peak memory 201052 kb
Host smart-2a92c7db-f79e-47c0-b643-e1fc03c54012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164647008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.3164647008
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.342552454
Short name T286
Test name
Test status
Simulation time 2066687317 ps
CPU time 4.7 seconds
Started Aug 09 05:11:15 PM PDT 24
Finished Aug 09 05:11:20 PM PDT 24
Peak memory 201324 kb
Host smart-c7007a95-da21-454c-9bbd-89ee9befee2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342552454 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.342552454
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.81347797
Short name T323
Test name
Test status
Simulation time 2033368463 ps
CPU time 3.65 seconds
Started Aug 09 05:11:11 PM PDT 24
Finished Aug 09 05:11:15 PM PDT 24
Peak memory 201184 kb
Host smart-00065a93-eb3f-4ef6-a859-650bf84ff75b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81347797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw.81347797
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.696445883
Short name T841
Test name
Test status
Simulation time 2049396283 ps
CPU time 1.87 seconds
Started Aug 09 05:11:15 PM PDT 24
Finished Aug 09 05:11:17 PM PDT 24
Peak memory 201012 kb
Host smart-cd369f58-070b-414c-8526-0fe8c4d705e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696445883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test
.696445883
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1477660201
Short name T904
Test name
Test status
Simulation time 9786050560 ps
CPU time 13.47 seconds
Started Aug 09 05:11:14 PM PDT 24
Finished Aug 09 05:11:28 PM PDT 24
Peak memory 201620 kb
Host smart-7823606b-bb93-4330-be34-0823e7d463a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477660201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.1477660201
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2393209216
Short name T850
Test name
Test status
Simulation time 2375114791 ps
CPU time 3.65 seconds
Started Aug 09 05:11:11 PM PDT 24
Finished Aug 09 05:11:15 PM PDT 24
Peak memory 201564 kb
Host smart-6948fc37-2602-4830-a17f-a87350673200
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393209216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.2393209216
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.624118599
Short name T883
Test name
Test status
Simulation time 42550428038 ps
CPU time 28.56 seconds
Started Aug 09 05:11:12 PM PDT 24
Finished Aug 09 05:11:41 PM PDT 24
Peak memory 201496 kb
Host smart-c428988e-529a-4670-abc7-044e2c1c49b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624118599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_tl_intg_err.624118599
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3238487302
Short name T823
Test name
Test status
Simulation time 2081777619 ps
CPU time 2.07 seconds
Started Aug 09 05:11:13 PM PDT 24
Finished Aug 09 05:11:16 PM PDT 24
Peak memory 201304 kb
Host smart-6e42ce1e-8ea0-47d7-ac4a-a9be2d1b1ef9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238487302 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3238487302
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.832717967
Short name T865
Test name
Test status
Simulation time 2072332334 ps
CPU time 1.4 seconds
Started Aug 09 05:11:15 PM PDT 24
Finished Aug 09 05:11:16 PM PDT 24
Peak memory 200952 kb
Host smart-4bbc170a-b216-4e70-b67a-854a93885d3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832717967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw
.832717967
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.3592197119
Short name T887
Test name
Test status
Simulation time 2013135316 ps
CPU time 5.63 seconds
Started Aug 09 05:11:14 PM PDT 24
Finished Aug 09 05:11:20 PM PDT 24
Peak memory 201012 kb
Host smart-0520db4c-b71d-498a-8dd0-0e71d7093f64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592197119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.3592197119
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.1668595955
Short name T836
Test name
Test status
Simulation time 7169948326 ps
CPU time 15.98 seconds
Started Aug 09 05:11:12 PM PDT 24
Finished Aug 09 05:11:28 PM PDT 24
Peak memory 201572 kb
Host smart-3fcd16c4-905a-421c-9ed3-78e7721886b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668595955 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.1668595955
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.4224209181
Short name T905
Test name
Test status
Simulation time 2131840896 ps
CPU time 8.18 seconds
Started Aug 09 05:11:14 PM PDT 24
Finished Aug 09 05:11:23 PM PDT 24
Peak memory 201368 kb
Host smart-c5608f0f-8d1c-4477-8025-58950e51a91e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224209181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.4224209181
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3932458814
Short name T281
Test name
Test status
Simulation time 22235138801 ps
CPU time 53.32 seconds
Started Aug 09 05:11:12 PM PDT 24
Finished Aug 09 05:12:05 PM PDT 24
Peak memory 201656 kb
Host smart-c2c4e1dd-ba57-49a7-8ed9-bf782a418551
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932458814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.3932458814
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3118136116
Short name T886
Test name
Test status
Simulation time 2085338712 ps
CPU time 2.19 seconds
Started Aug 09 05:11:15 PM PDT 24
Finished Aug 09 05:11:18 PM PDT 24
Peak memory 201292 kb
Host smart-0da1c00b-1d8b-498e-a433-f75aedd3e508
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118136116 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3118136116
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.1680372092
Short name T880
Test name
Test status
Simulation time 2049687123 ps
CPU time 2.03 seconds
Started Aug 09 05:11:13 PM PDT 24
Finished Aug 09 05:11:15 PM PDT 24
Peak memory 201224 kb
Host smart-e17a5208-1bd6-4658-87fd-7151b1606508
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680372092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.1680372092
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.192337467
Short name T855
Test name
Test status
Simulation time 2039355479 ps
CPU time 1.7 seconds
Started Aug 09 05:11:15 PM PDT 24
Finished Aug 09 05:11:17 PM PDT 24
Peak memory 201052 kb
Host smart-e4c0e53f-f634-442d-a19c-3b3b243e43d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192337467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test
.192337467
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2876494543
Short name T328
Test name
Test status
Simulation time 7873455740 ps
CPU time 3.12 seconds
Started Aug 09 05:11:12 PM PDT 24
Finished Aug 09 05:11:15 PM PDT 24
Peak memory 201512 kb
Host smart-a7d64298-ad01-448f-95fa-87f493405304
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876494543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.2876494543
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.3895065988
Short name T908
Test name
Test status
Simulation time 2082428855 ps
CPU time 6.62 seconds
Started Aug 09 05:11:12 PM PDT 24
Finished Aug 09 05:11:19 PM PDT 24
Peak memory 201440 kb
Host smart-9b4d71db-5900-4291-b6f3-8537b5d1abba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895065988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.3895065988
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3931010121
Short name T27
Test name
Test status
Simulation time 22424831563 ps
CPU time 14.99 seconds
Started Aug 09 05:11:12 PM PDT 24
Finished Aug 09 05:11:28 PM PDT 24
Peak memory 201660 kb
Host smart-781ad49d-a158-4a46-9b92-cd0b7c5b8787
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931010121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.3931010121
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.1988499382
Short name T25
Test name
Test status
Simulation time 2092151026 ps
CPU time 2.1 seconds
Started Aug 09 05:11:12 PM PDT 24
Finished Aug 09 05:11:15 PM PDT 24
Peak memory 201320 kb
Host smart-596ac733-c0f7-476c-a053-a8bb04c556ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988499382 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.1988499382
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3452932092
Short name T314
Test name
Test status
Simulation time 2084733039 ps
CPU time 1.89 seconds
Started Aug 09 05:11:13 PM PDT 24
Finished Aug 09 05:11:15 PM PDT 24
Peak memory 201164 kb
Host smart-61453083-8d06-4075-a784-96e2129fce9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452932092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.3452932092
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.188570845
Short name T900
Test name
Test status
Simulation time 2010023933 ps
CPU time 5.56 seconds
Started Aug 09 05:11:15 PM PDT 24
Finished Aug 09 05:11:21 PM PDT 24
Peak memory 200852 kb
Host smart-ebf64133-9b8e-431d-9026-015e3f8f2465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188570845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test
.188570845
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3977723214
Short name T870
Test name
Test status
Simulation time 4909182118 ps
CPU time 3.8 seconds
Started Aug 09 05:11:15 PM PDT 24
Finished Aug 09 05:11:19 PM PDT 24
Peak memory 201464 kb
Host smart-1fab9899-b2b1-4603-8ce0-2e85bcc9b21f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977723214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.3977723214
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.657151769
Short name T867
Test name
Test status
Simulation time 2044598300 ps
CPU time 7.94 seconds
Started Aug 09 05:11:14 PM PDT 24
Finished Aug 09 05:11:22 PM PDT 24
Peak memory 201360 kb
Host smart-f54ce4dc-902e-47f4-a490-b195c8271896
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657151769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors
.657151769
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3524131472
Short name T848
Test name
Test status
Simulation time 42500232788 ps
CPU time 58.7 seconds
Started Aug 09 05:11:14 PM PDT 24
Finished Aug 09 05:12:13 PM PDT 24
Peak memory 201580 kb
Host smart-dcf3979f-9efb-48a3-99ae-01793da0855d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524131472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.3524131472
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3310044875
Short name T878
Test name
Test status
Simulation time 2096790009 ps
CPU time 2.82 seconds
Started Aug 09 05:11:19 PM PDT 24
Finished Aug 09 05:11:22 PM PDT 24
Peak memory 209660 kb
Host smart-0cea7816-d350-4bc7-a50a-0ae1f6083f04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310044875 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3310044875
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.1189692025
Short name T318
Test name
Test status
Simulation time 2064206748 ps
CPU time 3.54 seconds
Started Aug 09 05:11:23 PM PDT 24
Finished Aug 09 05:11:27 PM PDT 24
Peak memory 201280 kb
Host smart-d2361473-b9a4-48d7-93ce-784e641e83ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189692025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.1189692025
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3023662826
Short name T822
Test name
Test status
Simulation time 2041055078 ps
CPU time 1.88 seconds
Started Aug 09 05:11:22 PM PDT 24
Finished Aug 09 05:11:24 PM PDT 24
Peak memory 201376 kb
Host smart-9db8da7f-235b-4c59-938a-1815f1aa3a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023662826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.3023662826
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.923772283
Short name T813
Test name
Test status
Simulation time 7064881290 ps
CPU time 5.26 seconds
Started Aug 09 05:11:22 PM PDT 24
Finished Aug 09 05:11:27 PM PDT 24
Peak memory 201616 kb
Host smart-dd3af9c3-5b81-4c56-b839-9841228ea34c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923772283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
sysrst_ctrl_same_csr_outstanding.923772283
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1959240562
Short name T285
Test name
Test status
Simulation time 2148275837 ps
CPU time 3.53 seconds
Started Aug 09 05:11:14 PM PDT 24
Finished Aug 09 05:11:18 PM PDT 24
Peak memory 209668 kb
Host smart-e1c58dc0-fde2-4bbe-b28d-7e7f2a7e493b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959240562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.1959240562
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3712992672
Short name T352
Test name
Test status
Simulation time 23733053464 ps
CPU time 5.3 seconds
Started Aug 09 05:11:13 PM PDT 24
Finished Aug 09 05:11:18 PM PDT 24
Peak memory 201576 kb
Host smart-c0860050-9566-4b2f-a459-df58c318fed1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712992672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.3712992672
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.3580651678
Short name T645
Test name
Test status
Simulation time 2011514184 ps
CPU time 5.35 seconds
Started Aug 09 05:12:38 PM PDT 24
Finished Aug 09 05:12:44 PM PDT 24
Peak memory 200824 kb
Host smart-f39650a4-c569-410d-818c-6605c6fd90f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580651678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_tes
t.3580651678
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1540579282
Short name T593
Test name
Test status
Simulation time 3529532274 ps
CPU time 1.6 seconds
Started Aug 09 05:12:33 PM PDT 24
Finished Aug 09 05:12:35 PM PDT 24
Peak memory 200784 kb
Host smart-bb3194c9-9a89-44ac-b29c-4e79248be299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540579282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.1540579282
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.2823319895
Short name T91
Test name
Test status
Simulation time 130031382980 ps
CPU time 172.48 seconds
Started Aug 09 05:12:35 PM PDT 24
Finished Aug 09 05:15:28 PM PDT 24
Peak memory 200948 kb
Host smart-ebdea38c-782c-4bea-89d2-fe606bc9b7d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823319895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_combo_detect.2823319895
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.224008911
Short name T590
Test name
Test status
Simulation time 2434675762 ps
CPU time 7.16 seconds
Started Aug 09 05:12:35 PM PDT 24
Finished Aug 09 05:12:42 PM PDT 24
Peak memory 200736 kb
Host smart-00fcd965-921d-4cba-8f91-e46f74faac46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224008911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.224008911
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1094564889
Short name T468
Test name
Test status
Simulation time 2395849180 ps
CPU time 1.9 seconds
Started Aug 09 05:12:37 PM PDT 24
Finished Aug 09 05:12:39 PM PDT 24
Peak memory 200772 kb
Host smart-de7b28a4-0d42-4e8d-82dc-084fcab755f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094564889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1094564889
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1278415277
Short name T372
Test name
Test status
Simulation time 60196121961 ps
CPU time 151.08 seconds
Started Aug 09 05:12:39 PM PDT 24
Finished Aug 09 05:15:10 PM PDT 24
Peak memory 201088 kb
Host smart-5bfb4863-bbde-43a9-9a47-a00e75e55709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278415277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.1278415277
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.2997229242
Short name T55
Test name
Test status
Simulation time 2995435154 ps
CPU time 7.8 seconds
Started Aug 09 05:12:35 PM PDT 24
Finished Aug 09 05:12:43 PM PDT 24
Peak memory 200640 kb
Host smart-2d038271-c860-4736-ba06-fe5042f1ecc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997229242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ec_pwr_on_rst.2997229242
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.1718399340
Short name T162
Test name
Test status
Simulation time 3450169092 ps
CPU time 2.93 seconds
Started Aug 09 05:12:35 PM PDT 24
Finished Aug 09 05:12:38 PM PDT 24
Peak memory 200824 kb
Host smart-db52f14b-bc1a-482c-8d3c-14a3cace4c98
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718399340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.1718399340
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.2844615793
Short name T663
Test name
Test status
Simulation time 2612877084 ps
CPU time 5.12 seconds
Started Aug 09 05:12:35 PM PDT 24
Finished Aug 09 05:12:40 PM PDT 24
Peak memory 200732 kb
Host smart-f834bf0d-9953-4c45-84d7-21d6345cd2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844615793 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.2844615793
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.3041944383
Short name T585
Test name
Test status
Simulation time 2472966738 ps
CPU time 2 seconds
Started Aug 09 05:12:37 PM PDT 24
Finished Aug 09 05:12:39 PM PDT 24
Peak memory 200696 kb
Host smart-e1a39656-7dcc-4a8a-96b7-652f9e688db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041944383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.3041944383
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.998422629
Short name T481
Test name
Test status
Simulation time 2151191079 ps
CPU time 3.6 seconds
Started Aug 09 05:12:38 PM PDT 24
Finished Aug 09 05:12:42 PM PDT 24
Peak memory 200820 kb
Host smart-d85025be-c22a-4d2f-8fe6-afdb6982d033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998422629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.998422629
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.2453573473
Short name T454
Test name
Test status
Simulation time 2517891237 ps
CPU time 3.58 seconds
Started Aug 09 05:12:36 PM PDT 24
Finished Aug 09 05:12:39 PM PDT 24
Peak memory 200788 kb
Host smart-57a541b1-e869-4637-9ec9-d5e236752c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453573473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.2453573473
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.955213115
Short name T291
Test name
Test status
Simulation time 22195738156 ps
CPU time 7.93 seconds
Started Aug 09 05:12:36 PM PDT 24
Finished Aug 09 05:12:44 PM PDT 24
Peak memory 220624 kb
Host smart-e146e45b-73c9-4065-bb3f-8e4c1994d85a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955213115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.955213115
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.2882335068
Short name T393
Test name
Test status
Simulation time 2120836099 ps
CPU time 3.04 seconds
Started Aug 09 05:12:35 PM PDT 24
Finished Aug 09 05:12:38 PM PDT 24
Peak memory 200716 kb
Host smart-606ec299-0813-4ac3-9dfc-7476815942af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882335068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.2882335068
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.2456469814
Short name T517
Test name
Test status
Simulation time 17986901834 ps
CPU time 37.41 seconds
Started Aug 09 05:12:34 PM PDT 24
Finished Aug 09 05:13:12 PM PDT 24
Peak memory 200792 kb
Host smart-1ccd3b06-1686-40d5-bd9a-1f13114656b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456469814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.2456469814
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1256873224
Short name T117
Test name
Test status
Simulation time 27614371871 ps
CPU time 52.53 seconds
Started Aug 09 05:12:39 PM PDT 24
Finished Aug 09 05:13:31 PM PDT 24
Peak memory 209308 kb
Host smart-8fe45560-5889-4dc1-a33f-fc32917a42ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256873224 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.1256873224
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.3303105790
Short name T512
Test name
Test status
Simulation time 2012563152 ps
CPU time 5.56 seconds
Started Aug 09 05:12:41 PM PDT 24
Finished Aug 09 05:12:47 PM PDT 24
Peak memory 200760 kb
Host smart-05dc2866-b47a-4b51-b331-92785924ca4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303105790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.3303105790
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.521769055
Short name T429
Test name
Test status
Simulation time 3763408209 ps
CPU time 2.92 seconds
Started Aug 09 05:12:44 PM PDT 24
Finished Aug 09 05:12:47 PM PDT 24
Peak memory 200820 kb
Host smart-51d44e9a-3f83-457b-a970-5517d68241b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521769055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.521769055
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.304534459
Short name T382
Test name
Test status
Simulation time 163821064199 ps
CPU time 382.77 seconds
Started Aug 09 05:12:42 PM PDT 24
Finished Aug 09 05:19:05 PM PDT 24
Peak memory 201044 kb
Host smart-9e5a6e1f-0976-4122-9fdb-9fa06f7df2cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304534459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_combo_detect.304534459
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.1317572106
Short name T110
Test name
Test status
Simulation time 2189188222 ps
CPU time 1.98 seconds
Started Aug 09 05:12:34 PM PDT 24
Finished Aug 09 05:12:36 PM PDT 24
Peak memory 200748 kb
Host smart-b3caac68-2065-47e2-9584-89ca2471b9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317572106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.1317572106
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.646044623
Short name T508
Test name
Test status
Simulation time 2263500143 ps
CPU time 4.09 seconds
Started Aug 09 05:12:34 PM PDT 24
Finished Aug 09 05:12:39 PM PDT 24
Peak memory 200716 kb
Host smart-91e9524f-3755-40bc-9b30-d68b061687ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646044623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.646044623
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.2659803721
Short name T519
Test name
Test status
Simulation time 4529289088 ps
CPU time 3.37 seconds
Started Aug 09 05:12:40 PM PDT 24
Finished Aug 09 05:12:44 PM PDT 24
Peak memory 200768 kb
Host smart-37d6b8ea-9484-49b9-8219-49177282effe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659803721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.2659803721
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.3594178483
Short name T231
Test name
Test status
Simulation time 3279339194 ps
CPU time 4.4 seconds
Started Aug 09 05:12:41 PM PDT 24
Finished Aug 09 05:12:46 PM PDT 24
Peak memory 200864 kb
Host smart-4072ad94-08bc-4ff0-bdd6-931d462b4457
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594178483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.3594178483
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.1919884135
Short name T75
Test name
Test status
Simulation time 33566491541 ps
CPU time 82.24 seconds
Started Aug 09 05:12:40 PM PDT 24
Finished Aug 09 05:14:02 PM PDT 24
Peak memory 200784 kb
Host smart-9a74f757-7cdc-4891-b2e9-495f5b67696a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919884135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.1919884135
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.2735379266
Short name T250
Test name
Test status
Simulation time 2616489187 ps
CPU time 4.32 seconds
Started Aug 09 05:12:44 PM PDT 24
Finished Aug 09 05:12:49 PM PDT 24
Peak memory 200820 kb
Host smart-e7db2156-2b93-4bda-8319-fdb2ddb888ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735379266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.2735379266
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.2750871671
Short name T604
Test name
Test status
Simulation time 2473980296 ps
CPU time 2.24 seconds
Started Aug 09 05:12:37 PM PDT 24
Finished Aug 09 05:12:39 PM PDT 24
Peak memory 200832 kb
Host smart-3b9ba408-2bad-4a53-a4c5-24c9c34cff11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750871671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.2750871671
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.458367131
Short name T779
Test name
Test status
Simulation time 2045879750 ps
CPU time 1.92 seconds
Started Aug 09 05:12:34 PM PDT 24
Finished Aug 09 05:12:36 PM PDT 24
Peak memory 200672 kb
Host smart-94ffb8ab-2b59-42c2-b8ac-13b44515027e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458367131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.458367131
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.2532900197
Short name T678
Test name
Test status
Simulation time 2649775746 ps
CPU time 1.16 seconds
Started Aug 09 05:12:35 PM PDT 24
Finished Aug 09 05:12:36 PM PDT 24
Peak memory 200704 kb
Host smart-a92e5793-286a-4599-a95a-edc77527919e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532900197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.2532900197
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.98280389
Short name T280
Test name
Test status
Simulation time 42011163483 ps
CPU time 108.11 seconds
Started Aug 09 05:12:42 PM PDT 24
Finished Aug 09 05:14:30 PM PDT 24
Peak memory 220628 kb
Host smart-f9f32127-4ec8-46c7-b75b-939b81d070e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98280389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.98280389
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.3544125376
Short name T418
Test name
Test status
Simulation time 2109409530 ps
CPU time 6.05 seconds
Started Aug 09 05:12:36 PM PDT 24
Finished Aug 09 05:12:42 PM PDT 24
Peak memory 200640 kb
Host smart-9b312804-7582-4e5c-992c-752786308204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544125376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.3544125376
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.4209082701
Short name T82
Test name
Test status
Simulation time 83641415604 ps
CPU time 7.1 seconds
Started Aug 09 05:12:41 PM PDT 24
Finished Aug 09 05:12:49 PM PDT 24
Peak memory 200876 kb
Host smart-7a2fc51f-4abd-4ba6-bc69-6e7cd0ef1db4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209082701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.4209082701
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.1368912820
Short name T524
Test name
Test status
Simulation time 8820196100 ps
CPU time 9.29 seconds
Started Aug 09 05:12:42 PM PDT 24
Finished Aug 09 05:12:51 PM PDT 24
Peak memory 200772 kb
Host smart-3c69520f-3e4b-4471-81e2-2c1c24226adf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368912820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.1368912820
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.2601122127
Short name T717
Test name
Test status
Simulation time 2036135379 ps
CPU time 1.89 seconds
Started Aug 09 05:13:10 PM PDT 24
Finished Aug 09 05:13:12 PM PDT 24
Peak memory 200676 kb
Host smart-c4d8cd98-6548-430a-a8d9-2a04ebc3862c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601122127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.2601122127
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.808514478
Short name T484
Test name
Test status
Simulation time 204633202310 ps
CPU time 134.35 seconds
Started Aug 09 05:13:10 PM PDT 24
Finished Aug 09 05:15:24 PM PDT 24
Peak memory 200900 kb
Host smart-cb198513-0506-4bb7-b244-f5c168bffb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808514478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.808514478
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2800445924
Short name T639
Test name
Test status
Simulation time 3334917350 ps
CPU time 9.2 seconds
Started Aug 09 05:13:09 PM PDT 24
Finished Aug 09 05:13:19 PM PDT 24
Peak memory 200792 kb
Host smart-fda6a5f7-5bec-4303-836b-08d1d0bfb8e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800445924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.2800445924
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.4018193865
Short name T783
Test name
Test status
Simulation time 3916155196 ps
CPU time 2.5 seconds
Started Aug 09 05:13:08 PM PDT 24
Finished Aug 09 05:13:11 PM PDT 24
Peak memory 200808 kb
Host smart-16130e7d-276d-49eb-b1ef-084fe12f86bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018193865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_edge_detect.4018193865
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.4174801194
Short name T558
Test name
Test status
Simulation time 2688500475 ps
CPU time 1.15 seconds
Started Aug 09 05:13:07 PM PDT 24
Finished Aug 09 05:13:08 PM PDT 24
Peak memory 200748 kb
Host smart-7a97bd95-da80-4530-b0a5-54745d50eb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174801194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.4174801194
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.623589625
Short name T434
Test name
Test status
Simulation time 2483000403 ps
CPU time 2.37 seconds
Started Aug 09 05:13:10 PM PDT 24
Finished Aug 09 05:13:12 PM PDT 24
Peak memory 200764 kb
Host smart-ab5ce50e-ca35-4510-8836-c3e5496e166e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623589625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.623589625
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.2044780649
Short name T761
Test name
Test status
Simulation time 2195550008 ps
CPU time 1.98 seconds
Started Aug 09 05:13:10 PM PDT 24
Finished Aug 09 05:13:12 PM PDT 24
Peak memory 200736 kb
Host smart-a3da539e-0a9d-49d0-a152-3e4d18fd6c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044780649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.2044780649
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.50264756
Short name T652
Test name
Test status
Simulation time 2519971795 ps
CPU time 4.15 seconds
Started Aug 09 05:13:10 PM PDT 24
Finished Aug 09 05:13:15 PM PDT 24
Peak memory 200724 kb
Host smart-ecdb0687-f27a-4fca-80a6-92e599b6bc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50264756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.50264756
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.2970180760
Short name T423
Test name
Test status
Simulation time 2182538520 ps
CPU time 1.11 seconds
Started Aug 09 05:13:11 PM PDT 24
Finished Aug 09 05:13:12 PM PDT 24
Peak memory 200756 kb
Host smart-38f2294b-6aba-4aa9-b447-004246a99679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970180760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.2970180760
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.4255023896
Short name T571
Test name
Test status
Simulation time 123300477789 ps
CPU time 57.89 seconds
Started Aug 09 05:13:07 PM PDT 24
Finished Aug 09 05:14:05 PM PDT 24
Peak memory 201012 kb
Host smart-c504d361-a21b-486a-9681-b2f1b197dbdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255023896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.4255023896
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.3481047268
Short name T183
Test name
Test status
Simulation time 65775256080 ps
CPU time 41.64 seconds
Started Aug 09 05:13:07 PM PDT 24
Finished Aug 09 05:13:49 PM PDT 24
Peak memory 209352 kb
Host smart-0b9c2b10-9c5e-4b78-a36d-a9e3dee0f38a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481047268 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.3481047268
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3529962129
Short name T242
Test name
Test status
Simulation time 3175895060 ps
CPU time 6.17 seconds
Started Aug 09 05:13:08 PM PDT 24
Finished Aug 09 05:13:14 PM PDT 24
Peak memory 200860 kb
Host smart-9e8cfd9c-9d3d-43b4-9a8a-e9006f741853
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529962129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.3529962129
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.2711259482
Short name T488
Test name
Test status
Simulation time 2013838705 ps
CPU time 5.46 seconds
Started Aug 09 05:13:14 PM PDT 24
Finished Aug 09 05:13:19 PM PDT 24
Peak memory 200724 kb
Host smart-525dbc60-dc9d-4287-a3dd-3746d0fd360b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711259482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.2711259482
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2803984607
Short name T557
Test name
Test status
Simulation time 3922407116 ps
CPU time 5.33 seconds
Started Aug 09 05:13:07 PM PDT 24
Finished Aug 09 05:13:12 PM PDT 24
Peak memory 200824 kb
Host smart-c5edeb7f-7ea3-4d31-99fc-f528c885ab59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803984607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.2
803984607
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.458629599
Short name T333
Test name
Test status
Simulation time 101300200550 ps
CPU time 246.06 seconds
Started Aug 09 05:13:09 PM PDT 24
Finished Aug 09 05:17:15 PM PDT 24
Peak memory 201028 kb
Host smart-89200f72-7753-43b2-9ac0-c157f5fc6fb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458629599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_combo_detect.458629599
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.2268241853
Short name T696
Test name
Test status
Simulation time 2952943003 ps
CPU time 4.16 seconds
Started Aug 09 05:13:09 PM PDT 24
Finished Aug 09 05:13:13 PM PDT 24
Peak memory 200812 kb
Host smart-1302ac9d-e6e1-4d85-9ff9-6ce610e96035
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268241853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ec_pwr_on_rst.2268241853
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.595997454
Short name T644
Test name
Test status
Simulation time 3360630764 ps
CPU time 4.67 seconds
Started Aug 09 05:13:10 PM PDT 24
Finished Aug 09 05:13:15 PM PDT 24
Peak memory 200848 kb
Host smart-99294e92-320e-472c-b880-52a3ec24d024
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595997454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctr
l_edge_detect.595997454
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.2651429276
Short name T190
Test name
Test status
Simulation time 2637721229 ps
CPU time 2.34 seconds
Started Aug 09 05:13:10 PM PDT 24
Finished Aug 09 05:13:13 PM PDT 24
Peak memory 200740 kb
Host smart-e26d14df-24e1-4191-b61b-f14216b84f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651429276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.2651429276
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.4237449503
Short name T58
Test name
Test status
Simulation time 2478159118 ps
CPU time 1.71 seconds
Started Aug 09 05:13:07 PM PDT 24
Finished Aug 09 05:13:09 PM PDT 24
Peak memory 200748 kb
Host smart-340ba5bf-fdcb-4f22-9565-cd3f543688d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237449503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.4237449503
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.2143734395
Short name T165
Test name
Test status
Simulation time 2055925853 ps
CPU time 1.79 seconds
Started Aug 09 05:13:09 PM PDT 24
Finished Aug 09 05:13:11 PM PDT 24
Peak memory 200656 kb
Host smart-ca17b923-218a-4d34-be8e-5fd3dca1d313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143734395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.2143734395
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.3413317495
Short name T13
Test name
Test status
Simulation time 2525127057 ps
CPU time 2.29 seconds
Started Aug 09 05:13:07 PM PDT 24
Finished Aug 09 05:13:09 PM PDT 24
Peak memory 200820 kb
Host smart-12f54d17-0807-4f70-b8d8-65a2bb3f0038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413317495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.3413317495
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.2497439820
Short name T431
Test name
Test status
Simulation time 2110158870 ps
CPU time 6.02 seconds
Started Aug 09 05:13:11 PM PDT 24
Finished Aug 09 05:13:17 PM PDT 24
Peak memory 200684 kb
Host smart-353dc1ee-5f77-4b0a-b055-8de69cacbdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497439820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.2497439820
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.961325434
Short name T395
Test name
Test status
Simulation time 12078035311 ps
CPU time 26.06 seconds
Started Aug 09 05:13:08 PM PDT 24
Finished Aug 09 05:13:34 PM PDT 24
Peak memory 200696 kb
Host smart-5ac82271-5b59-414b-a764-dc252b7a8830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961325434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_st
ress_all.961325434
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.380068339
Short name T251
Test name
Test status
Simulation time 5974668958 ps
CPU time 4.14 seconds
Started Aug 09 05:13:09 PM PDT 24
Finished Aug 09 05:13:13 PM PDT 24
Peak memory 200880 kb
Host smart-1dd689c8-3cde-4acc-80c1-49d11594d0f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380068339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_ultra_low_pwr.380068339
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.587366500
Short name T470
Test name
Test status
Simulation time 2012016798 ps
CPU time 5.82 seconds
Started Aug 09 05:13:16 PM PDT 24
Finished Aug 09 05:13:22 PM PDT 24
Peak memory 200424 kb
Host smart-fbf9abc3-ff26-4152-9756-411b4e090a7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587366500 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_tes
t.587366500
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1981655986
Short name T401
Test name
Test status
Simulation time 3723228840 ps
CPU time 5.45 seconds
Started Aug 09 05:13:18 PM PDT 24
Finished Aug 09 05:13:23 PM PDT 24
Peak memory 200792 kb
Host smart-7fe5e9cf-761d-4501-a001-4a65f6a10662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981655986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.1
981655986
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.1992272750
Short name T264
Test name
Test status
Simulation time 91868147421 ps
CPU time 115.77 seconds
Started Aug 09 05:13:15 PM PDT 24
Finished Aug 09 05:15:11 PM PDT 24
Peak memory 201032 kb
Host smart-37f4e788-b68b-4932-9c97-9902aedee40c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992272750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.1992272750
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2048022275
Short name T247
Test name
Test status
Simulation time 50165531539 ps
CPU time 16.52 seconds
Started Aug 09 05:13:19 PM PDT 24
Finished Aug 09 05:13:35 PM PDT 24
Peak memory 201028 kb
Host smart-7cca74e7-2b81-4d44-a643-cbbfa97eee55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048022275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.2048022275
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.1961340436
Short name T432
Test name
Test status
Simulation time 4574019298 ps
CPU time 3.28 seconds
Started Aug 09 05:13:13 PM PDT 24
Finished Aug 09 05:13:17 PM PDT 24
Peak memory 200704 kb
Host smart-b58de417-394f-42db-8b16-a8e90764c5ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961340436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ec_pwr_on_rst.1961340436
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.3660765968
Short name T632
Test name
Test status
Simulation time 49516992256 ps
CPU time 3.05 seconds
Started Aug 09 05:13:16 PM PDT 24
Finished Aug 09 05:13:19 PM PDT 24
Peak memory 200744 kb
Host smart-69f6ec65-e429-4ba2-928c-a9a67327c7ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660765968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.3660765968
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.4115547174
Short name T545
Test name
Test status
Simulation time 2634981373 ps
CPU time 2.21 seconds
Started Aug 09 05:13:18 PM PDT 24
Finished Aug 09 05:13:20 PM PDT 24
Peak memory 200728 kb
Host smart-2d216f16-f884-44a4-abac-16067917c500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115547174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.4115547174
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.1910977340
Short name T701
Test name
Test status
Simulation time 2456964183 ps
CPU time 6.65 seconds
Started Aug 09 05:13:16 PM PDT 24
Finished Aug 09 05:13:22 PM PDT 24
Peak memory 200732 kb
Host smart-e5806422-fe62-484b-aaf6-f351e1c5608e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910977340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.1910977340
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.3183716447
Short name T765
Test name
Test status
Simulation time 2037988132 ps
CPU time 3.07 seconds
Started Aug 09 05:13:16 PM PDT 24
Finished Aug 09 05:13:19 PM PDT 24
Peak memory 200448 kb
Host smart-db612ce2-2e1a-4b88-9c9a-73e708aeb146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183716447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.3183716447
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.2008509477
Short name T575
Test name
Test status
Simulation time 2520531132 ps
CPU time 3.96 seconds
Started Aug 09 05:13:14 PM PDT 24
Finished Aug 09 05:13:19 PM PDT 24
Peak memory 200744 kb
Host smart-2b42d7ef-cfd3-42af-9fb0-97ff8f03a928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008509477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.2008509477
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.972630471
Short name T409
Test name
Test status
Simulation time 2110116182 ps
CPU time 6.07 seconds
Started Aug 09 05:13:18 PM PDT 24
Finished Aug 09 05:13:24 PM PDT 24
Peak memory 200652 kb
Host smart-3974de7f-7261-4255-8595-4557e39529d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972630471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.972630471
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.2078095636
Short name T192
Test name
Test status
Simulation time 12146338703 ps
CPU time 13 seconds
Started Aug 09 05:13:16 PM PDT 24
Finished Aug 09 05:13:29 PM PDT 24
Peak memory 200820 kb
Host smart-aa8274e0-3f96-42ae-8137-36684536cb70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078095636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_s
tress_all.2078095636
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3174810496
Short name T770
Test name
Test status
Simulation time 29032521180 ps
CPU time 79.1 seconds
Started Aug 09 05:13:18 PM PDT 24
Finished Aug 09 05:14:37 PM PDT 24
Peak memory 209232 kb
Host smart-c4ba5ca4-d9f2-4962-8ed8-caa8410b14a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174810496 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.3174810496
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.2149574612
Short name T127
Test name
Test status
Simulation time 7277042813 ps
CPU time 9 seconds
Started Aug 09 05:13:16 PM PDT 24
Finished Aug 09 05:13:25 PM PDT 24
Peak memory 200840 kb
Host smart-5cc1b09c-48b4-47ac-869b-7c7ed45ac219
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149574612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.2149574612
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.3245430625
Short name T746
Test name
Test status
Simulation time 2013599669 ps
CPU time 5.47 seconds
Started Aug 09 05:13:16 PM PDT 24
Finished Aug 09 05:13:22 PM PDT 24
Peak memory 200720 kb
Host smart-696a97eb-3675-4bcc-b1ac-9f2be3eaeab8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245430625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.3245430625
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2903887402
Short name T496
Test name
Test status
Simulation time 3124891727 ps
CPU time 8.68 seconds
Started Aug 09 05:13:16 PM PDT 24
Finished Aug 09 05:13:25 PM PDT 24
Peak memory 200872 kb
Host smart-6ab3620c-a5f5-47b9-8d01-1de96abbbe84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903887402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.2
903887402
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.3686878562
Short name T230
Test name
Test status
Simulation time 99265033855 ps
CPU time 64.62 seconds
Started Aug 09 05:13:19 PM PDT 24
Finished Aug 09 05:14:24 PM PDT 24
Peak memory 200964 kb
Host smart-d348da49-2dda-41cc-9a77-b1f8f8bb8eb1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686878562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.3686878562
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.318388096
Short name T369
Test name
Test status
Simulation time 92785718306 ps
CPU time 30.02 seconds
Started Aug 09 05:13:15 PM PDT 24
Finished Aug 09 05:13:45 PM PDT 24
Peak memory 201028 kb
Host smart-1c2f218f-e651-49cd-aebf-279c283641c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318388096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_wi
th_pre_cond.318388096
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1059348379
Short name T471
Test name
Test status
Simulation time 4650908510 ps
CPU time 12.08 seconds
Started Aug 09 05:13:15 PM PDT 24
Finished Aug 09 05:13:27 PM PDT 24
Peak memory 200828 kb
Host smart-59f65062-8bb1-4813-902c-dff4e376e92d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059348379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.1059348379
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3149817088
Short name T506
Test name
Test status
Simulation time 2620037960 ps
CPU time 4.07 seconds
Started Aug 09 05:13:19 PM PDT 24
Finished Aug 09 05:13:23 PM PDT 24
Peak memory 200804 kb
Host smart-85b08e7a-dd83-4de6-82e3-90b89b7e1511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149817088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.3149817088
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.3242017711
Short name T495
Test name
Test status
Simulation time 2475563079 ps
CPU time 4.19 seconds
Started Aug 09 05:13:15 PM PDT 24
Finished Aug 09 05:13:19 PM PDT 24
Peak memory 200764 kb
Host smart-e83e3aa3-9d02-4cb6-9ac1-601cfe644e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242017711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.3242017711
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.1734179964
Short name T749
Test name
Test status
Simulation time 2179626428 ps
CPU time 2.02 seconds
Started Aug 09 05:13:17 PM PDT 24
Finished Aug 09 05:13:20 PM PDT 24
Peak memory 200740 kb
Host smart-b0929ec4-35af-4c86-b483-eac96a5cee5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734179964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.1734179964
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.4067567952
Short name T253
Test name
Test status
Simulation time 2599754222 ps
CPU time 1.24 seconds
Started Aug 09 05:13:14 PM PDT 24
Finished Aug 09 05:13:15 PM PDT 24
Peak memory 200736 kb
Host smart-742f9a8e-fc56-4398-8fbb-69bea9aa81cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067567952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.4067567952
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.3639593341
Short name T710
Test name
Test status
Simulation time 2139307482 ps
CPU time 1.41 seconds
Started Aug 09 05:13:15 PM PDT 24
Finished Aug 09 05:13:16 PM PDT 24
Peak memory 200652 kb
Host smart-c2ae0662-b34b-4d1f-a0fd-5ae250828979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639593341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.3639593341
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.3936719102
Short name T229
Test name
Test status
Simulation time 7843802648 ps
CPU time 6.17 seconds
Started Aug 09 05:13:14 PM PDT 24
Finished Aug 09 05:13:20 PM PDT 24
Peak memory 200836 kb
Host smart-558e2e98-5931-4e9f-9c9e-9b656c88671e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936719102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_s
tress_all.3936719102
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.938000623
Short name T298
Test name
Test status
Simulation time 23044201907 ps
CPU time 56.42 seconds
Started Aug 09 05:13:19 PM PDT 24
Finished Aug 09 05:14:15 PM PDT 24
Peak memory 201240 kb
Host smart-9a6121df-30d7-40d5-a5c3-440e442d4b7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938000623 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.938000623
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1121908027
Short name T772
Test name
Test status
Simulation time 3128333633 ps
CPU time 0.98 seconds
Started Aug 09 05:13:15 PM PDT 24
Finished Aug 09 05:13:16 PM PDT 24
Peak memory 200748 kb
Host smart-8bf36e57-b1eb-4a9b-ad38-0632ce151727
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121908027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.1121908027
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.3720373742
Short name T236
Test name
Test status
Simulation time 2010643694 ps
CPU time 5.06 seconds
Started Aug 09 05:13:25 PM PDT 24
Finished Aug 09 05:13:30 PM PDT 24
Peak memory 201068 kb
Host smart-e3866d81-c5f1-4312-8885-e94555f5301e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720373742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.3720373742
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.1836306239
Short name T756
Test name
Test status
Simulation time 200648101732 ps
CPU time 122.65 seconds
Started Aug 09 05:13:26 PM PDT 24
Finished Aug 09 05:15:28 PM PDT 24
Peak memory 200844 kb
Host smart-9d055537-5b3d-4566-9135-3744d353826d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836306239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.1
836306239
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.837581978
Short name T342
Test name
Test status
Simulation time 120110512293 ps
CPU time 319.59 seconds
Started Aug 09 05:13:27 PM PDT 24
Finished Aug 09 05:18:46 PM PDT 24
Peak memory 200924 kb
Host smart-3c3fb457-e7ef-4a20-9b57-35b9aec6b121
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837581978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_combo_detect.837581978
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2854651618
Short name T751
Test name
Test status
Simulation time 59599054635 ps
CPU time 41.32 seconds
Started Aug 09 05:13:25 PM PDT 24
Finished Aug 09 05:14:07 PM PDT 24
Peak memory 201000 kb
Host smart-575e94a6-63b9-4661-92a7-711555e08678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854651618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w
ith_pre_cond.2854651618
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.2178056279
Short name T302
Test name
Test status
Simulation time 4386973567 ps
CPU time 10.81 seconds
Started Aug 09 05:13:22 PM PDT 24
Finished Aug 09 05:13:33 PM PDT 24
Peak memory 200756 kb
Host smart-6bff0f8f-1682-4eb8-bdf1-59dfcf3226e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178056279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.2178056279
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.2109696696
Short name T144
Test name
Test status
Simulation time 5223390357 ps
CPU time 1.61 seconds
Started Aug 09 05:13:23 PM PDT 24
Finished Aug 09 05:13:25 PM PDT 24
Peak memory 200796 kb
Host smart-a6ee889a-2c23-4857-b596-4cc9bca82126
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109696696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_edge_detect.2109696696
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.2207738052
Short name T618
Test name
Test status
Simulation time 2613147078 ps
CPU time 7.74 seconds
Started Aug 09 05:13:24 PM PDT 24
Finished Aug 09 05:13:32 PM PDT 24
Peak memory 200720 kb
Host smart-54af05e1-cf9f-4b80-9dc1-2994ea12b63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207738052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.2207738052
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.1969426997
Short name T653
Test name
Test status
Simulation time 2454803526 ps
CPU time 3.26 seconds
Started Aug 09 05:13:23 PM PDT 24
Finished Aug 09 05:13:27 PM PDT 24
Peak memory 200748 kb
Host smart-7cba72b5-89a0-46f3-b332-ab938e49410c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969426997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.1969426997
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.2053657680
Short name T462
Test name
Test status
Simulation time 2173236971 ps
CPU time 5.65 seconds
Started Aug 09 05:13:25 PM PDT 24
Finished Aug 09 05:13:31 PM PDT 24
Peak memory 200784 kb
Host smart-1616647e-efa8-4390-b290-2ab55525c84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053657680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.2053657680
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.749458318
Short name T474
Test name
Test status
Simulation time 2512389773 ps
CPU time 6.97 seconds
Started Aug 09 05:13:24 PM PDT 24
Finished Aug 09 05:13:31 PM PDT 24
Peak memory 200836 kb
Host smart-bbc564df-e245-4bf5-a00b-36132304cb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749458318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.749458318
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.4121378450
Short name T705
Test name
Test status
Simulation time 2132160215 ps
CPU time 1.96 seconds
Started Aug 09 05:13:22 PM PDT 24
Finished Aug 09 05:13:25 PM PDT 24
Peak memory 200616 kb
Host smart-d72b036f-6842-4fbd-abfc-d2aa57bf85aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121378450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.4121378450
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.453230702
Short name T442
Test name
Test status
Simulation time 13350942935 ps
CPU time 13.18 seconds
Started Aug 09 05:13:23 PM PDT 24
Finished Aug 09 05:13:36 PM PDT 24
Peak memory 200804 kb
Host smart-dfbbedd5-d182-4c6a-a228-d1647bb9aba9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453230702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_st
ress_all.453230702
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.1115847069
Short name T648
Test name
Test status
Simulation time 5733918081 ps
CPU time 3.49 seconds
Started Aug 09 05:13:25 PM PDT 24
Finished Aug 09 05:13:29 PM PDT 24
Peak memory 200876 kb
Host smart-765ef49f-0e43-47d9-a519-d685e295cd47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115847069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.1115847069
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.519783145
Short name T439
Test name
Test status
Simulation time 2010168660 ps
CPU time 5.45 seconds
Started Aug 09 05:13:25 PM PDT 24
Finished Aug 09 05:13:30 PM PDT 24
Peak memory 200664 kb
Host smart-00f354ed-ea3a-47ae-bc5e-012e8e299fa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519783145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_tes
t.519783145
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2069767986
Short name T84
Test name
Test status
Simulation time 3824812107 ps
CPU time 5.05 seconds
Started Aug 09 05:13:23 PM PDT 24
Finished Aug 09 05:13:28 PM PDT 24
Peak memory 200796 kb
Host smart-60261f65-fd01-4e8f-aae9-664ca904c4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069767986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2
069767986
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.353293509
Short name T629
Test name
Test status
Simulation time 4745552196 ps
CPU time 3.78 seconds
Started Aug 09 05:13:25 PM PDT 24
Finished Aug 09 05:13:29 PM PDT 24
Peak memory 200836 kb
Host smart-48a27834-c805-4e10-b272-2586e21f4fa5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353293509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_ec_pwr_on_rst.353293509
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.3129119005
Short name T198
Test name
Test status
Simulation time 5480879825 ps
CPU time 9.33 seconds
Started Aug 09 05:13:26 PM PDT 24
Finished Aug 09 05:13:36 PM PDT 24
Peak memory 200780 kb
Host smart-58773fbf-833f-4e01-b28a-fe75d5ee6516
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129119005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.3129119005
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.1229713927
Short name T47
Test name
Test status
Simulation time 2616228041 ps
CPU time 3.97 seconds
Started Aug 09 05:13:25 PM PDT 24
Finished Aug 09 05:13:29 PM PDT 24
Peak memory 200736 kb
Host smart-0c8f3be3-7975-4a86-a88e-710352aee78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229713927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.1229713927
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.817718492
Short name T561
Test name
Test status
Simulation time 2476598408 ps
CPU time 7.79 seconds
Started Aug 09 05:13:25 PM PDT 24
Finished Aug 09 05:13:33 PM PDT 24
Peak memory 200640 kb
Host smart-a7f3b0e5-fdbb-481b-8607-d143ce965672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817718492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.817718492
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.2017512455
Short name T15
Test name
Test status
Simulation time 2033874855 ps
CPU time 1.68 seconds
Started Aug 09 05:13:24 PM PDT 24
Finished Aug 09 05:13:25 PM PDT 24
Peak memory 200740 kb
Host smart-4600df95-5f6d-49b8-8e2f-3cdc1c979bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017512455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.2017512455
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.2361387092
Short name T567
Test name
Test status
Simulation time 2509689244 ps
CPU time 7.23 seconds
Started Aug 09 05:13:24 PM PDT 24
Finished Aug 09 05:13:31 PM PDT 24
Peak memory 200752 kb
Host smart-161979c2-d0cb-44ad-85e4-3bcc7a4c405d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361387092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.2361387092
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.3358853883
Short name T49
Test name
Test status
Simulation time 2111533819 ps
CPU time 6.58 seconds
Started Aug 09 05:13:22 PM PDT 24
Finished Aug 09 05:13:29 PM PDT 24
Peak memory 200732 kb
Host smart-1b98113b-407c-4cb8-8d51-e37a52229b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358853883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.3358853883
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2752205281
Short name T788
Test name
Test status
Simulation time 29482628679 ps
CPU time 73.35 seconds
Started Aug 09 05:13:27 PM PDT 24
Finished Aug 09 05:14:40 PM PDT 24
Peak memory 212664 kb
Host smart-2fe64b53-2ca8-4bbe-b169-23f1b718e9cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752205281 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.2752205281
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.4849962
Short name T126
Test name
Test status
Simulation time 12330681245 ps
CPU time 4.45 seconds
Started Aug 09 05:13:24 PM PDT 24
Finished Aug 09 05:13:28 PM PDT 24
Peak memory 200756 kb
Host smart-a59fc9da-9b9b-4ffc-9c0f-c30bf89dc981
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4849962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctr
l_ultra_low_pwr.4849962
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.3364458030
Short name T458
Test name
Test status
Simulation time 2019461980 ps
CPU time 3.07 seconds
Started Aug 09 05:13:37 PM PDT 24
Finished Aug 09 05:13:40 PM PDT 24
Peak memory 200728 kb
Host smart-818c7d89-174d-4826-922c-4c54710bb63c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364458030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_te
st.3364458030
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.216475297
Short name T691
Test name
Test status
Simulation time 3253111527 ps
CPU time 8.28 seconds
Started Aug 09 05:13:36 PM PDT 24
Finished Aug 09 05:13:45 PM PDT 24
Peak memory 200880 kb
Host smart-274e7af2-bf4c-41a8-838c-8a065ded5d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216475297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.216475297
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.1483160442
Short name T769
Test name
Test status
Simulation time 45164099138 ps
CPU time 119.53 seconds
Started Aug 09 05:13:38 PM PDT 24
Finished Aug 09 05:15:38 PM PDT 24
Peak memory 200968 kb
Host smart-7c2fc1e8-79de-4382-b982-5bd7641b76af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483160442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.1483160442
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1084590991
Short name T275
Test name
Test status
Simulation time 86276821920 ps
CPU time 216.19 seconds
Started Aug 09 05:13:38 PM PDT 24
Finished Aug 09 05:17:15 PM PDT 24
Peak memory 201100 kb
Host smart-dec0ec27-a193-4c8a-9cbb-e507c4e6beb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084590991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w
ith_pre_cond.1084590991
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.2526235666
Short name T189
Test name
Test status
Simulation time 3816922939 ps
CPU time 3.83 seconds
Started Aug 09 05:13:35 PM PDT 24
Finished Aug 09 05:13:39 PM PDT 24
Peak memory 200756 kb
Host smart-ab6ba3eb-e579-4e28-a591-0c7350e3c9af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526235666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.2526235666
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3073495321
Short name T562
Test name
Test status
Simulation time 2629107236 ps
CPU time 2.69 seconds
Started Aug 09 05:13:38 PM PDT 24
Finished Aug 09 05:13:41 PM PDT 24
Peak memory 200656 kb
Host smart-5b51ee1e-4550-4dda-baba-ca3e006d875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073495321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.3073495321
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.4275258947
Short name T60
Test name
Test status
Simulation time 2462032692 ps
CPU time 2.25 seconds
Started Aug 09 05:13:35 PM PDT 24
Finished Aug 09 05:13:37 PM PDT 24
Peak memory 200752 kb
Host smart-c6673df0-e78e-4e74-b59c-e3849d9feed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275258947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.4275258947
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.1807764121
Short name T443
Test name
Test status
Simulation time 2098168712 ps
CPU time 3.36 seconds
Started Aug 09 05:13:37 PM PDT 24
Finished Aug 09 05:13:41 PM PDT 24
Peak memory 200664 kb
Host smart-1634996f-dad3-49aa-8135-ce4f983e70ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807764121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.1807764121
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.677177162
Short name T500
Test name
Test status
Simulation time 2533353171 ps
CPU time 2.61 seconds
Started Aug 09 05:13:36 PM PDT 24
Finished Aug 09 05:13:39 PM PDT 24
Peak memory 200784 kb
Host smart-3784cc8c-9e46-41db-a3e2-9b9b38a9f18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677177162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.677177162
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.1550840001
Short name T602
Test name
Test status
Simulation time 2141828592 ps
CPU time 1.66 seconds
Started Aug 09 05:13:25 PM PDT 24
Finished Aug 09 05:13:26 PM PDT 24
Peak memory 200664 kb
Host smart-469c410d-7c7e-4169-b45a-5fd8e52662d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550840001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.1550840001
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.84282723
Short name T41
Test name
Test status
Simulation time 13907728573 ps
CPU time 7.52 seconds
Started Aug 09 05:13:35 PM PDT 24
Finished Aug 09 05:13:43 PM PDT 24
Peak memory 200832 kb
Host smart-1df66c5f-8e14-466c-8341-cfb758da83fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84282723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_str
ess_all.84282723
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.2738369699
Short name T387
Test name
Test status
Simulation time 993922780066 ps
CPU time 78.63 seconds
Started Aug 09 05:13:37 PM PDT 24
Finished Aug 09 05:14:56 PM PDT 24
Peak memory 200820 kb
Host smart-0ca157b2-08aa-4a92-8ecd-e82b8f7a4ffa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738369699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.2738369699
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.2703549469
Short name T674
Test name
Test status
Simulation time 2034234150 ps
CPU time 1.87 seconds
Started Aug 09 05:13:39 PM PDT 24
Finished Aug 09 05:13:41 PM PDT 24
Peak memory 200820 kb
Host smart-28dd0c3c-f5d3-472b-a159-95b8b209ad77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703549469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.2703549469
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1578282146
Short name T206
Test name
Test status
Simulation time 3795647661 ps
CPU time 9.67 seconds
Started Aug 09 05:13:36 PM PDT 24
Finished Aug 09 05:13:46 PM PDT 24
Peak memory 200844 kb
Host smart-e73327a0-a412-4485-a2b3-1c15f19bd5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578282146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.1
578282146
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.4204543692
Short name T102
Test name
Test status
Simulation time 88154963424 ps
CPU time 228.4 seconds
Started Aug 09 05:13:36 PM PDT 24
Finished Aug 09 05:17:25 PM PDT 24
Peak memory 200944 kb
Host smart-b108936b-b572-4613-86e4-f0565813c773
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204543692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_combo_detect.4204543692
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3917089005
Short name T370
Test name
Test status
Simulation time 46446439317 ps
CPU time 19.26 seconds
Started Aug 09 05:13:37 PM PDT 24
Finished Aug 09 05:13:56 PM PDT 24
Peak memory 201080 kb
Host smart-cb2c57a1-c39f-426a-862d-8c62b4362c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917089005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.3917089005
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.780398214
Short name T182
Test name
Test status
Simulation time 2657892303 ps
CPU time 1.6 seconds
Started Aug 09 05:13:36 PM PDT 24
Finished Aug 09 05:13:37 PM PDT 24
Peak memory 200712 kb
Host smart-569f2a7a-fb72-4ac6-a84f-2ebcf8fa7537
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780398214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_ec_pwr_on_rst.780398214
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.3943866237
Short name T38
Test name
Test status
Simulation time 3219511112 ps
CPU time 3.6 seconds
Started Aug 09 05:13:35 PM PDT 24
Finished Aug 09 05:13:39 PM PDT 24
Peak memory 200796 kb
Host smart-555284c8-b23e-4d9e-a18a-df569ead1761
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943866237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_edge_detect.3943866237
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.392473575
Short name T595
Test name
Test status
Simulation time 2628427522 ps
CPU time 2.33 seconds
Started Aug 09 05:13:36 PM PDT 24
Finished Aug 09 05:13:39 PM PDT 24
Peak memory 200816 kb
Host smart-f379e3ef-a4f1-44d0-9c17-fda5cc282fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392473575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.392473575
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.3489063337
Short name T59
Test name
Test status
Simulation time 2514245382 ps
CPU time 1.6 seconds
Started Aug 09 05:13:36 PM PDT 24
Finished Aug 09 05:13:38 PM PDT 24
Peak memory 200808 kb
Host smart-4b822f38-c9ef-4564-8e3d-3ee260c5f55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489063337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.3489063337
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.1226700508
Short name T185
Test name
Test status
Simulation time 2032170904 ps
CPU time 5.45 seconds
Started Aug 09 05:13:35 PM PDT 24
Finished Aug 09 05:13:40 PM PDT 24
Peak memory 200752 kb
Host smart-9212b284-cf26-4fa4-acfe-67c3dd9be45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226700508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.1226700508
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.4158975128
Short name T308
Test name
Test status
Simulation time 2528122919 ps
CPU time 2.1 seconds
Started Aug 09 05:13:35 PM PDT 24
Finished Aug 09 05:13:38 PM PDT 24
Peak memory 200800 kb
Host smart-4e7e2108-0ae0-41a6-9c6a-9069258a72fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158975128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.4158975128
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.3867919741
Short name T609
Test name
Test status
Simulation time 2112919199 ps
CPU time 5.63 seconds
Started Aug 09 05:13:36 PM PDT 24
Finished Aug 09 05:13:41 PM PDT 24
Peak memory 200672 kb
Host smart-23dac40c-9736-4dfd-a07f-da771f6fa274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867919741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.3867919741
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.2600708011
Short name T214
Test name
Test status
Simulation time 420852752897 ps
CPU time 34.64 seconds
Started Aug 09 05:13:34 PM PDT 24
Finished Aug 09 05:14:09 PM PDT 24
Peak memory 200856 kb
Host smart-fa42bff4-3b76-4a02-b205-3a696df57e48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600708011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_s
tress_all.2600708011
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.4244059643
Short name T541
Test name
Test status
Simulation time 3115392560 ps
CPU time 8.3 seconds
Started Aug 09 05:13:38 PM PDT 24
Finished Aug 09 05:13:46 PM PDT 24
Peak memory 200720 kb
Host smart-d3037925-ee62-40b2-bc38-40a56d0ca7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244059643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.4
244059643
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1764298373
Short name T23
Test name
Test status
Simulation time 42074221047 ps
CPU time 8.97 seconds
Started Aug 09 05:13:43 PM PDT 24
Finished Aug 09 05:13:53 PM PDT 24
Peak memory 201104 kb
Host smart-0011c8d2-31d3-40c6-8e74-7a55d42de25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764298373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_w
ith_pre_cond.1764298373
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.71424189
Short name T596
Test name
Test status
Simulation time 3992342305 ps
CPU time 3.26 seconds
Started Aug 09 05:13:37 PM PDT 24
Finished Aug 09 05:13:40 PM PDT 24
Peak memory 200760 kb
Host smart-627cea54-8415-4c98-aac4-f0572497d14b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71424189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_ec_pwr_on_rst.71424189
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.2054539179
Short name T35
Test name
Test status
Simulation time 4145468977 ps
CPU time 11.41 seconds
Started Aug 09 05:13:37 PM PDT 24
Finished Aug 09 05:13:48 PM PDT 24
Peak memory 200800 kb
Host smart-762772c6-b3c2-4625-a3f1-5b8781642e0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054539179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.2054539179
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.2807163135
Short name T649
Test name
Test status
Simulation time 2625833898 ps
CPU time 2.42 seconds
Started Aug 09 05:13:38 PM PDT 24
Finished Aug 09 05:13:41 PM PDT 24
Peak memory 200720 kb
Host smart-d8cdb659-99d3-42d0-9d27-26bdbc13bf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807163135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.2807163135
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.1309648603
Short name T491
Test name
Test status
Simulation time 2461998982 ps
CPU time 3.11 seconds
Started Aug 09 05:13:38 PM PDT 24
Finished Aug 09 05:13:42 PM PDT 24
Peak memory 200672 kb
Host smart-d2f048f8-df9f-447f-b4e2-70c0b506da72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309648603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.1309648603
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.119359337
Short name T671
Test name
Test status
Simulation time 2168258598 ps
CPU time 1.23 seconds
Started Aug 09 05:13:37 PM PDT 24
Finished Aug 09 05:13:38 PM PDT 24
Peak memory 200724 kb
Host smart-8516361e-eb06-4d37-8741-3a15ba638c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119359337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.119359337
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.3952078212
Short name T155
Test name
Test status
Simulation time 2510536018 ps
CPU time 5.08 seconds
Started Aug 09 05:13:37 PM PDT 24
Finished Aug 09 05:13:42 PM PDT 24
Peak memory 200708 kb
Host smart-9d543baf-c6aa-4f20-83d0-aba54bbd5cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952078212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.3952078212
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.3838283903
Short name T728
Test name
Test status
Simulation time 2133439322 ps
CPU time 1.97 seconds
Started Aug 09 05:13:37 PM PDT 24
Finished Aug 09 05:13:39 PM PDT 24
Peak memory 200668 kb
Host smart-79dabea6-b4c0-44c1-892d-13a2b260917a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838283903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.3838283903
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.3531047574
Short name T630
Test name
Test status
Simulation time 6625429855 ps
CPU time 17.55 seconds
Started Aug 09 05:13:39 PM PDT 24
Finished Aug 09 05:13:57 PM PDT 24
Peak memory 200668 kb
Host smart-fb6142f5-be36-436f-8d79-0855d2cad895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531047574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.3531047574
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.4026382863
Short name T139
Test name
Test status
Simulation time 3542303709 ps
CPU time 1.47 seconds
Started Aug 09 05:13:38 PM PDT 24
Finished Aug 09 05:13:40 PM PDT 24
Peak memory 200832 kb
Host smart-c6245064-cab7-4b1d-8903-5ac421e5fa2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026382863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ultra_low_pwr.4026382863
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.4147362603
Short name T600
Test name
Test status
Simulation time 2038782275 ps
CPU time 1.97 seconds
Started Aug 09 05:13:43 PM PDT 24
Finished Aug 09 05:13:45 PM PDT 24
Peak memory 200744 kb
Host smart-cc24d1f0-1964-44b4-809e-d508c4c292ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147362603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.4147362603
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3477233260
Short name T523
Test name
Test status
Simulation time 3343231780 ps
CPU time 1.83 seconds
Started Aug 09 05:13:37 PM PDT 24
Finished Aug 09 05:13:39 PM PDT 24
Peak memory 200880 kb
Host smart-423f7515-3411-40af-83d3-ffc8c2a0dfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477233260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.3
477233260
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.419455411
Short name T103
Test name
Test status
Simulation time 22069531571 ps
CPU time 29.57 seconds
Started Aug 09 05:13:43 PM PDT 24
Finished Aug 09 05:14:13 PM PDT 24
Peak memory 201040 kb
Host smart-2b190dd9-6fac-421d-a2c5-5cec62c18030
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419455411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_combo_detect.419455411
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.790635237
Short name T597
Test name
Test status
Simulation time 3059549885 ps
CPU time 8.57 seconds
Started Aug 09 05:13:42 PM PDT 24
Finished Aug 09 05:13:51 PM PDT 24
Peak memory 200752 kb
Host smart-e5e06e93-5632-4519-a898-0db274cb7751
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790635237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_ec_pwr_on_rst.790635237
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2390188392
Short name T583
Test name
Test status
Simulation time 2612559592 ps
CPU time 6.83 seconds
Started Aug 09 05:13:41 PM PDT 24
Finished Aug 09 05:13:48 PM PDT 24
Peak memory 200764 kb
Host smart-d3404f07-ad66-47a4-a015-1cffd5c89764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390188392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.2390188392
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.456533349
Short name T778
Test name
Test status
Simulation time 2456756944 ps
CPU time 7.16 seconds
Started Aug 09 05:13:41 PM PDT 24
Finished Aug 09 05:13:48 PM PDT 24
Peak memory 201056 kb
Host smart-29f1c9b0-7b5c-45e0-b5b9-d339fa16a901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456533349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.456533349
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.3421897164
Short name T743
Test name
Test status
Simulation time 2123489558 ps
CPU time 6.34 seconds
Started Aug 09 05:13:40 PM PDT 24
Finished Aug 09 05:13:46 PM PDT 24
Peak memory 200724 kb
Host smart-cb959382-6629-40b9-aba4-4e2c1bfa9df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421897164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.3421897164
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.1866184777
Short name T166
Test name
Test status
Simulation time 2508396303 ps
CPU time 7.33 seconds
Started Aug 09 05:13:39 PM PDT 24
Finished Aug 09 05:13:47 PM PDT 24
Peak memory 201084 kb
Host smart-e4e599cc-b523-47e5-a441-93a410f15522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866184777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.1866184777
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.1906965409
Short name T404
Test name
Test status
Simulation time 2110053174 ps
CPU time 6.21 seconds
Started Aug 09 05:13:38 PM PDT 24
Finished Aug 09 05:13:44 PM PDT 24
Peak memory 200672 kb
Host smart-61c9e86c-2af7-4a16-8cdb-a0b6964ea034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906965409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.1906965409
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.2399415043
Short name T787
Test name
Test status
Simulation time 7151110709 ps
CPU time 7.46 seconds
Started Aug 09 05:13:40 PM PDT 24
Finished Aug 09 05:13:48 PM PDT 24
Peak memory 200764 kb
Host smart-5fc013db-9d54-425b-a34e-c6ae76ebd537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399415043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.2399415043
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.378828541
Short name T297
Test name
Test status
Simulation time 61161237678 ps
CPU time 153.73 seconds
Started Aug 09 05:13:40 PM PDT 24
Finished Aug 09 05:16:14 PM PDT 24
Peak memory 209460 kb
Host smart-c576c2ec-ced7-4fa8-b725-1886f249ddb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378828541 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.378828541
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2851275708
Short name T72
Test name
Test status
Simulation time 1481699635505 ps
CPU time 40.65 seconds
Started Aug 09 05:13:39 PM PDT 24
Finished Aug 09 05:14:19 PM PDT 24
Peak memory 200784 kb
Host smart-43490150-b956-412f-9f30-9ff20d479484
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851275708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ultra_low_pwr.2851275708
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.1285796459
Short name T397
Test name
Test status
Simulation time 2014627419 ps
CPU time 5.93 seconds
Started Aug 09 05:12:43 PM PDT 24
Finished Aug 09 05:12:49 PM PDT 24
Peak memory 200744 kb
Host smart-12af3b8b-635f-4841-9fa6-42f55fced16f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285796459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.1285796459
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3462589092
Short name T260
Test name
Test status
Simulation time 192012538337 ps
CPU time 36.47 seconds
Started Aug 09 05:12:42 PM PDT 24
Finished Aug 09 05:13:19 PM PDT 24
Peak memory 200848 kb
Host smart-133b9d81-35d4-4b4d-88e9-c7de99523657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462589092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.3462589092
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.3804738870
Short name T272
Test name
Test status
Simulation time 36240590112 ps
CPU time 86.03 seconds
Started Aug 09 05:12:43 PM PDT 24
Finished Aug 09 05:14:09 PM PDT 24
Peak memory 201060 kb
Host smart-61dd7d9f-b228-45a2-9c0d-7aff25acec7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804738870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.3804738870
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.4067226650
Short name T503
Test name
Test status
Simulation time 2189998190 ps
CPU time 1.96 seconds
Started Aug 09 05:12:43 PM PDT 24
Finished Aug 09 05:12:45 PM PDT 24
Peak memory 200756 kb
Host smart-2beaeb40-b7a3-4d4c-aa78-4b439ba3d0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067226650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.4067226650
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2059742990
Short name T411
Test name
Test status
Simulation time 2519923969 ps
CPU time 2.29 seconds
Started Aug 09 05:12:42 PM PDT 24
Finished Aug 09 05:12:45 PM PDT 24
Peak memory 200724 kb
Host smart-62da1b7c-41ed-46a4-8cd2-a66d4d478663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059742990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2059742990
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.2095975170
Short name T400
Test name
Test status
Simulation time 4034388529 ps
CPU time 2.98 seconds
Started Aug 09 05:12:42 PM PDT 24
Finished Aug 09 05:12:45 PM PDT 24
Peak memory 200756 kb
Host smart-ae861ed2-d01d-42e0-af0c-f6ff8271bd18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095975170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.2095975170
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.3691079891
Short name T234
Test name
Test status
Simulation time 2488851219 ps
CPU time 1.65 seconds
Started Aug 09 05:12:48 PM PDT 24
Finished Aug 09 05:12:50 PM PDT 24
Peak memory 200756 kb
Host smart-8a2e57a4-6b7e-4a85-b5a8-dc31eaf937ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691079891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.3691079891
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3481327096
Short name T731
Test name
Test status
Simulation time 2634830254 ps
CPU time 2.31 seconds
Started Aug 09 05:12:43 PM PDT 24
Finished Aug 09 05:12:46 PM PDT 24
Peak memory 200640 kb
Host smart-66dae146-beaa-44a0-9a6f-dcacfc55f03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481327096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.3481327096
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.2856433473
Short name T447
Test name
Test status
Simulation time 2488980955 ps
CPU time 2.46 seconds
Started Aug 09 05:12:41 PM PDT 24
Finished Aug 09 05:12:43 PM PDT 24
Peak memory 200800 kb
Host smart-8967fda1-b60b-40df-99e3-b8f1b96fb275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856433473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.2856433473
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.3594288257
Short name T635
Test name
Test status
Simulation time 2213768208 ps
CPU time 2 seconds
Started Aug 09 05:12:41 PM PDT 24
Finished Aug 09 05:12:44 PM PDT 24
Peak memory 200792 kb
Host smart-bda54dcd-0095-40f1-ba94-04c2b28bd49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594288257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.3594288257
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.2264335687
Short name T226
Test name
Test status
Simulation time 2523046977 ps
CPU time 2.39 seconds
Started Aug 09 05:12:46 PM PDT 24
Finished Aug 09 05:12:49 PM PDT 24
Peak memory 200832 kb
Host smart-942961c1-b329-4a76-8922-2aa3fe7298ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264335687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.2264335687
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.1902524709
Short name T292
Test name
Test status
Simulation time 22051409858 ps
CPU time 15.05 seconds
Started Aug 09 05:12:41 PM PDT 24
Finished Aug 09 05:12:56 PM PDT 24
Peak memory 220596 kb
Host smart-e4bb0d86-fa87-4426-bcb6-85eab9180116
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902524709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.1902524709
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.1575529235
Short name T723
Test name
Test status
Simulation time 2131867464 ps
CPU time 1.81 seconds
Started Aug 09 05:12:43 PM PDT 24
Finished Aug 09 05:12:45 PM PDT 24
Peak memory 200620 kb
Host smart-7103de08-9b3c-4804-a3a8-8320fae0fef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575529235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.1575529235
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.3012798347
Short name T614
Test name
Test status
Simulation time 11537737052 ps
CPU time 7.15 seconds
Started Aug 09 05:12:42 PM PDT 24
Finished Aug 09 05:12:50 PM PDT 24
Peak memory 200688 kb
Host smart-77af6e07-6a22-4684-88ee-412ca9f20695
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012798347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_st
ress_all.3012798347
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.545986838
Short name T113
Test name
Test status
Simulation time 12886598507 ps
CPU time 1.75 seconds
Started Aug 09 05:12:42 PM PDT 24
Finished Aug 09 05:12:44 PM PDT 24
Peak memory 201144 kb
Host smart-a2e47030-2041-436b-8915-7453dd5bbdeb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545986838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_ultra_low_pwr.545986838
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.1218214483
Short name T248
Test name
Test status
Simulation time 2027215957 ps
CPU time 1.89 seconds
Started Aug 09 05:13:40 PM PDT 24
Finished Aug 09 05:13:42 PM PDT 24
Peak memory 200680 kb
Host smart-27e003a6-737e-474c-9e54-517427a75ac6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218214483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.1218214483
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.2237009028
Short name T565
Test name
Test status
Simulation time 3151247874 ps
CPU time 4.27 seconds
Started Aug 09 05:13:41 PM PDT 24
Finished Aug 09 05:13:45 PM PDT 24
Peak memory 200808 kb
Host smart-b7d540ff-d211-485d-8ad9-c09eced4aff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237009028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.2
237009028
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.1374223410
Short name T208
Test name
Test status
Simulation time 56523790488 ps
CPU time 136.24 seconds
Started Aug 09 05:13:44 PM PDT 24
Finished Aug 09 05:16:00 PM PDT 24
Peak memory 201056 kb
Host smart-91655941-b9b8-4d21-b680-25c377797856
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374223410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_combo_detect.1374223410
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1622708254
Short name T511
Test name
Test status
Simulation time 3315687551 ps
CPU time 2.72 seconds
Started Aug 09 05:13:39 PM PDT 24
Finished Aug 09 05:13:41 PM PDT 24
Peak memory 200728 kb
Host smart-192c6f2d-0a96-4b6b-be99-9e06bdc1a479
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622708254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.1622708254
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.2192399997
Short name T232
Test name
Test status
Simulation time 2836741805 ps
CPU time 3.93 seconds
Started Aug 09 05:13:40 PM PDT 24
Finished Aug 09 05:13:44 PM PDT 24
Peak memory 200804 kb
Host smart-e23499eb-43fd-4330-bfdd-086b7eb72c8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192399997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.2192399997
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.671135817
Short name T186
Test name
Test status
Simulation time 2610664907 ps
CPU time 6.81 seconds
Started Aug 09 05:13:43 PM PDT 24
Finished Aug 09 05:13:50 PM PDT 24
Peak memory 200740 kb
Host smart-04347eb6-5c1f-452c-bbd1-f10e2957b8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671135817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.671135817
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.1387785305
Short name T441
Test name
Test status
Simulation time 2455169370 ps
CPU time 7.21 seconds
Started Aug 09 05:13:36 PM PDT 24
Finished Aug 09 05:13:44 PM PDT 24
Peak memory 200744 kb
Host smart-4694c132-748c-41a3-971c-27d88768cf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387785305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.1387785305
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.388856801
Short name T733
Test name
Test status
Simulation time 2064266341 ps
CPU time 1.96 seconds
Started Aug 09 05:13:38 PM PDT 24
Finished Aug 09 05:13:40 PM PDT 24
Peak memory 200648 kb
Host smart-6158dfe9-0648-423b-b57c-1193e5143f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388856801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.388856801
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.4056266613
Short name T610
Test name
Test status
Simulation time 2514663208 ps
CPU time 3.75 seconds
Started Aug 09 05:13:40 PM PDT 24
Finished Aug 09 05:13:44 PM PDT 24
Peak memory 200736 kb
Host smart-7f783f99-ce49-4346-a8e1-dbb1b6dfaf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056266613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.4056266613
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.1875340433
Short name T712
Test name
Test status
Simulation time 2120004251 ps
CPU time 3.38 seconds
Started Aug 09 05:13:38 PM PDT 24
Finished Aug 09 05:13:42 PM PDT 24
Peak memory 200644 kb
Host smart-16f28d6d-ea74-425c-8b29-8f6cae3a9899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875340433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.1875340433
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.233884975
Short name T521
Test name
Test status
Simulation time 6389318021 ps
CPU time 8.38 seconds
Started Aug 09 05:13:44 PM PDT 24
Finished Aug 09 05:13:52 PM PDT 24
Peak memory 200648 kb
Host smart-e634b552-abb8-4b04-8d42-a088e0d448e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233884975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_st
ress_all.233884975
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2843022077
Short name T121
Test name
Test status
Simulation time 4095189505 ps
CPU time 3.93 seconds
Started Aug 09 05:13:42 PM PDT 24
Finished Aug 09 05:13:46 PM PDT 24
Peak memory 200844 kb
Host smart-bcf04cb6-7679-4cbc-9033-94f3f6055980
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843022077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ultra_low_pwr.2843022077
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.2527317960
Short name T580
Test name
Test status
Simulation time 2012060588 ps
CPU time 5.33 seconds
Started Aug 09 05:13:46 PM PDT 24
Finished Aug 09 05:13:51 PM PDT 24
Peak memory 200740 kb
Host smart-440e71e2-af39-41c3-88e0-3407e9b48920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527317960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.2527317960
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.3962096730
Short name T480
Test name
Test status
Simulation time 3468784865 ps
CPU time 4.6 seconds
Started Aug 09 05:13:47 PM PDT 24
Finished Aug 09 05:13:52 PM PDT 24
Peak memory 200748 kb
Host smart-d65a0189-4710-45d4-891a-b3eb38afd900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962096730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.3
962096730
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.1468520339
Short name T684
Test name
Test status
Simulation time 77099278208 ps
CPU time 75.52 seconds
Started Aug 09 05:13:44 PM PDT 24
Finished Aug 09 05:15:00 PM PDT 24
Peak memory 201088 kb
Host smart-f7edbc69-60cf-4b28-bd08-86f848fdd3b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468520339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_combo_detect.1468520339
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.83338913
Short name T786
Test name
Test status
Simulation time 25598465327 ps
CPU time 17.32 seconds
Started Aug 09 05:13:47 PM PDT 24
Finished Aug 09 05:14:04 PM PDT 24
Peak memory 201124 kb
Host smart-e6de4aa6-0b4c-4570-a971-c4edb5ed4e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83338913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_wit
h_pre_cond.83338913
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.4058610545
Short name T546
Test name
Test status
Simulation time 2680910167 ps
CPU time 2.29 seconds
Started Aug 09 05:13:40 PM PDT 24
Finished Aug 09 05:13:42 PM PDT 24
Peak memory 200700 kb
Host smart-49955a4f-4da8-4db6-a2e9-f3f6ef108fed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058610545 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.4058610545
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.3546119377
Short name T197
Test name
Test status
Simulation time 3920891997 ps
CPU time 2.61 seconds
Started Aug 09 05:13:45 PM PDT 24
Finished Aug 09 05:13:48 PM PDT 24
Peak memory 200812 kb
Host smart-82bf83a6-c54c-4364-a4d6-6a060d4f2098
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546119377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.3546119377
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.1165390884
Short name T50
Test name
Test status
Simulation time 2619168745 ps
CPU time 3.78 seconds
Started Aug 09 05:13:38 PM PDT 24
Finished Aug 09 05:13:42 PM PDT 24
Peak memory 199608 kb
Host smart-0edd0200-c51e-4abf-a801-3e8978f4f451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165390884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.1165390884
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.2256190328
Short name T613
Test name
Test status
Simulation time 2467343775 ps
CPU time 1.63 seconds
Started Aug 09 05:13:44 PM PDT 24
Finished Aug 09 05:13:45 PM PDT 24
Peak memory 200624 kb
Host smart-687441a6-00bd-47f9-9349-a754bfc9df33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256190328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.2256190328
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.2836550984
Short name T603
Test name
Test status
Simulation time 2185984656 ps
CPU time 3.77 seconds
Started Aug 09 05:13:40 PM PDT 24
Finished Aug 09 05:13:44 PM PDT 24
Peak memory 200784 kb
Host smart-9c88afae-33ba-41e2-b0ca-23b39f7e2a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836550984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.2836550984
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.190434651
Short name T677
Test name
Test status
Simulation time 2509323461 ps
CPU time 6.78 seconds
Started Aug 09 05:13:44 PM PDT 24
Finished Aug 09 05:13:50 PM PDT 24
Peak memory 200708 kb
Host smart-1cf2754c-7b3d-4c55-9fb6-ca86d8be3760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190434651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.190434651
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.1941679591
Short name T672
Test name
Test status
Simulation time 2152068536 ps
CPU time 1.41 seconds
Started Aug 09 05:13:43 PM PDT 24
Finished Aug 09 05:13:45 PM PDT 24
Peak memory 200732 kb
Host smart-c992079a-3b3a-4beb-88bd-b96aeba7f9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941679591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.1941679591
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.1112193673
Short name T582
Test name
Test status
Simulation time 15299150613 ps
CPU time 8.1 seconds
Started Aug 09 05:13:46 PM PDT 24
Finished Aug 09 05:13:54 PM PDT 24
Peak memory 200756 kb
Host smart-51f3cbd6-0c8e-43e8-bab9-2f3ac9db37d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112193673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.1112193673
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.3007094207
Short name T457
Test name
Test status
Simulation time 2687865565 ps
CPU time 6.23 seconds
Started Aug 09 05:13:44 PM PDT 24
Finished Aug 09 05:13:51 PM PDT 24
Peak memory 200860 kb
Host smart-d8037a92-58bb-49e7-8579-f9ca3310d508
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007094207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ultra_low_pwr.3007094207
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.2698700341
Short name T612
Test name
Test status
Simulation time 2013783301 ps
CPU time 5.19 seconds
Started Aug 09 05:13:50 PM PDT 24
Finished Aug 09 05:13:55 PM PDT 24
Peak memory 200820 kb
Host smart-6d69e50f-9da6-4eaa-9874-54445d61a23d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698700341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.2698700341
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.3864390696
Short name T569
Test name
Test status
Simulation time 268806777468 ps
CPU time 669.19 seconds
Started Aug 09 05:13:50 PM PDT 24
Finished Aug 09 05:24:59 PM PDT 24
Peak memory 200860 kb
Host smart-a323cdf6-32b8-4027-b93c-2389c5ab15b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864390696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.3
864390696
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.1796707997
Short name T191
Test name
Test status
Simulation time 104740917397 ps
CPU time 14.03 seconds
Started Aug 09 05:13:44 PM PDT 24
Finished Aug 09 05:13:58 PM PDT 24
Peak memory 201040 kb
Host smart-34e98baf-b127-4f35-b3be-4f144dc4692f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796707997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.1796707997
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3907451089
Short name T598
Test name
Test status
Simulation time 4473313541 ps
CPU time 6.45 seconds
Started Aug 09 05:13:50 PM PDT 24
Finished Aug 09 05:13:57 PM PDT 24
Peak memory 200756 kb
Host smart-6496af24-eb33-4699-b04e-dd743f374438
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907451089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.3907451089
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.226782326
Short name T212
Test name
Test status
Simulation time 3999353430 ps
CPU time 2.9 seconds
Started Aug 09 05:13:51 PM PDT 24
Finished Aug 09 05:13:54 PM PDT 24
Peak memory 200796 kb
Host smart-6123269d-f5b8-4a5f-a6ed-83fffe232856
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226782326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctr
l_edge_detect.226782326
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3450838006
Short name T623
Test name
Test status
Simulation time 2625409715 ps
CPU time 2.27 seconds
Started Aug 09 05:13:45 PM PDT 24
Finished Aug 09 05:13:48 PM PDT 24
Peak memory 200816 kb
Host smart-4ddb404c-fd34-4b38-b672-0257451fae0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450838006 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.3450838006
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.2899758637
Short name T238
Test name
Test status
Simulation time 2470203095 ps
CPU time 6.41 seconds
Started Aug 09 05:13:44 PM PDT 24
Finished Aug 09 05:13:51 PM PDT 24
Peak memory 200736 kb
Host smart-d7ce4629-fcd3-4001-8f66-9404e784dd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899758637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.2899758637
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.2468401017
Short name T530
Test name
Test status
Simulation time 2041551667 ps
CPU time 1.6 seconds
Started Aug 09 05:13:47 PM PDT 24
Finished Aug 09 05:13:49 PM PDT 24
Peak memory 200624 kb
Host smart-1a01674c-c94a-4ab5-8382-9b458630158c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468401017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.2468401017
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.2834706972
Short name T584
Test name
Test status
Simulation time 2529579343 ps
CPU time 2.4 seconds
Started Aug 09 05:13:47 PM PDT 24
Finished Aug 09 05:13:49 PM PDT 24
Peak memory 200764 kb
Host smart-2f46ca26-0f80-4a70-8068-cadb6f198de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834706972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.2834706972
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.1536181415
Short name T707
Test name
Test status
Simulation time 2113146529 ps
CPU time 5.97 seconds
Started Aug 09 05:13:51 PM PDT 24
Finished Aug 09 05:13:57 PM PDT 24
Peak memory 200688 kb
Host smart-19fa7ea6-82e0-47a4-8ecd-5f5b240119d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536181415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.1536181415
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.1249232534
Short name T138
Test name
Test status
Simulation time 6880014651 ps
CPU time 8.31 seconds
Started Aug 09 05:13:47 PM PDT 24
Finished Aug 09 05:13:56 PM PDT 24
Peak memory 200824 kb
Host smart-7e35b469-0dcc-4d64-98ac-97c04e5ec115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249232534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_s
tress_all.1249232534
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2886997440
Short name T303
Test name
Test status
Simulation time 71993394573 ps
CPU time 74.31 seconds
Started Aug 09 05:13:47 PM PDT 24
Finished Aug 09 05:15:02 PM PDT 24
Peak memory 213608 kb
Host smart-6a87cacb-ea6f-45ec-838d-2408357a3ab4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886997440 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.2886997440
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.2413742567
Short name T128
Test name
Test status
Simulation time 1297522996529 ps
CPU time 225.58 seconds
Started Aug 09 05:13:45 PM PDT 24
Finished Aug 09 05:17:30 PM PDT 24
Peak memory 200876 kb
Host smart-c4677262-79fa-47ac-813f-26dcdf15c140
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413742567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.2413742567
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.4181600130
Short name T531
Test name
Test status
Simulation time 2028967327 ps
CPU time 1.93 seconds
Started Aug 09 05:13:46 PM PDT 24
Finished Aug 09 05:13:48 PM PDT 24
Peak memory 200764 kb
Host smart-fc7bfa71-2769-42ff-a088-4d326938e22e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181600130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.4181600130
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.916670916
Short name T453
Test name
Test status
Simulation time 3279057310 ps
CPU time 1.07 seconds
Started Aug 09 05:13:44 PM PDT 24
Finished Aug 09 05:13:45 PM PDT 24
Peak memory 200916 kb
Host smart-5644b11d-6aa2-423f-b0af-4ea0f9151d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916670916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.916670916
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.580092183
Short name T271
Test name
Test status
Simulation time 125799004663 ps
CPU time 80.08 seconds
Started Aug 09 05:13:47 PM PDT 24
Finished Aug 09 05:15:07 PM PDT 24
Peak memory 201004 kb
Host smart-2425e7b9-04e6-4ad8-9fe6-36e5006dbf91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580092183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_combo_detect.580092183
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3737257072
Short name T361
Test name
Test status
Simulation time 99921893247 ps
CPU time 28.03 seconds
Started Aug 09 05:13:46 PM PDT 24
Finished Aug 09 05:14:15 PM PDT 24
Peak memory 201084 kb
Host smart-195630ec-3df2-4029-a28d-36bc11ffc2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737257072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.3737257072
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3268486395
Short name T667
Test name
Test status
Simulation time 3148103484 ps
CPU time 8.26 seconds
Started Aug 09 05:13:44 PM PDT 24
Finished Aug 09 05:13:53 PM PDT 24
Peak memory 200724 kb
Host smart-c62696f9-aa76-40d0-91d3-30217e7915f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268486395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ec_pwr_on_rst.3268486395
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.2539563418
Short name T661
Test name
Test status
Simulation time 826558922463 ps
CPU time 565.61 seconds
Started Aug 09 05:13:51 PM PDT 24
Finished Aug 09 05:23:17 PM PDT 24
Peak memory 200796 kb
Host smart-abef20f6-e804-4a43-a129-82957c70d4e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539563418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.2539563418
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.2216154770
Short name T681
Test name
Test status
Simulation time 2612399398 ps
CPU time 7.11 seconds
Started Aug 09 05:13:45 PM PDT 24
Finished Aug 09 05:13:52 PM PDT 24
Peak memory 200860 kb
Host smart-8307cdb3-ae82-4237-8ff5-dde4b8200a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216154770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.2216154770
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.1993756775
Short name T460
Test name
Test status
Simulation time 2479714924 ps
CPU time 2.62 seconds
Started Aug 09 05:13:45 PM PDT 24
Finished Aug 09 05:13:48 PM PDT 24
Peak memory 200756 kb
Host smart-d7164d51-8561-4c44-85ca-817c0aeb083c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993756775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.1993756775
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.2659368968
Short name T262
Test name
Test status
Simulation time 2018165026 ps
CPU time 5.16 seconds
Started Aug 09 05:13:48 PM PDT 24
Finished Aug 09 05:13:53 PM PDT 24
Peak memory 200988 kb
Host smart-e90a1a9a-4dda-4809-905e-a8451ce4e66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659368968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.2659368968
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.3209664255
Short name T528
Test name
Test status
Simulation time 2536440611 ps
CPU time 1.88 seconds
Started Aug 09 05:13:48 PM PDT 24
Finished Aug 09 05:13:50 PM PDT 24
Peak memory 200672 kb
Host smart-e575a529-4487-42c6-a241-93a663d933ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209664255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.3209664255
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.800405968
Short name T742
Test name
Test status
Simulation time 2120095494 ps
CPU time 3.27 seconds
Started Aug 09 05:13:45 PM PDT 24
Finished Aug 09 05:13:49 PM PDT 24
Peak memory 200644 kb
Host smart-5aebbfb6-1bb7-44b2-b667-356a0bfa4dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800405968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.800405968
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.238618336
Short name T154
Test name
Test status
Simulation time 15098521760 ps
CPU time 4.36 seconds
Started Aug 09 05:13:47 PM PDT 24
Finished Aug 09 05:13:52 PM PDT 24
Peak memory 200736 kb
Host smart-c048e6c7-21f4-4455-ace3-c7cc3ed94e4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238618336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_st
ress_all.238618336
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.1558767633
Short name T592
Test name
Test status
Simulation time 5140482953 ps
CPU time 1.77 seconds
Started Aug 09 05:13:47 PM PDT 24
Finished Aug 09 05:13:49 PM PDT 24
Peak memory 200832 kb
Host smart-caf5f2da-a9b7-4d4c-855a-30007be96289
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558767633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.1558767633
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.3457147431
Short name T792
Test name
Test status
Simulation time 2094441084 ps
CPU time 0.98 seconds
Started Aug 09 05:13:52 PM PDT 24
Finished Aug 09 05:13:53 PM PDT 24
Peak memory 200744 kb
Host smart-0c534908-cfc7-4349-8c49-c2622a5db8e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457147431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.3457147431
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.1105613619
Short name T638
Test name
Test status
Simulation time 3181391268 ps
CPU time 2.7 seconds
Started Aug 09 05:13:52 PM PDT 24
Finished Aug 09 05:13:55 PM PDT 24
Peak memory 200808 kb
Host smart-a44f375c-bcd1-4e2c-99d8-d1a846b42794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105613619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.1
105613619
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.714885140
Short name T207
Test name
Test status
Simulation time 98454426388 ps
CPU time 116.04 seconds
Started Aug 09 05:13:52 PM PDT 24
Finished Aug 09 05:15:49 PM PDT 24
Peak memory 201048 kb
Host smart-a48c4b2c-f5ec-42e1-b2ad-616260d3833b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714885140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_combo_detect.714885140
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2835595564
Short name T513
Test name
Test status
Simulation time 49012329135 ps
CPU time 30.17 seconds
Started Aug 09 05:13:52 PM PDT 24
Finished Aug 09 05:14:22 PM PDT 24
Peak memory 201032 kb
Host smart-c34e63e5-dfcb-4c2f-ad21-1d54c209e48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835595564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.2835595564
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.2719713506
Short name T219
Test name
Test status
Simulation time 4378346531 ps
CPU time 2.46 seconds
Started Aug 09 05:13:53 PM PDT 24
Finished Aug 09 05:13:55 PM PDT 24
Peak memory 200684 kb
Host smart-b3c8cafb-162c-450d-b797-a9c7861a3bfe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719713506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ec_pwr_on_rst.2719713506
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.2974021201
Short name T682
Test name
Test status
Simulation time 2659758874 ps
CPU time 2.19 seconds
Started Aug 09 05:13:53 PM PDT 24
Finished Aug 09 05:13:55 PM PDT 24
Peak memory 200744 kb
Host smart-5ca082db-e186-4ac4-999b-b8677a4d8e9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974021201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.2974021201
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.3119440794
Short name T734
Test name
Test status
Simulation time 2625406562 ps
CPU time 2.19 seconds
Started Aug 09 05:13:51 PM PDT 24
Finished Aug 09 05:13:53 PM PDT 24
Peak memory 200800 kb
Host smart-c153d70a-c2c5-4273-a398-1c050cb23fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119440794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.3119440794
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.1608473963
Short name T410
Test name
Test status
Simulation time 2480614414 ps
CPU time 2.56 seconds
Started Aug 09 05:13:56 PM PDT 24
Finished Aug 09 05:13:59 PM PDT 24
Peak memory 200704 kb
Host smart-20316c35-202f-4643-a0df-ed3c75da962b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608473963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.1608473963
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.132649540
Short name T240
Test name
Test status
Simulation time 2041426434 ps
CPU time 3.01 seconds
Started Aug 09 05:13:53 PM PDT 24
Finished Aug 09 05:13:56 PM PDT 24
Peak memory 200660 kb
Host smart-d5eee4c3-149c-4ba1-be8a-f0af08240fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132649540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.132649540
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.788892863
Short name T149
Test name
Test status
Simulation time 2521048061 ps
CPU time 3.81 seconds
Started Aug 09 05:13:50 PM PDT 24
Finished Aug 09 05:13:55 PM PDT 24
Peak memory 200732 kb
Host smart-fc7b3c40-85dc-4899-9206-be4b04bf887b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788892863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.788892863
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.2030299354
Short name T258
Test name
Test status
Simulation time 2136104062 ps
CPU time 1.29 seconds
Started Aug 09 05:13:50 PM PDT 24
Finished Aug 09 05:13:52 PM PDT 24
Peak memory 200636 kb
Host smart-fb5374cd-337e-4bba-a7cf-8ccc89457a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030299354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.2030299354
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.435387098
Short name T532
Test name
Test status
Simulation time 13481636788 ps
CPU time 9.8 seconds
Started Aug 09 05:13:57 PM PDT 24
Finished Aug 09 05:14:07 PM PDT 24
Peak memory 200800 kb
Host smart-3275e6c5-c65e-4d32-9da8-a28ae66838d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435387098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_st
ress_all.435387098
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1117168407
Short name T611
Test name
Test status
Simulation time 13111957209 ps
CPU time 31.02 seconds
Started Aug 09 05:13:51 PM PDT 24
Finished Aug 09 05:14:23 PM PDT 24
Peak memory 201160 kb
Host smart-7ebd8cf5-39c0-4bd5-babb-1cffd4c1f06a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117168407 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.1117168407
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.2354055881
Short name T223
Test name
Test status
Simulation time 5702889060 ps
CPU time 3.4 seconds
Started Aug 09 05:13:56 PM PDT 24
Finished Aug 09 05:14:00 PM PDT 24
Peak memory 200776 kb
Host smart-670c9172-9896-4c60-9bcb-067a76ab0e22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354055881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.2354055881
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.2329982836
Short name T599
Test name
Test status
Simulation time 2025307494 ps
CPU time 1.75 seconds
Started Aug 09 05:13:56 PM PDT 24
Finished Aug 09 05:13:58 PM PDT 24
Peak memory 200644 kb
Host smart-add0ee92-b393-4779-98e7-e4555ac19ea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329982836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.2329982836
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.4255600552
Short name T621
Test name
Test status
Simulation time 3031130240 ps
CPU time 8.14 seconds
Started Aug 09 05:13:51 PM PDT 24
Finished Aug 09 05:13:59 PM PDT 24
Peak memory 200808 kb
Host smart-67d696c0-9e37-40fe-ba78-8985748deec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255600552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.4
255600552
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.127627144
Short name T33
Test name
Test status
Simulation time 60423767962 ps
CPU time 123.73 seconds
Started Aug 09 05:13:53 PM PDT 24
Finished Aug 09 05:15:57 PM PDT 24
Peak memory 201132 kb
Host smart-a651331c-e2c9-44ac-ac17-b5cf3ce3e14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127627144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_wi
th_pre_cond.127627144
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.792553115
Short name T435
Test name
Test status
Simulation time 2801097389 ps
CPU time 7.69 seconds
Started Aug 09 05:13:53 PM PDT 24
Finished Aug 09 05:14:01 PM PDT 24
Peak memory 200804 kb
Host smart-f4525cc8-4f12-462d-a830-59ca24243901
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792553115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_ec_pwr_on_rst.792553115
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.4203934182
Short name T176
Test name
Test status
Simulation time 3397422941 ps
CPU time 3.39 seconds
Started Aug 09 05:13:53 PM PDT 24
Finished Aug 09 05:13:57 PM PDT 24
Peak memory 200780 kb
Host smart-bafc9beb-bccb-4c6e-923e-763bf355e56c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203934182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_edge_detect.4203934182
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.2152638113
Short name T686
Test name
Test status
Simulation time 2610295453 ps
CPU time 7.55 seconds
Started Aug 09 05:13:53 PM PDT 24
Finished Aug 09 05:14:00 PM PDT 24
Peak memory 200768 kb
Host smart-3078a97f-8993-4696-9319-325e8d7fca15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152638113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.2152638113
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.1375981751
Short name T184
Test name
Test status
Simulation time 2453541513 ps
CPU time 6.21 seconds
Started Aug 09 05:13:50 PM PDT 24
Finished Aug 09 05:13:56 PM PDT 24
Peak memory 200820 kb
Host smart-9d9c54fa-2ee2-4148-baf6-177ae5af2037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375981751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.1375981751
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.3682896480
Short name T426
Test name
Test status
Simulation time 2289548964 ps
CPU time 1.48 seconds
Started Aug 09 05:13:53 PM PDT 24
Finished Aug 09 05:13:54 PM PDT 24
Peak memory 200816 kb
Host smart-d53e2e0c-2007-4e57-b979-c3f4e24afef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682896480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.3682896480
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.244942370
Short name T106
Test name
Test status
Simulation time 2512238886 ps
CPU time 7.11 seconds
Started Aug 09 05:13:53 PM PDT 24
Finished Aug 09 05:14:00 PM PDT 24
Peak memory 200816 kb
Host smart-f95fe23e-22a2-4d54-9b72-78667ff7e339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244942370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.244942370
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.3936192373
Short name T181
Test name
Test status
Simulation time 2109876062 ps
CPU time 6.15 seconds
Started Aug 09 05:13:52 PM PDT 24
Finished Aug 09 05:13:59 PM PDT 24
Peak memory 200676 kb
Host smart-9929595e-d297-479f-866c-09548fc8610d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936192373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.3936192373
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.269233745
Short name T514
Test name
Test status
Simulation time 11736529837 ps
CPU time 30.3 seconds
Started Aug 09 05:13:52 PM PDT 24
Finished Aug 09 05:14:23 PM PDT 24
Peak memory 200824 kb
Host smart-fe99386d-6456-4c1d-8374-693ab3d5e35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269233745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_st
ress_all.269233745
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.3541188003
Short name T123
Test name
Test status
Simulation time 35113048694 ps
CPU time 80.86 seconds
Started Aug 09 05:13:58 PM PDT 24
Finished Aug 09 05:15:19 PM PDT 24
Peak memory 216736 kb
Host smart-1fba201a-7ddc-41a3-be3e-4c3e73bb100b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541188003 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.3541188003
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.1975887257
Short name T693
Test name
Test status
Simulation time 14816878590 ps
CPU time 2.47 seconds
Started Aug 09 05:13:53 PM PDT 24
Finished Aug 09 05:13:55 PM PDT 24
Peak memory 200748 kb
Host smart-cd97527e-3e6a-493b-a97d-c08002834baf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975887257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ultra_low_pwr.1975887257
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.3348188736
Short name T433
Test name
Test status
Simulation time 2030897643 ps
CPU time 1.99 seconds
Started Aug 09 05:13:59 PM PDT 24
Finished Aug 09 05:14:01 PM PDT 24
Peak memory 200696 kb
Host smart-94a345c0-d9e8-4409-9a63-c715629f9034
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348188736 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.3348188736
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2158093155
Short name T605
Test name
Test status
Simulation time 3204936707 ps
CPU time 1.4 seconds
Started Aug 09 05:13:54 PM PDT 24
Finished Aug 09 05:13:55 PM PDT 24
Peak memory 200716 kb
Host smart-9fcf7ed3-20f5-40d8-adee-3d0a401db0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158093155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.2
158093155
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.1932099755
Short name T378
Test name
Test status
Simulation time 162981239168 ps
CPU time 91.82 seconds
Started Aug 09 05:13:56 PM PDT 24
Finished Aug 09 05:15:28 PM PDT 24
Peak memory 200968 kb
Host smart-e77535db-91ae-4808-bf0a-59ebcb5224e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932099755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.1932099755
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.218233789
Short name T246
Test name
Test status
Simulation time 33089372397 ps
CPU time 42.36 seconds
Started Aug 09 05:13:59 PM PDT 24
Finished Aug 09 05:14:41 PM PDT 24
Peak memory 200964 kb
Host smart-74f2054b-5c17-4ad8-bb07-6296563cfd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218233789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_wi
th_pre_cond.218233789
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.4190528731
Short name T391
Test name
Test status
Simulation time 4430429100 ps
CPU time 12.47 seconds
Started Aug 09 05:13:54 PM PDT 24
Finished Aug 09 05:14:07 PM PDT 24
Peak memory 200728 kb
Host smart-e56ca9eb-180a-46f6-9fb6-6fdbe56e058b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190528731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ec_pwr_on_rst.4190528731
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.4245098224
Short name T10
Test name
Test status
Simulation time 2904043907 ps
CPU time 1.63 seconds
Started Aug 09 05:14:03 PM PDT 24
Finished Aug 09 05:14:05 PM PDT 24
Peak memory 200796 kb
Host smart-1c416a14-c360-4a3c-9826-1196f12dd3f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245098224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.4245098224
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1489288331
Short name T642
Test name
Test status
Simulation time 2626886129 ps
CPU time 2.23 seconds
Started Aug 09 05:13:50 PM PDT 24
Finished Aug 09 05:13:53 PM PDT 24
Peak memory 200780 kb
Host smart-4421085a-f037-44b2-bd4a-c98144d17ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489288331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.1489288331
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.3906219728
Short name T305
Test name
Test status
Simulation time 2442282637 ps
CPU time 6.82 seconds
Started Aug 09 05:13:57 PM PDT 24
Finished Aug 09 05:14:04 PM PDT 24
Peak memory 200732 kb
Host smart-193512d6-3fc0-4585-ae15-5b6882b6e381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906219728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.3906219728
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.2934487880
Short name T209
Test name
Test status
Simulation time 2247630578 ps
CPU time 2.16 seconds
Started Aug 09 05:13:58 PM PDT 24
Finished Aug 09 05:14:00 PM PDT 24
Peak memory 200720 kb
Host smart-ddf927dd-2e84-4e62-b6ac-77b50568d254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934487880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.2934487880
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3658908628
Short name T64
Test name
Test status
Simulation time 2555223899 ps
CPU time 1.79 seconds
Started Aug 09 05:13:52 PM PDT 24
Finished Aug 09 05:13:54 PM PDT 24
Peak memory 200748 kb
Host smart-785edb30-7638-496d-8e70-3a2e865d6afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658908628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.3658908628
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.316090417
Short name T716
Test name
Test status
Simulation time 2110703244 ps
CPU time 5.52 seconds
Started Aug 09 05:13:56 PM PDT 24
Finished Aug 09 05:14:02 PM PDT 24
Peak memory 200644 kb
Host smart-e7a04675-6274-49cb-88ff-4a825867eaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316090417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.316090417
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.2188132351
Short name T259
Test name
Test status
Simulation time 24252076505 ps
CPU time 65.18 seconds
Started Aug 09 05:14:02 PM PDT 24
Finished Aug 09 05:15:08 PM PDT 24
Peak memory 200824 kb
Host smart-0bc2ab79-d443-42ab-82a3-6854a3e1435f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188132351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.2188132351
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.411348231
Short name T105
Test name
Test status
Simulation time 67934266054 ps
CPU time 49.23 seconds
Started Aug 09 05:14:01 PM PDT 24
Finished Aug 09 05:14:50 PM PDT 24
Peak memory 217440 kb
Host smart-3962aa81-671b-4ff3-92e4-500c1610172d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411348231 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.411348231
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.2840837264
Short name T465
Test name
Test status
Simulation time 4007770066 ps
CPU time 2.04 seconds
Started Aug 09 05:13:56 PM PDT 24
Finished Aug 09 05:13:58 PM PDT 24
Peak memory 200772 kb
Host smart-e7cb8ec6-ea87-4f76-bcad-17bc7f601eaf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840837264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ultra_low_pwr.2840837264
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.37546045
Short name T780
Test name
Test status
Simulation time 2017067543 ps
CPU time 3.29 seconds
Started Aug 09 05:14:02 PM PDT 24
Finished Aug 09 05:14:06 PM PDT 24
Peak memory 200764 kb
Host smart-e2dc51cf-d466-45e5-a89b-f24f85890e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37546045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_test
.37546045
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.3548604966
Short name T714
Test name
Test status
Simulation time 3742220077 ps
CPU time 3.33 seconds
Started Aug 09 05:14:01 PM PDT 24
Finished Aug 09 05:14:04 PM PDT 24
Peak memory 200856 kb
Host smart-f412e53e-be4c-4544-97ad-57e9a2ed945a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548604966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.3
548604966
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.184704883
Short name T748
Test name
Test status
Simulation time 76914377849 ps
CPU time 11.33 seconds
Started Aug 09 05:13:59 PM PDT 24
Finished Aug 09 05:14:10 PM PDT 24
Peak memory 201064 kb
Host smart-3dca74b8-28bf-476e-ade2-f301fca459c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184704883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_combo_detect.184704883
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.4276829676
Short name T412
Test name
Test status
Simulation time 4137446272 ps
CPU time 1.79 seconds
Started Aug 09 05:13:59 PM PDT 24
Finished Aug 09 05:14:01 PM PDT 24
Peak memory 200700 kb
Host smart-71a76228-09c3-47e7-9ae1-cdf3ee20eccd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276829676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.4276829676
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.2266985167
Short name T39
Test name
Test status
Simulation time 2597736827 ps
CPU time 2.48 seconds
Started Aug 09 05:14:00 PM PDT 24
Finished Aug 09 05:14:02 PM PDT 24
Peak memory 200792 kb
Host smart-ce4707d8-da96-41e2-858b-ae3982a62a36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266985167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.2266985167
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.3957038693
Short name T790
Test name
Test status
Simulation time 2613300509 ps
CPU time 7.62 seconds
Started Aug 09 05:13:59 PM PDT 24
Finished Aug 09 05:14:07 PM PDT 24
Peak memory 200752 kb
Host smart-c9f548ec-4656-4150-a2b4-2a773042608f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957038693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.3957038693
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.396514758
Short name T467
Test name
Test status
Simulation time 2503914480 ps
CPU time 2.41 seconds
Started Aug 09 05:14:00 PM PDT 24
Finished Aug 09 05:14:02 PM PDT 24
Peak memory 200688 kb
Host smart-8beed747-039f-4199-8b37-93f50b5c7d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396514758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.396514758
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.1283900209
Short name T675
Test name
Test status
Simulation time 2212800166 ps
CPU time 6.62 seconds
Started Aug 09 05:14:02 PM PDT 24
Finished Aug 09 05:14:09 PM PDT 24
Peak memory 200748 kb
Host smart-23256852-52b9-448d-8ed7-6efed0fcf72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283900209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.1283900209
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.4035972803
Short name T469
Test name
Test status
Simulation time 2508410063 ps
CPU time 7.21 seconds
Started Aug 09 05:14:01 PM PDT 24
Finished Aug 09 05:14:08 PM PDT 24
Peak memory 200760 kb
Host smart-d0c5c245-15ee-467c-8fac-da785a15bd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035972803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.4035972803
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.3214791460
Short name T745
Test name
Test status
Simulation time 2117849853 ps
CPU time 3.08 seconds
Started Aug 09 05:14:02 PM PDT 24
Finished Aug 09 05:14:05 PM PDT 24
Peak memory 200712 kb
Host smart-dcd71928-4c8d-4d3c-920b-d270b3b7336c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214791460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.3214791460
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.192416095
Short name T771
Test name
Test status
Simulation time 13440794475 ps
CPU time 33.78 seconds
Started Aug 09 05:14:00 PM PDT 24
Finished Aug 09 05:14:34 PM PDT 24
Peak memory 200800 kb
Host smart-0dc363b1-1c7b-41e1-ba27-b7e42017a7f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192416095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_st
ress_all.192416095
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.677682153
Short name T679
Test name
Test status
Simulation time 9434122583 ps
CPU time 9.41 seconds
Started Aug 09 05:14:00 PM PDT 24
Finished Aug 09 05:14:10 PM PDT 24
Peak memory 200812 kb
Host smart-2e29d5c8-c097-4f04-81a5-a6ee4b127704
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677682153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_ultra_low_pwr.677682153
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.2887801634
Short name T551
Test name
Test status
Simulation time 2017052062 ps
CPU time 5.65 seconds
Started Aug 09 05:14:06 PM PDT 24
Finished Aug 09 05:14:11 PM PDT 24
Peak memory 200780 kb
Host smart-1056c776-cbd1-4a29-b50e-8a8c17ca25aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887801634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.2887801634
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.1619522433
Short name T45
Test name
Test status
Simulation time 3695770190 ps
CPU time 5.14 seconds
Started Aug 09 05:14:07 PM PDT 24
Finished Aug 09 05:14:12 PM PDT 24
Peak memory 200736 kb
Host smart-705ceaae-8cdf-46b8-8304-d47010317138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619522433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.1
619522433
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.2432279839
Short name T338
Test name
Test status
Simulation time 89488876262 ps
CPU time 233.48 seconds
Started Aug 09 05:14:05 PM PDT 24
Finished Aug 09 05:17:58 PM PDT 24
Peak memory 201020 kb
Host smart-183bb5d7-b135-4ccf-aa9f-a91b357a102b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432279839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.2432279839
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.1433160620
Short name T22
Test name
Test status
Simulation time 50263516367 ps
CPU time 127.01 seconds
Started Aug 09 05:14:14 PM PDT 24
Finished Aug 09 05:16:21 PM PDT 24
Peak memory 201104 kb
Host smart-3b9ff61d-ac6d-4a57-9d58-d405b777f67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433160620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_w
ith_pre_cond.1433160620
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.526219058
Short name T510
Test name
Test status
Simulation time 5532746338 ps
CPU time 4.57 seconds
Started Aug 09 05:14:10 PM PDT 24
Finished Aug 09 05:14:15 PM PDT 24
Peak memory 200744 kb
Host smart-03ea3a89-c66a-4255-8940-9124bd90f697
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526219058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_ec_pwr_on_rst.526219058
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.2603488038
Short name T725
Test name
Test status
Simulation time 2853560811 ps
CPU time 2.42 seconds
Started Aug 09 05:14:08 PM PDT 24
Finished Aug 09 05:14:11 PM PDT 24
Peak memory 200776 kb
Host smart-093606da-00a9-4316-b29f-783e96cb4478
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603488038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.2603488038
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.3329287138
Short name T502
Test name
Test status
Simulation time 2612626791 ps
CPU time 7.59 seconds
Started Aug 09 05:14:08 PM PDT 24
Finished Aug 09 05:14:16 PM PDT 24
Peak memory 200740 kb
Host smart-2f788da6-9ae8-4c69-9ae1-ba29d78219d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329287138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.3329287138
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.3262812283
Short name T637
Test name
Test status
Simulation time 2457591168 ps
CPU time 3.91 seconds
Started Aug 09 05:14:01 PM PDT 24
Finished Aug 09 05:14:05 PM PDT 24
Peak memory 201056 kb
Host smart-c628d661-e298-4a43-a680-edef7ce723a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262812283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.3262812283
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.412508067
Short name T413
Test name
Test status
Simulation time 2132391398 ps
CPU time 6.46 seconds
Started Aug 09 05:14:05 PM PDT 24
Finished Aug 09 05:14:12 PM PDT 24
Peak memory 200760 kb
Host smart-6e73ee27-88a5-4513-8a7b-18fba52074c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412508067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.412508067
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.3779216597
Short name T168
Test name
Test status
Simulation time 2511689144 ps
CPU time 4.13 seconds
Started Aug 09 05:14:05 PM PDT 24
Finished Aug 09 05:14:09 PM PDT 24
Peak memory 200748 kb
Host smart-e82c08cf-4e93-4fbe-a562-48ea8b8c923d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779216597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.3779216597
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.3755620520
Short name T414
Test name
Test status
Simulation time 2109690859 ps
CPU time 5.99 seconds
Started Aug 09 05:14:00 PM PDT 24
Finished Aug 09 05:14:06 PM PDT 24
Peak memory 200672 kb
Host smart-589f5d07-ef12-4fb7-8700-e47aa81dd1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755620520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.3755620520
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.4180389211
Short name T493
Test name
Test status
Simulation time 15288548569 ps
CPU time 31.51 seconds
Started Aug 09 05:14:07 PM PDT 24
Finished Aug 09 05:14:39 PM PDT 24
Peak memory 200784 kb
Host smart-4897aef0-7af2-44ab-ba01-9c8e46a182e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180389211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s
tress_all.4180389211
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.987278379
Short name T175
Test name
Test status
Simulation time 237747004453 ps
CPU time 164.13 seconds
Started Aug 09 05:14:17 PM PDT 24
Finished Aug 09 05:17:01 PM PDT 24
Peak memory 209384 kb
Host smart-03dcee40-59d7-4db2-855f-69516b203b2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987278379 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.987278379
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.1555135575
Short name T129
Test name
Test status
Simulation time 1846993402290 ps
CPU time 31.2 seconds
Started Aug 09 05:14:07 PM PDT 24
Finished Aug 09 05:14:38 PM PDT 24
Peak memory 201176 kb
Host smart-3d59a6d4-5cee-45f2-b17b-1e6e165fa228
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555135575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ultra_low_pwr.1555135575
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.2323991248
Short name T628
Test name
Test status
Simulation time 2013878661 ps
CPU time 5.3 seconds
Started Aug 09 05:14:06 PM PDT 24
Finished Aug 09 05:14:12 PM PDT 24
Peak memory 200796 kb
Host smart-7abe1c91-f52c-4a03-a526-dab33c3ec159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323991248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.2323991248
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.1179972742
Short name T507
Test name
Test status
Simulation time 255640764295 ps
CPU time 632.15 seconds
Started Aug 09 05:14:07 PM PDT 24
Finished Aug 09 05:24:39 PM PDT 24
Peak memory 200796 kb
Host smart-b7088722-a0cd-400a-9829-bde27bad9559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179972742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.1
179972742
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.2599454413
Short name T764
Test name
Test status
Simulation time 100901145160 ps
CPU time 25.95 seconds
Started Aug 09 05:14:17 PM PDT 24
Finished Aug 09 05:14:43 PM PDT 24
Peak memory 201124 kb
Host smart-be816544-7308-4451-abb2-6836089b5aa8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599454413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.2599454413
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.216344997
Short name T536
Test name
Test status
Simulation time 26081191143 ps
CPU time 63.32 seconds
Started Aug 09 05:14:06 PM PDT 24
Finished Aug 09 05:15:09 PM PDT 24
Peak memory 201128 kb
Host smart-9a3b8677-9af9-4760-bc87-a516be99764f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216344997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_wi
th_pre_cond.216344997
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.1004977204
Short name T235
Test name
Test status
Simulation time 4324876358 ps
CPU time 5.7 seconds
Started Aug 09 05:14:07 PM PDT 24
Finished Aug 09 05:14:12 PM PDT 24
Peak memory 200744 kb
Host smart-6315c359-3154-4b98-8313-ea84f216965f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004977204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ec_pwr_on_rst.1004977204
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.3356663819
Short name T203
Test name
Test status
Simulation time 3857291940 ps
CPU time 2.67 seconds
Started Aug 09 05:14:07 PM PDT 24
Finished Aug 09 05:14:09 PM PDT 24
Peak memory 200796 kb
Host smart-ce0bfe1c-8934-4243-92ce-ba16bed98b60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356663819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.3356663819
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.3443921247
Short name T137
Test name
Test status
Simulation time 2615869411 ps
CPU time 5.04 seconds
Started Aug 09 05:14:07 PM PDT 24
Finished Aug 09 05:14:12 PM PDT 24
Peak memory 200816 kb
Host smart-71f6c298-433f-4ef4-a61e-88e9a3507984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443921247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.3443921247
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.3058250620
Short name T753
Test name
Test status
Simulation time 2492474561 ps
CPU time 2.38 seconds
Started Aug 09 05:14:17 PM PDT 24
Finished Aug 09 05:14:20 PM PDT 24
Peak memory 200820 kb
Host smart-40b7df64-503d-409d-9caf-93d3f04b02fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058250620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.3058250620
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.4190723558
Short name T438
Test name
Test status
Simulation time 2069471051 ps
CPU time 5.42 seconds
Started Aug 09 05:14:08 PM PDT 24
Finished Aug 09 05:14:14 PM PDT 24
Peak memory 200760 kb
Host smart-8735a09a-bda2-4039-a18e-5fbf895c7ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190723558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.4190723558
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.3472741936
Short name T483
Test name
Test status
Simulation time 2528069255 ps
CPU time 2.32 seconds
Started Aug 09 05:14:05 PM PDT 24
Finished Aug 09 05:14:08 PM PDT 24
Peak memory 200720 kb
Host smart-57b1ee4b-c57a-4a14-af5d-91cc2f6d8193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472741936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.3472741936
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.132120659
Short name T476
Test name
Test status
Simulation time 2125228093 ps
CPU time 1.91 seconds
Started Aug 09 05:14:07 PM PDT 24
Finished Aug 09 05:14:09 PM PDT 24
Peak memory 200712 kb
Host smart-f0869c37-ecbf-490d-b3de-e9786251bc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132120659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.132120659
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.2130313933
Short name T293
Test name
Test status
Simulation time 30997422316 ps
CPU time 21.44 seconds
Started Aug 09 05:14:05 PM PDT 24
Finished Aug 09 05:14:27 PM PDT 24
Peak memory 200820 kb
Host smart-6ba88cf4-d785-48ef-8aa1-c9a164991bb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130313933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.2130313933
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.3615286520
Short name T478
Test name
Test status
Simulation time 2023093507 ps
CPU time 1.97 seconds
Started Aug 09 05:12:48 PM PDT 24
Finished Aug 09 05:12:50 PM PDT 24
Peak memory 200764 kb
Host smart-e1589c00-7f35-455d-98a1-892a4a49b35c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615286520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.3615286520
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.4058475825
Short name T709
Test name
Test status
Simulation time 3814818052 ps
CPU time 5.47 seconds
Started Aug 09 05:12:52 PM PDT 24
Finished Aug 09 05:12:58 PM PDT 24
Peak memory 200784 kb
Host smart-b5c382b1-563f-48f0-a359-ff45b689d620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058475825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.4058475825
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.2895011524
Short name T270
Test name
Test status
Simulation time 123714266978 ps
CPU time 63.23 seconds
Started Aug 09 05:12:49 PM PDT 24
Finished Aug 09 05:13:53 PM PDT 24
Peak memory 200928 kb
Host smart-875d3c35-201b-4287-bc2e-10e97eb1cfa8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895011524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.2895011524
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.252900608
Short name T589
Test name
Test status
Simulation time 2237871138 ps
CPU time 3.63 seconds
Started Aug 09 05:12:44 PM PDT 24
Finished Aug 09 05:12:48 PM PDT 24
Peak memory 200716 kb
Host smart-13f1e4c8-46e0-4fd7-b6ad-a36d74b96aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252900608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.252900608
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1807438317
Short name T255
Test name
Test status
Simulation time 2269103621 ps
CPU time 5.9 seconds
Started Aug 09 05:12:47 PM PDT 24
Finished Aug 09 05:12:53 PM PDT 24
Peak memory 200712 kb
Host smart-bb7ea411-bc4c-4886-bab5-3f7f4de7e495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807438317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1807438317
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1780466092
Short name T216
Test name
Test status
Simulation time 25360977933 ps
CPU time 16.33 seconds
Started Aug 09 05:12:48 PM PDT 24
Finished Aug 09 05:13:04 PM PDT 24
Peak memory 201224 kb
Host smart-b4268763-eee5-4ed9-b24b-bd4bbe51cf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780466092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.1780466092
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.3418015071
Short name T394
Test name
Test status
Simulation time 3456594761 ps
CPU time 9.08 seconds
Started Aug 09 05:12:48 PM PDT 24
Finished Aug 09 05:12:57 PM PDT 24
Peak memory 200792 kb
Host smart-4b6d1cb2-59ba-4fb7-baa2-3ded79faa53d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418015071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.3418015071
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.3828667365
Short name T758
Test name
Test status
Simulation time 4156825994 ps
CPU time 11.68 seconds
Started Aug 09 05:12:50 PM PDT 24
Finished Aug 09 05:13:02 PM PDT 24
Peak memory 200800 kb
Host smart-80d617c4-29d6-4f12-9815-9c12f0584727
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828667365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.3828667365
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2350391618
Short name T436
Test name
Test status
Simulation time 2610109622 ps
CPU time 7.22 seconds
Started Aug 09 05:12:49 PM PDT 24
Finished Aug 09 05:12:56 PM PDT 24
Peak memory 200764 kb
Host smart-2060b3a0-c8dd-43ce-a0b4-7dc504824e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350391618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.2350391618
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.1744583780
Short name T61
Test name
Test status
Simulation time 2474195105 ps
CPU time 3.56 seconds
Started Aug 09 05:12:43 PM PDT 24
Finished Aug 09 05:12:47 PM PDT 24
Peak memory 200744 kb
Host smart-63393d1d-35c0-4b89-8565-74bc4facb35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744583780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.1744583780
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.4217944903
Short name T73
Test name
Test status
Simulation time 2026437726 ps
CPU time 2.88 seconds
Started Aug 09 05:12:48 PM PDT 24
Finished Aug 09 05:12:51 PM PDT 24
Peak memory 200732 kb
Host smart-d201d6f5-4b07-4d6e-aa3c-7bfe707abb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217944903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.4217944903
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.335279018
Short name T785
Test name
Test status
Simulation time 2509543968 ps
CPU time 6.5 seconds
Started Aug 09 05:12:50 PM PDT 24
Finished Aug 09 05:12:56 PM PDT 24
Peak memory 200748 kb
Host smart-86ccb9e3-47ba-4a46-897f-393cc9b481e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335279018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.335279018
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.2689384990
Short name T160
Test name
Test status
Simulation time 2112758458 ps
CPU time 5.85 seconds
Started Aug 09 05:12:43 PM PDT 24
Finished Aug 09 05:12:49 PM PDT 24
Peak memory 200576 kb
Host smart-b8e8c9d6-49e0-47b8-9e03-8085ffb953ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689384990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.2689384990
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.860550402
Short name T601
Test name
Test status
Simulation time 7284442825 ps
CPU time 10.9 seconds
Started Aug 09 05:12:48 PM PDT 24
Finished Aug 09 05:12:59 PM PDT 24
Peak memory 200744 kb
Host smart-2a2c69c8-ceed-403c-8c81-65a30c222a38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860550402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_str
ess_all.860550402
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2011161048
Short name T269
Test name
Test status
Simulation time 77131598076 ps
CPU time 51.86 seconds
Started Aug 09 05:12:50 PM PDT 24
Finished Aug 09 05:13:42 PM PDT 24
Peak memory 201292 kb
Host smart-42bd2246-974c-4aeb-bc78-101c12ee809b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011161048 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.2011161048
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.2152040395
Short name T83
Test name
Test status
Simulation time 5950635486 ps
CPU time 1.2 seconds
Started Aug 09 05:12:49 PM PDT 24
Finished Aug 09 05:12:51 PM PDT 24
Peak memory 200876 kb
Host smart-1a011a47-082a-4cba-8b86-142155ef81a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152040395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.2152040395
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.4144621244
Short name T427
Test name
Test status
Simulation time 2016283164 ps
CPU time 4.49 seconds
Started Aug 09 05:14:13 PM PDT 24
Finished Aug 09 05:14:18 PM PDT 24
Peak memory 200652 kb
Host smart-6e81b5c4-3e19-48d9-a4b6-671ce092a95a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144621244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.4144621244
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.404138300
Short name T44
Test name
Test status
Simulation time 3422009005 ps
CPU time 9.12 seconds
Started Aug 09 05:14:15 PM PDT 24
Finished Aug 09 05:14:24 PM PDT 24
Peak memory 200828 kb
Host smart-a293bc81-9cf6-43df-a96b-c1651181bdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404138300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.404138300
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.2711391482
Short name T96
Test name
Test status
Simulation time 66623743903 ps
CPU time 28.15 seconds
Started Aug 09 05:14:14 PM PDT 24
Finished Aug 09 05:14:42 PM PDT 24
Peak memory 201120 kb
Host smart-255ec2c6-8fd2-472b-bb43-75408b9b2bbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711391482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.2711391482
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.1235526920
Short name T631
Test name
Test status
Simulation time 64081046415 ps
CPU time 105.03 seconds
Started Aug 09 05:14:16 PM PDT 24
Finished Aug 09 05:16:01 PM PDT 24
Peak memory 201164 kb
Host smart-9d2622c7-24d3-4d79-9c40-efa9974f8eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235526920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.1235526920
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.283138038
Short name T301
Test name
Test status
Simulation time 3363508573 ps
CPU time 7.23 seconds
Started Aug 09 05:14:13 PM PDT 24
Finished Aug 09 05:14:21 PM PDT 24
Peak memory 200732 kb
Host smart-a8707d93-45ca-48c6-a12e-46e184fdd019
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283138038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_ec_pwr_on_rst.283138038
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.524542862
Short name T40
Test name
Test status
Simulation time 37902992506 ps
CPU time 42.63 seconds
Started Aug 09 05:14:14 PM PDT 24
Finished Aug 09 05:14:57 PM PDT 24
Peak memory 200876 kb
Host smart-469ea3fc-621f-42bd-9b04-2faca527d2b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524542862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctr
l_edge_detect.524542862
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.952459734
Short name T428
Test name
Test status
Simulation time 2633637999 ps
CPU time 2.38 seconds
Started Aug 09 05:14:14 PM PDT 24
Finished Aug 09 05:14:16 PM PDT 24
Peak memory 200712 kb
Host smart-2f266b21-adf4-4f9f-b8cc-98bcbc54cd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952459734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.952459734
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.3130676248
Short name T422
Test name
Test status
Simulation time 2449729551 ps
CPU time 7.67 seconds
Started Aug 09 05:14:06 PM PDT 24
Finished Aug 09 05:14:14 PM PDT 24
Peak memory 200732 kb
Host smart-ae6c55f6-468d-404d-833e-666421ac2d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130676248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.3130676248
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.678788579
Short name T430
Test name
Test status
Simulation time 2173749039 ps
CPU time 0.96 seconds
Started Aug 09 05:14:17 PM PDT 24
Finished Aug 09 05:14:18 PM PDT 24
Peak memory 200792 kb
Host smart-0325f74b-5518-4556-94be-46bf9558b840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678788579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.678788579
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.2476608383
Short name T151
Test name
Test status
Simulation time 2510689247 ps
CPU time 7.07 seconds
Started Aug 09 05:14:15 PM PDT 24
Finished Aug 09 05:14:22 PM PDT 24
Peak memory 200700 kb
Host smart-859d9c71-e6e3-4e91-9639-5e409bb13058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476608383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.2476608383
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.275006664
Short name T254
Test name
Test status
Simulation time 2128985269 ps
CPU time 1.78 seconds
Started Aug 09 05:14:05 PM PDT 24
Finished Aug 09 05:14:07 PM PDT 24
Peak memory 200712 kb
Host smart-345808ab-0434-4071-b4e3-9a559f52cb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275006664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.275006664
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.2320484210
Short name T341
Test name
Test status
Simulation time 136450633337 ps
CPU time 348.53 seconds
Started Aug 09 05:14:14 PM PDT 24
Finished Aug 09 05:20:02 PM PDT 24
Peak memory 200948 kb
Host smart-c3b4ca6f-b518-4edc-8e1d-bd7e1b0cd143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320484210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.2320484210
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.592240026
Short name T389
Test name
Test status
Simulation time 1398699179198 ps
CPU time 425.98 seconds
Started Aug 09 05:14:13 PM PDT 24
Finished Aug 09 05:21:20 PM PDT 24
Peak memory 209380 kb
Host smart-8ddbb773-2591-4080-9baf-8d4339f39ea0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592240026 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.592240026
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2998509130
Short name T114
Test name
Test status
Simulation time 5840911527 ps
CPU time 7.2 seconds
Started Aug 09 05:14:14 PM PDT 24
Finished Aug 09 05:14:22 PM PDT 24
Peak memory 200764 kb
Host smart-1a5c39ff-2f53-4032-92d1-0a0af8ceaf9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998509130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ultra_low_pwr.2998509130
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.2019219230
Short name T4
Test name
Test status
Simulation time 2011612366 ps
CPU time 5.21 seconds
Started Aug 09 05:14:23 PM PDT 24
Finished Aug 09 05:14:28 PM PDT 24
Peak memory 200760 kb
Host smart-fb1862de-53a8-4a0a-b441-137731902215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019219230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.2019219230
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3798016123
Short name T767
Test name
Test status
Simulation time 312987493758 ps
CPU time 400.2 seconds
Started Aug 09 05:14:26 PM PDT 24
Finished Aug 09 05:21:06 PM PDT 24
Peak memory 200852 kb
Host smart-c4ed6d56-eef6-4c9e-8bcc-0ee577e5b935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798016123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.3
798016123
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.3928890148
Short name T99
Test name
Test status
Simulation time 112677707795 ps
CPU time 139.39 seconds
Started Aug 09 05:14:22 PM PDT 24
Finished Aug 09 05:16:42 PM PDT 24
Peak memory 201048 kb
Host smart-020692b3-dc7a-400c-81fa-e0ca94ea82b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928890148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.3928890148
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.4130794673
Short name T92
Test name
Test status
Simulation time 75981655838 ps
CPU time 42.49 seconds
Started Aug 09 05:14:23 PM PDT 24
Finished Aug 09 05:15:06 PM PDT 24
Peak memory 201076 kb
Host smart-d6d04bc0-d8d6-4f62-b1b7-b6037dbfb90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130794673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.4130794673
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.4179571302
Short name T719
Test name
Test status
Simulation time 3150167624 ps
CPU time 2.57 seconds
Started Aug 09 05:14:15 PM PDT 24
Finished Aug 09 05:14:18 PM PDT 24
Peak memory 200828 kb
Host smart-80bc0137-d031-4d54-a49f-6bf16ad25c61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179571302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.4179571302
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.491862357
Short name T193
Test name
Test status
Simulation time 4268863161 ps
CPU time 7.81 seconds
Started Aug 09 05:14:21 PM PDT 24
Finished Aug 09 05:14:29 PM PDT 24
Peak memory 200728 kb
Host smart-659476f6-7ef3-47a3-bb69-7ac2aeed9892
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491862357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctr
l_edge_detect.491862357
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3284858700
Short name T620
Test name
Test status
Simulation time 2623340152 ps
CPU time 2.2 seconds
Started Aug 09 05:14:16 PM PDT 24
Finished Aug 09 05:14:18 PM PDT 24
Peak memory 200760 kb
Host smart-d4227f41-ebe2-402e-913b-15ae5db3a5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284858700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.3284858700
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.3097311930
Short name T304
Test name
Test status
Simulation time 2493887343 ps
CPU time 2.21 seconds
Started Aug 09 05:14:16 PM PDT 24
Finished Aug 09 05:14:18 PM PDT 24
Peak memory 200828 kb
Host smart-b0643886-1432-4f4c-99ae-6c45d43f813f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097311930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.3097311930
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.1943753451
Short name T16
Test name
Test status
Simulation time 2105650352 ps
CPU time 2.02 seconds
Started Aug 09 05:14:20 PM PDT 24
Finished Aug 09 05:14:22 PM PDT 24
Peak memory 200748 kb
Host smart-daca5821-1e7a-40ca-bf50-763e3b90d949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943753451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.1943753451
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.2379767043
Short name T309
Test name
Test status
Simulation time 2537990168 ps
CPU time 2.59 seconds
Started Aug 09 05:14:15 PM PDT 24
Finished Aug 09 05:14:17 PM PDT 24
Peak memory 200764 kb
Host smart-aea8b165-8873-439d-86b6-4b250b7929a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379767043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.2379767043
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.3242723009
Short name T124
Test name
Test status
Simulation time 2124410657 ps
CPU time 1.83 seconds
Started Aug 09 05:14:13 PM PDT 24
Finished Aug 09 05:14:15 PM PDT 24
Peak memory 200672 kb
Host smart-f346fdd3-e276-4b95-a484-38b0adb98bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242723009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.3242723009
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.1135044539
Short name T576
Test name
Test status
Simulation time 7609155954 ps
CPU time 9.84 seconds
Started Aug 09 05:14:26 PM PDT 24
Finished Aug 09 05:14:36 PM PDT 24
Peak memory 200760 kb
Host smart-46a1917d-2250-4940-a6b3-210ae7e35ce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135044539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.1135044539
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.1666464339
Short name T625
Test name
Test status
Simulation time 257127670243 ps
CPU time 17.54 seconds
Started Aug 09 05:14:21 PM PDT 24
Finished Aug 09 05:14:39 PM PDT 24
Peak memory 200908 kb
Host smart-49d05e80-ee3a-4e1a-99aa-a49635abd1cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666464339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.1666464339
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.406404640
Short name T703
Test name
Test status
Simulation time 2021884977 ps
CPU time 2.94 seconds
Started Aug 09 05:14:25 PM PDT 24
Finished Aug 09 05:14:28 PM PDT 24
Peak memory 200768 kb
Host smart-99747d68-16e4-47f3-9c1d-adf302142d7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406404640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_tes
t.406404640
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2561174418
Short name T294
Test name
Test status
Simulation time 3260382098 ps
CPU time 2.72 seconds
Started Aug 09 05:14:24 PM PDT 24
Finished Aug 09 05:14:27 PM PDT 24
Peak memory 200716 kb
Host smart-937c0562-71c6-4cfc-be8b-1fa3b36968d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561174418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.2
561174418
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.3803869060
Short name T581
Test name
Test status
Simulation time 159341062446 ps
CPU time 99.32 seconds
Started Aug 09 05:14:23 PM PDT 24
Finished Aug 09 05:16:02 PM PDT 24
Peak memory 200968 kb
Host smart-118f5e56-23d2-4cb2-9b29-31e39336535f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803869060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.3803869060
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.3490873444
Short name T268
Test name
Test status
Simulation time 48369872045 ps
CPU time 116.89 seconds
Started Aug 09 05:14:23 PM PDT 24
Finished Aug 09 05:16:20 PM PDT 24
Peak memory 201032 kb
Host smart-a7bb2919-5aba-4e25-a5a0-717e6d4d87f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490873444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_w
ith_pre_cond.3490873444
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.3135681781
Short name T51
Test name
Test status
Simulation time 3456019265 ps
CPU time 3.37 seconds
Started Aug 09 05:14:23 PM PDT 24
Finished Aug 09 05:14:27 PM PDT 24
Peak memory 200744 kb
Host smart-e6092511-63e5-45c0-aadf-e44951170529
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135681781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.3135681781
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.4020603490
Short name T641
Test name
Test status
Simulation time 2471444051 ps
CPU time 2.13 seconds
Started Aug 09 05:14:25 PM PDT 24
Finished Aug 09 05:14:28 PM PDT 24
Peak memory 200796 kb
Host smart-88cec6a2-bf49-44d3-aeba-243cdd2c97f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020603490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.4020603490
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.4013008932
Short name T472
Test name
Test status
Simulation time 2607422680 ps
CPU time 7.53 seconds
Started Aug 09 05:14:23 PM PDT 24
Finished Aug 09 05:14:30 PM PDT 24
Peak memory 200736 kb
Host smart-153fbf64-e74c-4e5e-9854-7af31b961da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013008932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.4013008932
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.1248389980
Short name T698
Test name
Test status
Simulation time 2504423388 ps
CPU time 1.55 seconds
Started Aug 09 05:14:22 PM PDT 24
Finished Aug 09 05:14:24 PM PDT 24
Peak memory 200736 kb
Host smart-3c60ce55-0923-49b3-9639-601539446895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248389980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.1248389980
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.341434189
Short name T624
Test name
Test status
Simulation time 2251809107 ps
CPU time 3.54 seconds
Started Aug 09 05:14:25 PM PDT 24
Finished Aug 09 05:14:28 PM PDT 24
Peak memory 200716 kb
Host smart-baf0c962-eefb-4eb4-b47c-f5b42438094f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341434189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.341434189
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.1045662561
Short name T525
Test name
Test status
Simulation time 2530559534 ps
CPU time 2.52 seconds
Started Aug 09 05:14:23 PM PDT 24
Finished Aug 09 05:14:26 PM PDT 24
Peak memory 200800 kb
Host smart-cf30106a-3987-4853-a4ca-51be89028064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045662561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.1045662561
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.1384822470
Short name T688
Test name
Test status
Simulation time 2127764882 ps
CPU time 2.02 seconds
Started Aug 09 05:14:23 PM PDT 24
Finished Aug 09 05:14:25 PM PDT 24
Peak memory 200736 kb
Host smart-c285a547-1329-440a-90ac-749e3f5d444f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384822470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.1384822470
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.1398426572
Short name T131
Test name
Test status
Simulation time 11581108120 ps
CPU time 18.52 seconds
Started Aug 09 05:14:23 PM PDT 24
Finished Aug 09 05:14:42 PM PDT 24
Peak memory 200892 kb
Host smart-1341494e-235e-4f66-9053-01e1f444d1b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398426572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s
tress_all.1398426572
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3889132466
Short name T241
Test name
Test status
Simulation time 151577157044 ps
CPU time 88.64 seconds
Started Aug 09 05:14:22 PM PDT 24
Finished Aug 09 05:15:51 PM PDT 24
Peak memory 209424 kb
Host smart-352a81a2-7e16-4e4f-829f-e810cb16e058
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889132466 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.3889132466
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.2519608770
Short name T81
Test name
Test status
Simulation time 3878435585 ps
CPU time 2.08 seconds
Started Aug 09 05:14:23 PM PDT 24
Finished Aug 09 05:14:25 PM PDT 24
Peak memory 200868 kb
Host smart-e322142a-8817-4309-908b-f9a4c3aff0fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519608770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.2519608770
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.2371121036
Short name T554
Test name
Test status
Simulation time 2012104872 ps
CPU time 5.5 seconds
Started Aug 09 05:14:23 PM PDT 24
Finished Aug 09 05:14:29 PM PDT 24
Peak memory 200832 kb
Host smart-30402a29-7139-43e6-bdc0-59b5a8de73e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371121036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.2371121036
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.1397404781
Short name T666
Test name
Test status
Simulation time 3123423626 ps
CPU time 2.59 seconds
Started Aug 09 05:14:25 PM PDT 24
Finished Aug 09 05:14:27 PM PDT 24
Peak memory 201120 kb
Host smart-9d7c261f-1e18-4c6d-8fc6-3838fd1bd392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397404781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.1
397404781
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.3804086466
Short name T535
Test name
Test status
Simulation time 136877441691 ps
CPU time 360.37 seconds
Started Aug 09 05:14:23 PM PDT 24
Finished Aug 09 05:20:23 PM PDT 24
Peak memory 200964 kb
Host smart-3524f18b-2d8d-4e40-b3c7-09d64c2d8062
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804086466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.3804086466
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.4249123466
Short name T456
Test name
Test status
Simulation time 4233016003 ps
CPU time 2.77 seconds
Started Aug 09 05:14:22 PM PDT 24
Finished Aug 09 05:14:25 PM PDT 24
Peak memory 200736 kb
Host smart-25e5e28b-eb92-4da3-9a77-3e5b6a74cab7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249123466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.4249123466
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.3265310868
Short name T737
Test name
Test status
Simulation time 2757735652 ps
CPU time 2.32 seconds
Started Aug 09 05:14:25 PM PDT 24
Finished Aug 09 05:14:28 PM PDT 24
Peak memory 200796 kb
Host smart-5f3ebb7c-b93e-496f-bd3f-d6f0e564abc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265310868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.3265310868
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3408271684
Short name T537
Test name
Test status
Simulation time 2613015660 ps
CPU time 7.24 seconds
Started Aug 09 05:14:25 PM PDT 24
Finished Aug 09 05:14:33 PM PDT 24
Peak memory 200764 kb
Host smart-8c2b7f6b-bc3b-4eef-800a-d7ab32587a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408271684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.3408271684
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.1154592929
Short name T776
Test name
Test status
Simulation time 2473815064 ps
CPU time 2.3 seconds
Started Aug 09 05:14:26 PM PDT 24
Finished Aug 09 05:14:28 PM PDT 24
Peak memory 200752 kb
Host smart-e6f49235-61f3-4852-bded-ae493760a002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154592929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.1154592929
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.799362417
Short name T150
Test name
Test status
Simulation time 2206669891 ps
CPU time 4.74 seconds
Started Aug 09 05:14:22 PM PDT 24
Finished Aug 09 05:14:27 PM PDT 24
Peak memory 200700 kb
Host smart-b6b71ac1-dc7d-4bf4-90fd-efa04a6a98b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799362417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.799362417
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.4181301219
Short name T239
Test name
Test status
Simulation time 2523212369 ps
CPU time 3.92 seconds
Started Aug 09 05:14:23 PM PDT 24
Finished Aug 09 05:14:27 PM PDT 24
Peak memory 200732 kb
Host smart-8c98e1dd-27c0-4389-bdf1-33e4bba80c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181301219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.4181301219
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.783045586
Short name T574
Test name
Test status
Simulation time 2113064535 ps
CPU time 6.07 seconds
Started Aug 09 05:14:22 PM PDT 24
Finished Aug 09 05:14:28 PM PDT 24
Peak memory 200656 kb
Host smart-c00a1e16-344b-449e-adfd-0a2ec5ceebc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783045586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.783045586
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.3138345579
Short name T52
Test name
Test status
Simulation time 4942533931 ps
CPU time 6.64 seconds
Started Aug 09 05:14:26 PM PDT 24
Finished Aug 09 05:14:33 PM PDT 24
Peak memory 200864 kb
Host smart-8c07ad69-908b-4c10-af9c-3a614b59fd62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138345579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ultra_low_pwr.3138345579
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.649646564
Short name T578
Test name
Test status
Simulation time 2012141743 ps
CPU time 5.54 seconds
Started Aug 09 05:14:33 PM PDT 24
Finished Aug 09 05:14:39 PM PDT 24
Peak memory 200732 kb
Host smart-f3b9aa0c-a071-4321-9ce5-18a4a73a905a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649646564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_tes
t.649646564
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2850104640
Short name T494
Test name
Test status
Simulation time 3247295436 ps
CPU time 2.02 seconds
Started Aug 09 05:14:25 PM PDT 24
Finished Aug 09 05:14:28 PM PDT 24
Peak memory 200796 kb
Host smart-fa5878ac-755f-4029-8af5-a80f5252f36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850104640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.2
850104640
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.2329805214
Short name T373
Test name
Test status
Simulation time 157758142444 ps
CPU time 364.91 seconds
Started Aug 09 05:14:25 PM PDT 24
Finished Aug 09 05:20:30 PM PDT 24
Peak memory 201308 kb
Host smart-23a8b1d7-33f3-4016-8415-456de4294a78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329805214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.2329805214
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.1950121976
Short name T257
Test name
Test status
Simulation time 42891433398 ps
CPU time 117.08 seconds
Started Aug 09 05:14:24 PM PDT 24
Finished Aug 09 05:16:22 PM PDT 24
Peak memory 200948 kb
Host smart-d6cd23b4-3569-465a-92df-1d6a48270f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950121976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.1950121976
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.3245821789
Short name T695
Test name
Test status
Simulation time 3739029208 ps
CPU time 2.84 seconds
Started Aug 09 05:14:24 PM PDT 24
Finished Aug 09 05:14:27 PM PDT 24
Peak memory 200760 kb
Host smart-1ce9f843-c721-4c10-8740-3a9bd9d0f1f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245821789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ec_pwr_on_rst.3245821789
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.3586688801
Short name T161
Test name
Test status
Simulation time 3939013458 ps
CPU time 2.51 seconds
Started Aug 09 05:14:24 PM PDT 24
Finished Aug 09 05:14:26 PM PDT 24
Peak memory 200812 kb
Host smart-c359aaed-ae6f-44c6-ab67-2310bbbea352
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586688801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.3586688801
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1378158765
Short name T311
Test name
Test status
Simulation time 2617609890 ps
CPU time 4.03 seconds
Started Aug 09 05:14:25 PM PDT 24
Finished Aug 09 05:14:29 PM PDT 24
Peak memory 200744 kb
Host smart-14b29da1-c47b-414a-9f54-940f38f5d5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378158765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.1378158765
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.2459187879
Short name T87
Test name
Test status
Simulation time 2475871874 ps
CPU time 2.51 seconds
Started Aug 09 05:14:25 PM PDT 24
Finished Aug 09 05:14:27 PM PDT 24
Peak memory 200636 kb
Host smart-e601fb90-77ed-41eb-a42c-521f6c9e87eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459187879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.2459187879
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.130767578
Short name T774
Test name
Test status
Simulation time 2213946842 ps
CPU time 3.43 seconds
Started Aug 09 05:14:26 PM PDT 24
Finished Aug 09 05:14:29 PM PDT 24
Peak memory 200780 kb
Host smart-09dabc62-dc79-4188-a19a-ea77e1b9422c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130767578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.130767578
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.3139775643
Short name T781
Test name
Test status
Simulation time 2530464845 ps
CPU time 2.16 seconds
Started Aug 09 05:14:23 PM PDT 24
Finished Aug 09 05:14:26 PM PDT 24
Peak memory 200800 kb
Host smart-2c9373ba-e873-45bf-8344-d34e1a66097f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139775643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.3139775643
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.4066218992
Short name T768
Test name
Test status
Simulation time 2115282576 ps
CPU time 3.16 seconds
Started Aug 09 05:14:24 PM PDT 24
Finished Aug 09 05:14:27 PM PDT 24
Peak memory 200644 kb
Host smart-21c05104-572e-4403-9831-141536d45eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066218992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.4066218992
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.1988131666
Short name T479
Test name
Test status
Simulation time 109141342837 ps
CPU time 32.29 seconds
Started Aug 09 05:14:37 PM PDT 24
Finished Aug 09 05:15:09 PM PDT 24
Peak memory 200972 kb
Host smart-e8f47427-db6d-422f-8edd-db0e252ea9b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988131666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.1988131666
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2882912549
Short name T563
Test name
Test status
Simulation time 16113648408 ps
CPU time 43.12 seconds
Started Aug 09 05:14:23 PM PDT 24
Finished Aug 09 05:15:06 PM PDT 24
Peak memory 201168 kb
Host smart-488146d6-5167-4f9c-bf7d-92a0a2cf7c00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882912549 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.2882912549
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2571790871
Short name T559
Test name
Test status
Simulation time 2845618583 ps
CPU time 1.99 seconds
Started Aug 09 05:14:25 PM PDT 24
Finished Aug 09 05:14:27 PM PDT 24
Peak memory 200800 kb
Host smart-c7fdef04-ddcd-4425-938a-8cf851701d1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571790871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ultra_low_pwr.2571790871
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.2596233525
Short name T636
Test name
Test status
Simulation time 2019668572 ps
CPU time 3.38 seconds
Started Aug 09 05:14:32 PM PDT 24
Finished Aug 09 05:14:35 PM PDT 24
Peak memory 200804 kb
Host smart-16f8a2e1-2a42-4fd3-8d52-4ee141ca5f22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596233525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.2596233525
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.3791220435
Short name T750
Test name
Test status
Simulation time 3138693190 ps
CPU time 6.94 seconds
Started Aug 09 05:14:35 PM PDT 24
Finished Aug 09 05:14:42 PM PDT 24
Peak memory 200856 kb
Host smart-0e3b407d-dcba-43c6-9b2d-f5c5234359ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791220435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.3
791220435
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.4206475111
Short name T560
Test name
Test status
Simulation time 3182455451 ps
CPU time 4.58 seconds
Started Aug 09 05:14:37 PM PDT 24
Finished Aug 09 05:14:41 PM PDT 24
Peak memory 200736 kb
Host smart-fa1ec7a7-c97b-452b-932e-5e2ad38984b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206475111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ec_pwr_on_rst.4206475111
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.4180877603
Short name T174
Test name
Test status
Simulation time 4073381905 ps
CPU time 11.86 seconds
Started Aug 09 05:14:32 PM PDT 24
Finished Aug 09 05:14:44 PM PDT 24
Peak memory 200796 kb
Host smart-988fa8f9-87ea-4959-832e-843d0671dbdc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180877603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.4180877603
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.3027972311
Short name T482
Test name
Test status
Simulation time 2618293074 ps
CPU time 3.87 seconds
Started Aug 09 05:14:32 PM PDT 24
Finished Aug 09 05:14:36 PM PDT 24
Peak memory 200764 kb
Host smart-dae92e7d-5ccc-4f05-a86f-82983b4034eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027972311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.3027972311
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.2735100506
Short name T403
Test name
Test status
Simulation time 2489186894 ps
CPU time 3.78 seconds
Started Aug 09 05:14:35 PM PDT 24
Finished Aug 09 05:14:38 PM PDT 24
Peak memory 200712 kb
Host smart-9d0fbabb-6c3c-433d-8d9d-35fdef20cfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735100506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.2735100506
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.1064857343
Short name T726
Test name
Test status
Simulation time 2220257467 ps
CPU time 5.95 seconds
Started Aug 09 05:14:36 PM PDT 24
Finished Aug 09 05:14:42 PM PDT 24
Peak memory 200716 kb
Host smart-e0bffe5d-a9e9-4e24-939a-d48f910f1d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064857343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.1064857343
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.3403433383
Short name T487
Test name
Test status
Simulation time 2511386132 ps
CPU time 6.65 seconds
Started Aug 09 05:14:35 PM PDT 24
Finished Aug 09 05:14:42 PM PDT 24
Peak memory 200816 kb
Host smart-7261c866-73f4-4715-a34a-3011658ed18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403433383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.3403433383
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.1659817273
Short name T249
Test name
Test status
Simulation time 2114210804 ps
CPU time 3.23 seconds
Started Aug 09 05:14:32 PM PDT 24
Finished Aug 09 05:14:36 PM PDT 24
Peak memory 200800 kb
Host smart-0be009cd-57a2-45d9-9ecb-07fa996f1834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659817273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.1659817273
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.782515692
Short name T668
Test name
Test status
Simulation time 230579746092 ps
CPU time 99.52 seconds
Started Aug 09 05:14:34 PM PDT 24
Finished Aug 09 05:16:13 PM PDT 24
Peak memory 200820 kb
Host smart-55dc769a-dc47-437c-9834-afdaafa11891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782515692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_st
ress_all.782515692
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1623031678
Short name T122
Test name
Test status
Simulation time 63266139690 ps
CPU time 12.18 seconds
Started Aug 09 05:14:36 PM PDT 24
Finished Aug 09 05:14:48 PM PDT 24
Peak memory 209340 kb
Host smart-6fbbc9e0-8a5b-496f-bb74-63654ef26e2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623031678 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.1623031678
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.2659924501
Short name T516
Test name
Test status
Simulation time 6693798694 ps
CPU time 3.14 seconds
Started Aug 09 05:14:32 PM PDT 24
Finished Aug 09 05:14:35 PM PDT 24
Peak memory 200908 kb
Host smart-1016f831-bfa8-4928-97e1-fc40f776ad54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659924501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.2659924501
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.2121186169
Short name T518
Test name
Test status
Simulation time 2032254952 ps
CPU time 1.72 seconds
Started Aug 09 05:14:36 PM PDT 24
Finished Aug 09 05:14:37 PM PDT 24
Peak memory 200672 kb
Host smart-009cbaf3-d8b3-4059-bdce-7aca1cf50fd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121186169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.2121186169
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.2291170744
Short name T425
Test name
Test status
Simulation time 197814644499 ps
CPU time 527.3 seconds
Started Aug 09 05:14:37 PM PDT 24
Finished Aug 09 05:23:25 PM PDT 24
Peak memory 200768 kb
Host smart-53dfaf80-a3b2-49df-9c1e-0eff00ca1c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291170744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.2
291170744
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.301742414
Short name T163
Test name
Test status
Simulation time 110731909981 ps
CPU time 74.3 seconds
Started Aug 09 05:14:33 PM PDT 24
Finished Aug 09 05:15:47 PM PDT 24
Peak memory 201372 kb
Host smart-3edc74bf-0fdf-4e05-b36a-7f42f2e3d790
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301742414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_combo_detect.301742414
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.3983688779
Short name T777
Test name
Test status
Simulation time 2922454891 ps
CPU time 3.87 seconds
Started Aug 09 05:14:33 PM PDT 24
Finished Aug 09 05:14:37 PM PDT 24
Peak memory 200724 kb
Host smart-be9d92bb-c553-44c8-a3f2-56c49d19327c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983688779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ec_pwr_on_rst.3983688779
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.1378108846
Short name T146
Test name
Test status
Simulation time 2899412925 ps
CPU time 6.6 seconds
Started Aug 09 05:14:32 PM PDT 24
Finished Aug 09 05:14:39 PM PDT 24
Peak memory 200796 kb
Host smart-5926857c-ba87-435e-a5bf-ca9784f164f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378108846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.1378108846
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.871564907
Short name T730
Test name
Test status
Simulation time 2611715711 ps
CPU time 7.14 seconds
Started Aug 09 05:14:35 PM PDT 24
Finished Aug 09 05:14:42 PM PDT 24
Peak memory 200724 kb
Host smart-ebc4ad8c-5c69-46e0-9992-f340cb2cee03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871564907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.871564907
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.2146750814
Short name T543
Test name
Test status
Simulation time 2494187270 ps
CPU time 2.11 seconds
Started Aug 09 05:14:33 PM PDT 24
Finished Aug 09 05:14:35 PM PDT 24
Peak memory 200820 kb
Host smart-d8f950b4-0e9d-4989-925f-bd69b95c34cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146750814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.2146750814
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.2522557379
Short name T702
Test name
Test status
Simulation time 2159105143 ps
CPU time 4.74 seconds
Started Aug 09 05:14:36 PM PDT 24
Finished Aug 09 05:14:41 PM PDT 24
Peak memory 200736 kb
Host smart-aca819db-3836-4d61-aa3e-8a67cad72497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522557379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.2522557379
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.2974198733
Short name T573
Test name
Test status
Simulation time 2510259124 ps
CPU time 7.4 seconds
Started Aug 09 05:14:32 PM PDT 24
Finished Aug 09 05:14:40 PM PDT 24
Peak memory 200780 kb
Host smart-6e92b724-546a-4160-89ea-e3dfa526ee89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974198733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.2974198733
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.1832512089
Short name T312
Test name
Test status
Simulation time 2118983553 ps
CPU time 3.13 seconds
Started Aug 09 05:14:33 PM PDT 24
Finished Aug 09 05:14:37 PM PDT 24
Peak memory 200668 kb
Host smart-cf784031-49ae-4c12-b15b-81e0f56160f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832512089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.1832512089
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.2602614725
Short name T5
Test name
Test status
Simulation time 10444166389 ps
CPU time 4.77 seconds
Started Aug 09 05:14:35 PM PDT 24
Finished Aug 09 05:14:40 PM PDT 24
Peak memory 200876 kb
Host smart-0a309db9-a8bf-4f62-9d05-bd9bf8522c2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602614725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.2602614725
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.4055726051
Short name T112
Test name
Test status
Simulation time 11572030184 ps
CPU time 2.64 seconds
Started Aug 09 05:14:33 PM PDT 24
Finished Aug 09 05:14:36 PM PDT 24
Peak memory 200852 kb
Host smart-fc3b0401-f225-48c7-9714-ae74ea7a5106
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055726051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ultra_low_pwr.4055726051
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.1581864504
Short name T424
Test name
Test status
Simulation time 2048140363 ps
CPU time 1.75 seconds
Started Aug 09 05:14:33 PM PDT 24
Finished Aug 09 05:14:35 PM PDT 24
Peak memory 200748 kb
Host smart-34ed574c-aad1-4523-be89-7108b94da3ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581864504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.1581864504
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.1308845203
Short name T492
Test name
Test status
Simulation time 3119608044 ps
CPU time 3.76 seconds
Started Aug 09 05:14:33 PM PDT 24
Finished Aug 09 05:14:36 PM PDT 24
Peak memory 200936 kb
Host smart-ad8dab2f-9ecf-4a81-a4a6-aa0a81bcf366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308845203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.1
308845203
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.1431194733
Short name T724
Test name
Test status
Simulation time 104814592633 ps
CPU time 144.72 seconds
Started Aug 09 05:14:37 PM PDT 24
Finished Aug 09 05:17:02 PM PDT 24
Peak memory 201004 kb
Host smart-bb252c40-0fa4-4c1d-b6cb-8a38ce585f6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431194733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.1431194733
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.2582470766
Short name T107
Test name
Test status
Simulation time 2558993264 ps
CPU time 3.8 seconds
Started Aug 09 05:14:33 PM PDT 24
Finished Aug 09 05:14:37 PM PDT 24
Peak memory 200800 kb
Host smart-3da84b43-f31f-4e77-94a3-633e092074a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582470766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.2582470766
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.758956225
Short name T740
Test name
Test status
Simulation time 2635378226 ps
CPU time 2.27 seconds
Started Aug 09 05:14:36 PM PDT 24
Finished Aug 09 05:14:39 PM PDT 24
Peak memory 200688 kb
Host smart-f93cba72-f83d-42c1-8c01-5886eaeea0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758956225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.758956225
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2076863750
Short name T392
Test name
Test status
Simulation time 2480343633 ps
CPU time 7.04 seconds
Started Aug 09 05:14:33 PM PDT 24
Finished Aug 09 05:14:41 PM PDT 24
Peak memory 200744 kb
Host smart-a7b2fc3c-72b6-4810-ac70-502656490fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076863750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.2076863750
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.3148075898
Short name T568
Test name
Test status
Simulation time 2075871367 ps
CPU time 6.12 seconds
Started Aug 09 05:14:34 PM PDT 24
Finished Aug 09 05:14:40 PM PDT 24
Peak memory 200676 kb
Host smart-18115a7c-40f4-450b-a467-ee68ab92f075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148075898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.3148075898
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.3529287236
Short name T167
Test name
Test status
Simulation time 2554763533 ps
CPU time 1.88 seconds
Started Aug 09 05:14:35 PM PDT 24
Finished Aug 09 05:14:37 PM PDT 24
Peak memory 200724 kb
Host smart-65823f59-687f-4a84-99da-860a6b9245c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529287236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.3529287236
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.1383017405
Short name T622
Test name
Test status
Simulation time 2130948642 ps
CPU time 1.93 seconds
Started Aug 09 05:14:36 PM PDT 24
Finished Aug 09 05:14:38 PM PDT 24
Peak memory 200708 kb
Host smart-2d4aaddf-c3b0-4e67-8677-cea9da216e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383017405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.1383017405
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.186830967
Short name T6
Test name
Test status
Simulation time 14732388207 ps
CPU time 30.13 seconds
Started Aug 09 05:14:34 PM PDT 24
Finished Aug 09 05:15:04 PM PDT 24
Peak memory 200868 kb
Host smart-c8b478ae-088f-44c9-bb50-073fc09c99c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186830967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_st
ress_all.186830967
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2539206878
Short name T386
Test name
Test status
Simulation time 25087864952 ps
CPU time 64.81 seconds
Started Aug 09 05:14:33 PM PDT 24
Finished Aug 09 05:15:38 PM PDT 24
Peak memory 209384 kb
Host smart-51c4a2d5-bc57-486d-826a-0e4dd246cfc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539206878 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.2539206878
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.773696993
Short name T498
Test name
Test status
Simulation time 3131021473 ps
CPU time 0.93 seconds
Started Aug 09 05:14:34 PM PDT 24
Finished Aug 09 05:14:35 PM PDT 24
Peak memory 201144 kb
Host smart-125d858b-2c8e-402d-b7a4-a4c9562b6438
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773696993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_ultra_low_pwr.773696993
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.952089323
Short name T732
Test name
Test status
Simulation time 2015899365 ps
CPU time 3.02 seconds
Started Aug 09 05:14:46 PM PDT 24
Finished Aug 09 05:14:50 PM PDT 24
Peak memory 200792 kb
Host smart-2ef33505-7970-4afe-b33d-68ea9fc391e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952089323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_tes
t.952089323
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.1538008860
Short name T729
Test name
Test status
Simulation time 3808728884 ps
CPU time 4.6 seconds
Started Aug 09 05:14:43 PM PDT 24
Finished Aug 09 05:14:47 PM PDT 24
Peak memory 200784 kb
Host smart-8e648fcb-a080-4bdc-aa5d-c1686bc3af2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538008860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.1
538008860
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.2047946485
Short name T374
Test name
Test status
Simulation time 163662543804 ps
CPU time 53.41 seconds
Started Aug 09 05:14:51 PM PDT 24
Finished Aug 09 05:15:45 PM PDT 24
Peak memory 200928 kb
Host smart-f8173154-6cf2-4b2b-9960-2b4ff7244aeb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047946485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.2047946485
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3044302136
Short name T66
Test name
Test status
Simulation time 37370922332 ps
CPU time 23.31 seconds
Started Aug 09 05:14:45 PM PDT 24
Finished Aug 09 05:15:08 PM PDT 24
Peak memory 201032 kb
Host smart-294faaa0-8d33-4dbc-b872-f182bdb0ba87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044302136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.3044302136
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.1395355648
Short name T205
Test name
Test status
Simulation time 3473082749 ps
CPU time 9.16 seconds
Started Aug 09 05:14:45 PM PDT 24
Finished Aug 09 05:14:55 PM PDT 24
Peak memory 200808 kb
Host smart-049f6d56-d2b6-40c2-ae5c-680d842cb775
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395355648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ec_pwr_on_rst.1395355648
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.2519489270
Short name T199
Test name
Test status
Simulation time 400138663584 ps
CPU time 634.23 seconds
Started Aug 09 05:14:51 PM PDT 24
Finished Aug 09 05:25:26 PM PDT 24
Peak memory 200764 kb
Host smart-76b36d0d-cf58-424a-9044-e0ade0ed9d84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519489270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_edge_detect.2519489270
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1192106005
Short name T156
Test name
Test status
Simulation time 2611264428 ps
CPU time 7.28 seconds
Started Aug 09 05:14:43 PM PDT 24
Finished Aug 09 05:14:51 PM PDT 24
Peak memory 200764 kb
Host smart-c6113db2-ae8c-490a-be8c-945a9649ce36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192106005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.1192106005
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1174624122
Short name T566
Test name
Test status
Simulation time 2486153515 ps
CPU time 2.38 seconds
Started Aug 09 05:14:42 PM PDT 24
Finished Aug 09 05:14:44 PM PDT 24
Peak memory 200796 kb
Host smart-4b16afb6-3603-4e7e-a58e-259a6b5fbb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174624122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.1174624122
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.627965457
Short name T533
Test name
Test status
Simulation time 2103847906 ps
CPU time 6.15 seconds
Started Aug 09 05:14:42 PM PDT 24
Finished Aug 09 05:14:48 PM PDT 24
Peak memory 200984 kb
Host smart-f46239a8-4139-472d-b963-a4f71c80eca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627965457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.627965457
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.1018391787
Short name T655
Test name
Test status
Simulation time 2521390829 ps
CPU time 2.44 seconds
Started Aug 09 05:14:46 PM PDT 24
Finished Aug 09 05:14:48 PM PDT 24
Peak memory 200736 kb
Host smart-607497d2-9f23-41a8-8e53-86e4c35e6578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018391787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.1018391787
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.1495560375
Short name T587
Test name
Test status
Simulation time 2167207672 ps
CPU time 1.14 seconds
Started Aug 09 05:14:37 PM PDT 24
Finished Aug 09 05:14:38 PM PDT 24
Peak memory 200684 kb
Host smart-a9443573-8948-4d9e-b139-630905bfbbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495560375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.1495560375
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.2056475425
Short name T145
Test name
Test status
Simulation time 13023623729 ps
CPU time 32.63 seconds
Started Aug 09 05:14:51 PM PDT 24
Finished Aug 09 05:15:24 PM PDT 24
Peak memory 200752 kb
Host smart-75d201ee-46d8-4ea6-ba54-6ad238f2f2f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056475425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_s
tress_all.2056475425
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.1078659647
Short name T101
Test name
Test status
Simulation time 52549085422 ps
CPU time 34.01 seconds
Started Aug 09 05:14:46 PM PDT 24
Finished Aug 09 05:15:20 PM PDT 24
Peak memory 217492 kb
Host smart-4d101d41-5e74-4a52-9512-6fa3a9d9b516
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078659647 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.1078659647
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.2522547345
Short name T437
Test name
Test status
Simulation time 3387295901 ps
CPU time 1.49 seconds
Started Aug 09 05:14:43 PM PDT 24
Finished Aug 09 05:14:44 PM PDT 24
Peak memory 200812 kb
Host smart-44b08a15-b5ac-485c-97e7-b2f3deaee33c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522547345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ultra_low_pwr.2522547345
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.3209562705
Short name T789
Test name
Test status
Simulation time 2012836987 ps
CPU time 5.73 seconds
Started Aug 09 05:14:44 PM PDT 24
Finished Aug 09 05:14:50 PM PDT 24
Peak memory 200764 kb
Host smart-cc3a0987-8257-4d95-88ff-7a76dac745ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209562705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.3209562705
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.3291030818
Short name T775
Test name
Test status
Simulation time 3621142421 ps
CPU time 10.36 seconds
Started Aug 09 05:14:50 PM PDT 24
Finished Aug 09 05:15:00 PM PDT 24
Peak memory 200840 kb
Host smart-2160459e-c6a5-4755-94d8-e7d75ae533ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291030818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.3
291030818
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.1051610168
Short name T159
Test name
Test status
Simulation time 61192846562 ps
CPU time 78.38 seconds
Started Aug 09 05:14:50 PM PDT 24
Finished Aug 09 05:16:09 PM PDT 24
Peak memory 200996 kb
Host smart-0afc6809-154a-41b7-aeb7-1d7f289e6e1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051610168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.1051610168
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1855774024
Short name T755
Test name
Test status
Simulation time 26580584271 ps
CPU time 66.77 seconds
Started Aug 09 05:14:50 PM PDT 24
Finished Aug 09 05:15:57 PM PDT 24
Peak memory 201140 kb
Host smart-743d9266-0b36-42be-ae46-be85699ecc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855774024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.1855774024
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3371142925
Short name T180
Test name
Test status
Simulation time 3332740433 ps
CPU time 8.58 seconds
Started Aug 09 05:14:45 PM PDT 24
Finished Aug 09 05:14:54 PM PDT 24
Peak memory 200740 kb
Host smart-a85ab8d1-a4d0-4c1c-b2c7-17d58c1b9ba4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371142925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.3371142925
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.891140288
Short name T204
Test name
Test status
Simulation time 2738325699 ps
CPU time 1.51 seconds
Started Aug 09 05:14:46 PM PDT 24
Finished Aug 09 05:14:48 PM PDT 24
Peak memory 200800 kb
Host smart-e4754175-0678-474d-ad72-7e4140e412ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891140288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctr
l_edge_detect.891140288
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1694808109
Short name T527
Test name
Test status
Simulation time 2613617045 ps
CPU time 7.49 seconds
Started Aug 09 05:14:45 PM PDT 24
Finished Aug 09 05:14:53 PM PDT 24
Peak memory 200736 kb
Host smart-5680b3e8-ff81-4833-b03f-45f85841e8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694808109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.1694808109
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.232120630
Short name T451
Test name
Test status
Simulation time 2443729716 ps
CPU time 7.19 seconds
Started Aug 09 05:14:46 PM PDT 24
Finished Aug 09 05:14:53 PM PDT 24
Peak memory 200764 kb
Host smart-1028bf82-fa27-4e39-9d73-d167b91cf5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232120630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.232120630
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.1231811950
Short name T680
Test name
Test status
Simulation time 2019144990 ps
CPU time 5.52 seconds
Started Aug 09 05:14:46 PM PDT 24
Finished Aug 09 05:14:51 PM PDT 24
Peak memory 200660 kb
Host smart-447a2fbb-3030-452e-9862-91997a5b2903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231811950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.1231811950
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.804527157
Short name T228
Test name
Test status
Simulation time 2513248141 ps
CPU time 3.71 seconds
Started Aug 09 05:14:46 PM PDT 24
Finished Aug 09 05:14:50 PM PDT 24
Peak memory 201088 kb
Host smart-86e2249c-108f-4b93-9540-6fd18670d5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804527157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.804527157
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.1093190312
Short name T687
Test name
Test status
Simulation time 2111079298 ps
CPU time 5.63 seconds
Started Aug 09 05:14:45 PM PDT 24
Finished Aug 09 05:14:51 PM PDT 24
Peak memory 200656 kb
Host smart-e354af12-0fed-4041-afc3-dd186d76816a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093190312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.1093190312
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.2434656460
Short name T222
Test name
Test status
Simulation time 11464036896 ps
CPU time 14.44 seconds
Started Aug 09 05:14:46 PM PDT 24
Finished Aug 09 05:15:01 PM PDT 24
Peak memory 200740 kb
Host smart-06a339a7-e2f8-4b0d-af43-77d65a033b47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434656460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.2434656460
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.1425498292
Short name T224
Test name
Test status
Simulation time 8133847331 ps
CPU time 9.34 seconds
Started Aug 09 05:14:47 PM PDT 24
Finished Aug 09 05:14:56 PM PDT 24
Peak memory 200800 kb
Host smart-bd37853e-1a98-40f8-97f7-01d0b8b4eb92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425498292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.1425498292
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.4248169491
Short name T534
Test name
Test status
Simulation time 2007457125 ps
CPU time 5.6 seconds
Started Aug 09 05:12:55 PM PDT 24
Finished Aug 09 05:13:01 PM PDT 24
Peak memory 200660 kb
Host smart-e7427dab-48f0-4844-acc8-79fb5e2e14e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248169491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.4248169491
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.3311083561
Short name T782
Test name
Test status
Simulation time 3451140840 ps
CPU time 3.77 seconds
Started Aug 09 05:12:47 PM PDT 24
Finished Aug 09 05:12:51 PM PDT 24
Peak memory 200844 kb
Host smart-62582ef3-4d9a-4849-9cd5-fd8b25742630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311083561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.3311083561
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.1115278295
Short name T32
Test name
Test status
Simulation time 146834381837 ps
CPU time 22.69 seconds
Started Aug 09 05:12:48 PM PDT 24
Finished Aug 09 05:13:10 PM PDT 24
Peak memory 201008 kb
Host smart-50b88f74-824c-48a3-89ee-226e585857a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115278295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_combo_detect.1115278295
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.138376376
Short name T658
Test name
Test status
Simulation time 2396352168 ps
CPU time 6.92 seconds
Started Aug 09 05:12:50 PM PDT 24
Finished Aug 09 05:12:57 PM PDT 24
Peak memory 200732 kb
Host smart-c19c8f2e-1d26-4479-8ac1-4ca57310b145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138376376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.138376376
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3652697751
Short name T490
Test name
Test status
Simulation time 2518172126 ps
CPU time 2.55 seconds
Started Aug 09 05:12:46 PM PDT 24
Finished Aug 09 05:12:49 PM PDT 24
Peak memory 200724 kb
Host smart-92d510d7-ffbd-492e-abee-fb6b55696735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652697751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3652697751
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1948928509
Short name T362
Test name
Test status
Simulation time 71287402297 ps
CPU time 88.56 seconds
Started Aug 09 05:12:48 PM PDT 24
Finished Aug 09 05:14:17 PM PDT 24
Peak memory 201048 kb
Host smart-f26afa51-f421-443c-b953-e4e78bd70487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948928509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.1948928509
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1249087355
Short name T577
Test name
Test status
Simulation time 3370986253 ps
CPU time 2.92 seconds
Started Aug 09 05:12:49 PM PDT 24
Finished Aug 09 05:12:52 PM PDT 24
Peak memory 200704 kb
Host smart-a70e456c-5e98-427f-bd06-a60c1eefe6b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249087355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.1249087355
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.1410297529
Short name T194
Test name
Test status
Simulation time 3388824736 ps
CPU time 9.75 seconds
Started Aug 09 05:12:53 PM PDT 24
Finished Aug 09 05:13:03 PM PDT 24
Peak memory 200784 kb
Host smart-11b93345-a1b8-4be4-8398-d5d8990c242a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410297529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.1410297529
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.1598699124
Short name T170
Test name
Test status
Simulation time 2710448076 ps
CPU time 1.04 seconds
Started Aug 09 05:12:50 PM PDT 24
Finished Aug 09 05:12:51 PM PDT 24
Peak memory 200764 kb
Host smart-0fa5afd9-2ff2-4583-b353-e4f90c97fd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598699124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.1598699124
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.1989124471
Short name T760
Test name
Test status
Simulation time 2491782339 ps
CPU time 1.7 seconds
Started Aug 09 05:12:53 PM PDT 24
Finished Aug 09 05:12:55 PM PDT 24
Peak memory 200724 kb
Host smart-e1781a34-2d27-4dcb-91a6-2fb8f61f2d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989124471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.1989124471
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.1415021459
Short name T662
Test name
Test status
Simulation time 2044263511 ps
CPU time 3.07 seconds
Started Aug 09 05:12:49 PM PDT 24
Finished Aug 09 05:12:52 PM PDT 24
Peak memory 200688 kb
Host smart-96261253-4a3f-474c-8455-fab54eb0d629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415021459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.1415021459
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.1665343619
Short name T211
Test name
Test status
Simulation time 2536416508 ps
CPU time 2.26 seconds
Started Aug 09 05:12:49 PM PDT 24
Finished Aug 09 05:12:51 PM PDT 24
Peak memory 200776 kb
Host smart-1d55d80d-c4de-4797-85d1-bf8a2f1b400c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665343619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.1665343619
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.3898655281
Short name T279
Test name
Test status
Simulation time 22011944428 ps
CPU time 56.15 seconds
Started Aug 09 05:12:50 PM PDT 24
Finished Aug 09 05:13:46 PM PDT 24
Peak memory 220488 kb
Host smart-749dfee6-155a-4f0e-9e1e-102b451ed175
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898655281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.3898655281
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.2255475259
Short name T448
Test name
Test status
Simulation time 2110310621 ps
CPU time 6.09 seconds
Started Aug 09 05:12:48 PM PDT 24
Finished Aug 09 05:12:54 PM PDT 24
Peak memory 200980 kb
Host smart-2d2a30da-b522-4ccf-bc68-5422c16004f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255475259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.2255475259
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.2492118727
Short name T53
Test name
Test status
Simulation time 15754068590 ps
CPU time 19.05 seconds
Started Aug 09 05:12:50 PM PDT 24
Finished Aug 09 05:13:09 PM PDT 24
Peak memory 200860 kb
Host smart-2c7101f2-8d06-4ce6-bad6-c5ff6c33c69a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492118727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.2492118727
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2664921838
Short name T210
Test name
Test status
Simulation time 53470605577 ps
CPU time 136.66 seconds
Started Aug 09 05:12:47 PM PDT 24
Finished Aug 09 05:15:04 PM PDT 24
Peak memory 216996 kb
Host smart-d5dc4be9-13f0-4524-8fbb-f132a4482cc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664921838 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.2664921838
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3321753951
Short name T120
Test name
Test status
Simulation time 3972678178 ps
CPU time 6.67 seconds
Started Aug 09 05:12:49 PM PDT 24
Finished Aug 09 05:12:56 PM PDT 24
Peak memory 200812 kb
Host smart-19ea9854-e23d-423d-8fad-a9ffdaebedb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321753951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ultra_low_pwr.3321753951
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.3722258108
Short name T475
Test name
Test status
Simulation time 2041906210 ps
CPU time 1.91 seconds
Started Aug 09 05:14:43 PM PDT 24
Finished Aug 09 05:14:45 PM PDT 24
Peak memory 200716 kb
Host smart-9f533ba3-1163-4914-b6ac-085f98a40b4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722258108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_te
st.3722258108
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3706855618
Short name T504
Test name
Test status
Simulation time 3796241522 ps
CPU time 10.55 seconds
Started Aug 09 05:14:44 PM PDT 24
Finished Aug 09 05:14:55 PM PDT 24
Peak memory 200804 kb
Host smart-83929dc2-d5f7-4c13-ac64-9168dfc5ab69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706855618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.3
706855618
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.3595600109
Short name T759
Test name
Test status
Simulation time 40019725020 ps
CPU time 51.12 seconds
Started Aug 09 05:14:42 PM PDT 24
Finished Aug 09 05:15:33 PM PDT 24
Peak memory 201040 kb
Host smart-693849a4-81c3-4732-920c-0dc0d39fe813
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595600109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.3595600109
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.2930215018
Short name T694
Test name
Test status
Simulation time 23600798372 ps
CPU time 16.54 seconds
Started Aug 09 05:14:46 PM PDT 24
Finished Aug 09 05:15:03 PM PDT 24
Peak memory 201084 kb
Host smart-30b9ada1-c99d-4685-b8de-f2701548bc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930215018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.2930215018
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.3661016510
Short name T416
Test name
Test status
Simulation time 2840472896 ps
CPU time 2.33 seconds
Started Aug 09 05:14:44 PM PDT 24
Finished Aug 09 05:14:47 PM PDT 24
Peak memory 200796 kb
Host smart-d95993c9-ddba-4db8-981d-5a4d9070ce0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661016510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.3661016510
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.3570269836
Short name T133
Test name
Test status
Simulation time 3438759234 ps
CPU time 9.48 seconds
Started Aug 09 05:14:46 PM PDT 24
Finished Aug 09 05:14:56 PM PDT 24
Peak memory 200768 kb
Host smart-c48444df-67b1-44d0-9f3d-8677096e1f01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570269836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_edge_detect.3570269836
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3331093740
Short name T646
Test name
Test status
Simulation time 2612514374 ps
CPU time 7.37 seconds
Started Aug 09 05:14:50 PM PDT 24
Finished Aug 09 05:14:58 PM PDT 24
Peak memory 200692 kb
Host smart-0f141a7e-d1bf-4846-a98c-737c788acb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331093740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.3331093740
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.1308171171
Short name T178
Test name
Test status
Simulation time 2453903737 ps
CPU time 3.62 seconds
Started Aug 09 05:14:46 PM PDT 24
Finished Aug 09 05:14:50 PM PDT 24
Peak memory 200772 kb
Host smart-af55f5b5-5d88-49a8-9b46-6cbbd703e3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308171171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.1308171171
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.2788002785
Short name T791
Test name
Test status
Simulation time 2117383908 ps
CPU time 1.78 seconds
Started Aug 09 05:14:51 PM PDT 24
Finished Aug 09 05:14:53 PM PDT 24
Peak memory 200696 kb
Host smart-09f10657-14a6-4b57-947e-c9263cc3b48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788002785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.2788002785
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.4101005017
Short name T739
Test name
Test status
Simulation time 2537164854 ps
CPU time 2.27 seconds
Started Aug 09 05:14:45 PM PDT 24
Finished Aug 09 05:14:47 PM PDT 24
Peak memory 200800 kb
Host smart-55238788-3816-4ee9-9625-19e8885ae583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101005017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.4101005017
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.3710616203
Short name T399
Test name
Test status
Simulation time 2116795596 ps
CPU time 3.84 seconds
Started Aug 09 05:14:41 PM PDT 24
Finished Aug 09 05:14:45 PM PDT 24
Peak memory 200712 kb
Host smart-8a0a7d6a-a7e7-4a97-8130-c2c01929d143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710616203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.3710616203
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.3591441982
Short name T171
Test name
Test status
Simulation time 15903283284 ps
CPU time 18.86 seconds
Started Aug 09 05:14:46 PM PDT 24
Finished Aug 09 05:15:05 PM PDT 24
Peak memory 200852 kb
Host smart-1b7b51d0-c338-4684-8042-3f179be4ef63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591441982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.3591441982
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.3885881348
Short name T477
Test name
Test status
Simulation time 10306056869 ps
CPU time 4.5 seconds
Started Aug 09 05:14:44 PM PDT 24
Finished Aug 09 05:14:48 PM PDT 24
Peak memory 200876 kb
Host smart-a34c4e66-a6ef-4f3e-af99-fc763a32d4a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885881348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ultra_low_pwr.3885881348
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.2643997678
Short name T552
Test name
Test status
Simulation time 2007768441 ps
CPU time 5.9 seconds
Started Aug 09 05:14:55 PM PDT 24
Finished Aug 09 05:15:00 PM PDT 24
Peak memory 200744 kb
Host smart-891b7922-57c1-4587-bc3e-9d8785b112bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643997678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.2643997678
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3851857558
Short name T42
Test name
Test status
Simulation time 296767060411 ps
CPU time 379.05 seconds
Started Aug 09 05:14:51 PM PDT 24
Finished Aug 09 05:21:10 PM PDT 24
Peak memory 200788 kb
Host smart-8bd107cb-cad0-4a38-aa1c-c82c0bdaf628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851857558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.3
851857558
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.2924160461
Short name T375
Test name
Test status
Simulation time 160748269183 ps
CPU time 106.09 seconds
Started Aug 09 05:14:52 PM PDT 24
Finished Aug 09 05:16:38 PM PDT 24
Peak memory 201024 kb
Host smart-2b023166-622f-4dc6-abac-102606ad3add
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924160461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.2924160461
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.791626134
Short name T588
Test name
Test status
Simulation time 78558154141 ps
CPU time 51.46 seconds
Started Aug 09 05:14:53 PM PDT 24
Finished Aug 09 05:15:45 PM PDT 24
Peak memory 201044 kb
Host smart-238bec52-e142-4b0a-af92-560141a86078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791626134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_wi
th_pre_cond.791626134
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.961479498
Short name T708
Test name
Test status
Simulation time 4093080049 ps
CPU time 3.2 seconds
Started Aug 09 05:14:50 PM PDT 24
Finished Aug 09 05:14:53 PM PDT 24
Peak memory 200768 kb
Host smart-819a4ba2-7841-448d-ae90-f892f3c7b725
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961479498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_ec_pwr_on_rst.961479498
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.1171710577
Short name T152
Test name
Test status
Simulation time 4522752743 ps
CPU time 4.98 seconds
Started Aug 09 05:14:52 PM PDT 24
Finished Aug 09 05:14:57 PM PDT 24
Peak memory 200848 kb
Host smart-3f9651a9-d7e7-42f5-aef7-0d5cbd60f75b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171710577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_edge_detect.1171710577
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2781565617
Short name T63
Test name
Test status
Simulation time 2612469999 ps
CPU time 7.6 seconds
Started Aug 09 05:14:46 PM PDT 24
Finished Aug 09 05:14:54 PM PDT 24
Peak memory 200812 kb
Host smart-2266d4e7-bc0a-4cbf-925e-7ed951946c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781565617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.2781565617
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.2434713388
Short name T158
Test name
Test status
Simulation time 2475913521 ps
CPU time 6.95 seconds
Started Aug 09 05:14:45 PM PDT 24
Finished Aug 09 05:14:52 PM PDT 24
Peak memory 200752 kb
Host smart-54a31371-16c8-4da9-9141-3be56f150629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434713388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.2434713388
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.4145874821
Short name T619
Test name
Test status
Simulation time 2267350071 ps
CPU time 2.37 seconds
Started Aug 09 05:14:47 PM PDT 24
Finished Aug 09 05:14:49 PM PDT 24
Peak memory 200736 kb
Host smart-716e6c63-f160-4957-b353-b3cbd4993821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145874821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.4145874821
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3515191889
Short name T606
Test name
Test status
Simulation time 2521998783 ps
CPU time 2.19 seconds
Started Aug 09 05:14:46 PM PDT 24
Finished Aug 09 05:14:48 PM PDT 24
Peak memory 200708 kb
Host smart-e60fe803-5d3d-46d8-aebf-a940c311ca29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515191889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.3515191889
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.1580850696
Short name T461
Test name
Test status
Simulation time 2121039982 ps
CPU time 1.9 seconds
Started Aug 09 05:14:46 PM PDT 24
Finished Aug 09 05:14:48 PM PDT 24
Peak memory 201012 kb
Host smart-01b5c6b4-9738-425a-a4de-b8585f84fe45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580850696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.1580850696
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.734618684
Short name T499
Test name
Test status
Simulation time 14819351702 ps
CPU time 10.01 seconds
Started Aug 09 05:14:50 PM PDT 24
Finished Aug 09 05:15:01 PM PDT 24
Peak memory 200816 kb
Host smart-18a7ce25-6335-4967-8c35-2a44604f8ea5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734618684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_st
ress_all.734618684
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1462289537
Short name T459
Test name
Test status
Simulation time 4555630962 ps
CPU time 5.59 seconds
Started Aug 09 05:14:51 PM PDT 24
Finished Aug 09 05:14:57 PM PDT 24
Peak memory 200784 kb
Host smart-c7332fae-e0c5-4d52-bd19-552769b88d41
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462289537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.1462289537
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.1930481832
Short name T406
Test name
Test status
Simulation time 2045081074 ps
CPU time 1.7 seconds
Started Aug 09 05:14:54 PM PDT 24
Finished Aug 09 05:14:56 PM PDT 24
Peak memory 200652 kb
Host smart-ef13dbf0-a84e-424a-b5c5-2d308921e982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930481832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.1930481832
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3195253122
Short name T564
Test name
Test status
Simulation time 3485273654 ps
CPU time 9.95 seconds
Started Aug 09 05:14:52 PM PDT 24
Finished Aug 09 05:15:02 PM PDT 24
Peak memory 200812 kb
Host smart-f33dd333-5754-46cb-9e69-76baf44c89e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195253122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.3
195253122
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.946979515
Short name T188
Test name
Test status
Simulation time 93568938398 ps
CPU time 117.67 seconds
Started Aug 09 05:14:53 PM PDT 24
Finished Aug 09 05:16:50 PM PDT 24
Peak memory 201024 kb
Host smart-4efe3de9-e18e-49d1-aa7a-e4ae065f915f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946979515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_combo_detect.946979515
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.415156231
Short name T713
Test name
Test status
Simulation time 3025463485 ps
CPU time 8.25 seconds
Started Aug 09 05:14:59 PM PDT 24
Finished Aug 09 05:15:07 PM PDT 24
Peak memory 200796 kb
Host smart-4369d033-4e91-4523-9b3b-9ba8a7db5cab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415156231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_ec_pwr_on_rst.415156231
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.1167877010
Short name T233
Test name
Test status
Simulation time 3746430334 ps
CPU time 2.53 seconds
Started Aug 09 05:14:59 PM PDT 24
Finished Aug 09 05:15:02 PM PDT 24
Peak memory 200856 kb
Host smart-0d7328f8-64c2-4a22-8cf0-8e5d951c54db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167877010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_edge_detect.1167877010
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.1095326593
Short name T550
Test name
Test status
Simulation time 2623477326 ps
CPU time 2.43 seconds
Started Aug 09 05:14:53 PM PDT 24
Finished Aug 09 05:14:55 PM PDT 24
Peak memory 200764 kb
Host smart-75b278e4-c631-4336-80ca-bc80c4242d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095326593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.1095326593
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.4174502875
Short name T689
Test name
Test status
Simulation time 2474753670 ps
CPU time 3.56 seconds
Started Aug 09 05:14:53 PM PDT 24
Finished Aug 09 05:14:56 PM PDT 24
Peak memory 200812 kb
Host smart-ba9da987-c45a-4bc2-b4d8-4267615acb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174502875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.4174502875
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3368040000
Short name T526
Test name
Test status
Simulation time 2137977755 ps
CPU time 2.04 seconds
Started Aug 09 05:14:56 PM PDT 24
Finished Aug 09 05:14:58 PM PDT 24
Peak memory 200664 kb
Host smart-2da0a7f2-b957-4a04-87d9-adc9844b1f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368040000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.3368040000
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3653028792
Short name T299
Test name
Test status
Simulation time 2533397116 ps
CPU time 2.43 seconds
Started Aug 09 05:14:52 PM PDT 24
Finished Aug 09 05:14:55 PM PDT 24
Peak memory 200700 kb
Host smart-754ac00c-5dec-4aaf-a964-48372c0115b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653028792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.3653028792
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.534119546
Short name T615
Test name
Test status
Simulation time 2112645072 ps
CPU time 5.91 seconds
Started Aug 09 05:14:50 PM PDT 24
Finished Aug 09 05:14:56 PM PDT 24
Peak memory 200652 kb
Host smart-2e2e6af0-620e-40fc-a136-d553fadcdb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534119546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.534119546
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.3493172516
Short name T651
Test name
Test status
Simulation time 178137657385 ps
CPU time 219.71 seconds
Started Aug 09 05:14:53 PM PDT 24
Finished Aug 09 05:18:33 PM PDT 24
Peak memory 201048 kb
Host smart-e08aef09-cee5-4f0f-b6f7-2fade477e209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493172516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.3493172516
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2500216566
Short name T200
Test name
Test status
Simulation time 80026335675 ps
CPU time 198.12 seconds
Started Aug 09 05:14:51 PM PDT 24
Finished Aug 09 05:18:09 PM PDT 24
Peak memory 209320 kb
Host smart-f715ede6-2e94-4bc4-98ea-0e49a8e2f3e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500216566 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.2500216566
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.2704148329
Short name T463
Test name
Test status
Simulation time 2796786205 ps
CPU time 1.96 seconds
Started Aug 09 05:14:58 PM PDT 24
Finished Aug 09 05:15:01 PM PDT 24
Peak memory 200844 kb
Host smart-b2849f8b-5e62-4f8d-916b-e2b79f79d171
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704148329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.2704148329
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.3712792702
Short name T446
Test name
Test status
Simulation time 2031518990 ps
CPU time 2.03 seconds
Started Aug 09 05:14:56 PM PDT 24
Finished Aug 09 05:14:58 PM PDT 24
Peak memory 200744 kb
Host smart-82415e3a-a5f7-4bf4-82ff-c19707a84642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712792702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.3712792702
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1619136711
Short name T773
Test name
Test status
Simulation time 123001457730 ps
CPU time 18.7 seconds
Started Aug 09 05:14:53 PM PDT 24
Finished Aug 09 05:15:12 PM PDT 24
Peak memory 200800 kb
Host smart-a8be3fce-46c0-4434-993f-d8cf22bb9b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619136711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.1
619136711
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.1049187911
Short name T266
Test name
Test status
Simulation time 112241068330 ps
CPU time 18.78 seconds
Started Aug 09 05:14:55 PM PDT 24
Finished Aug 09 05:15:14 PM PDT 24
Peak memory 200964 kb
Host smart-935850b7-5880-4a45-b08e-6b2006d34b49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049187911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.1049187911
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3169862385
Short name T367
Test name
Test status
Simulation time 164096317933 ps
CPU time 422.19 seconds
Started Aug 09 05:14:56 PM PDT 24
Finished Aug 09 05:21:58 PM PDT 24
Peak memory 201056 kb
Host smart-ba0ba2b6-b5c3-4f35-b3d7-96299b1892fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169862385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_w
ith_pre_cond.3169862385
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1520763758
Short name T685
Test name
Test status
Simulation time 3334185021 ps
CPU time 2.75 seconds
Started Aug 09 05:14:53 PM PDT 24
Finished Aug 09 05:14:56 PM PDT 24
Peak memory 200688 kb
Host smart-5ffa5910-bf0c-4131-850c-920d7a0598eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520763758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.1520763758
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.2517714585
Short name T763
Test name
Test status
Simulation time 5313892809 ps
CPU time 1.08 seconds
Started Aug 09 05:14:54 PM PDT 24
Finished Aug 09 05:14:55 PM PDT 24
Peak memory 200704 kb
Host smart-b5cb33e0-2422-4d1c-b5b9-4f5001111cdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517714585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.2517714585
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2127021884
Short name T747
Test name
Test status
Simulation time 2621614289 ps
CPU time 3.89 seconds
Started Aug 09 05:14:54 PM PDT 24
Finished Aug 09 05:14:58 PM PDT 24
Peak memory 200760 kb
Host smart-84b4fa44-68a5-42aa-8bd6-742a23359c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127021884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.2127021884
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3630545729
Short name T520
Test name
Test status
Simulation time 2482494000 ps
CPU time 2.94 seconds
Started Aug 09 05:14:51 PM PDT 24
Finished Aug 09 05:14:54 PM PDT 24
Peak memory 200784 kb
Host smart-490f4570-419f-4f7b-9a0b-164acb556dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630545729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.3630545729
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.4262373032
Short name T407
Test name
Test status
Simulation time 2049891043 ps
CPU time 1.98 seconds
Started Aug 09 05:14:52 PM PDT 24
Finished Aug 09 05:14:54 PM PDT 24
Peak memory 200712 kb
Host smart-145e8f81-2430-43d8-8fbc-af4cf9be9bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262373032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.4262373032
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.320144969
Short name T704
Test name
Test status
Simulation time 2525874820 ps
CPU time 2.39 seconds
Started Aug 09 05:14:51 PM PDT 24
Finished Aug 09 05:14:54 PM PDT 24
Peak memory 200796 kb
Host smart-bee6367a-712e-4e19-8512-2ed83837394d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320144969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.320144969
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.148207792
Short name T421
Test name
Test status
Simulation time 2128449315 ps
CPU time 1.88 seconds
Started Aug 09 05:14:52 PM PDT 24
Finished Aug 09 05:14:54 PM PDT 24
Peak memory 200680 kb
Host smart-dea56f59-93fd-4f89-b588-1f33a2020a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148207792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.148207792
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.3865614020
Short name T77
Test name
Test status
Simulation time 14422324218 ps
CPU time 8.78 seconds
Started Aug 09 05:14:52 PM PDT 24
Finished Aug 09 05:15:01 PM PDT 24
Peak memory 200800 kb
Host smart-8d4609d2-5a38-4294-9228-2161b84996a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865614020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.3865614020
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2733054390
Short name T70
Test name
Test status
Simulation time 10807361869 ps
CPU time 9.03 seconds
Started Aug 09 05:14:52 PM PDT 24
Finished Aug 09 05:15:01 PM PDT 24
Peak memory 200892 kb
Host smart-6ef8501e-97b3-410a-a562-5c1bb710ebcb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733054390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.2733054390
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.1424055391
Short name T634
Test name
Test status
Simulation time 2039460593 ps
CPU time 1.83 seconds
Started Aug 09 05:15:01 PM PDT 24
Finished Aug 09 05:15:03 PM PDT 24
Peak memory 200652 kb
Host smart-06118621-4102-4c2c-9925-da2c3433d117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424055391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.1424055391
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.635382631
Short name T711
Test name
Test status
Simulation time 3780473523 ps
CPU time 10.29 seconds
Started Aug 09 05:15:00 PM PDT 24
Finished Aug 09 05:15:11 PM PDT 24
Peak memory 200880 kb
Host smart-4fcd9ef4-21ef-49e0-bead-89ec0d8e2a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635382631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.635382631
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.1028203659
Short name T336
Test name
Test status
Simulation time 120718431054 ps
CPU time 54.13 seconds
Started Aug 09 05:15:00 PM PDT 24
Finished Aug 09 05:15:54 PM PDT 24
Peak memory 201040 kb
Host smart-2ab0bc6d-b79d-427b-9b2a-210d119babd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028203659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.1028203659
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.501988411
Short name T345
Test name
Test status
Simulation time 73104444814 ps
CPU time 47.92 seconds
Started Aug 09 05:15:04 PM PDT 24
Finished Aug 09 05:15:52 PM PDT 24
Peak memory 201184 kb
Host smart-b4c1bfad-b042-4377-bf7e-2a9e859eacc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501988411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_wi
th_pre_cond.501988411
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.958505401
Short name T485
Test name
Test status
Simulation time 4026357769 ps
CPU time 3.15 seconds
Started Aug 09 05:14:54 PM PDT 24
Finished Aug 09 05:14:57 PM PDT 24
Peak memory 200832 kb
Host smart-a4c14f55-a4da-4ef1-8675-9475efe0e74e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958505401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_ec_pwr_on_rst.958505401
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.3797860290
Short name T177
Test name
Test status
Simulation time 3307937112 ps
CPU time 4.42 seconds
Started Aug 09 05:15:00 PM PDT 24
Finished Aug 09 05:15:05 PM PDT 24
Peak memory 200808 kb
Host smart-8ed8817a-278f-405a-bf91-8ea6b43fa655
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797860290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.3797860290
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.593852692
Short name T111
Test name
Test status
Simulation time 2638507876 ps
CPU time 2.37 seconds
Started Aug 09 05:14:52 PM PDT 24
Finished Aug 09 05:14:54 PM PDT 24
Peak memory 200696 kb
Host smart-3c583ded-d16d-4674-bafd-07e4c4227c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593852692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.593852692
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2229382428
Short name T718
Test name
Test status
Simulation time 2459640484 ps
CPU time 2.22 seconds
Started Aug 09 05:14:59 PM PDT 24
Finished Aug 09 05:15:01 PM PDT 24
Peak memory 200792 kb
Host smart-6f16d1d1-e3ef-4295-908f-48340f4417b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229382428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.2229382428
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3115404005
Short name T449
Test name
Test status
Simulation time 2187806205 ps
CPU time 1.98 seconds
Started Aug 09 05:15:00 PM PDT 24
Finished Aug 09 05:15:02 PM PDT 24
Peak memory 200776 kb
Host smart-29d1d55d-223d-4ce7-9c58-a01711b1aa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115404005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.3115404005
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.4060984615
Short name T62
Test name
Test status
Simulation time 2625638292 ps
CPU time 1.19 seconds
Started Aug 09 05:14:54 PM PDT 24
Finished Aug 09 05:14:55 PM PDT 24
Peak memory 200856 kb
Host smart-ee889bff-05f8-4363-bb2e-6e07549d2529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060984615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.4060984615
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.4058292151
Short name T542
Test name
Test status
Simulation time 2133223619 ps
CPU time 1.78 seconds
Started Aug 09 05:14:52 PM PDT 24
Finished Aug 09 05:14:54 PM PDT 24
Peak memory 200652 kb
Host smart-7205a9b5-cfc1-464c-8666-4bd2ae0a67a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058292151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.4058292151
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.1176533352
Short name T7
Test name
Test status
Simulation time 11323926365 ps
CPU time 15.32 seconds
Started Aug 09 05:15:03 PM PDT 24
Finished Aug 09 05:15:19 PM PDT 24
Peak memory 200780 kb
Host smart-8bd06bc7-f294-4ee4-9624-571648e3f65d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176533352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.1176533352
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3265206823
Short name T690
Test name
Test status
Simulation time 7270812519 ps
CPU time 2.21 seconds
Started Aug 09 05:15:00 PM PDT 24
Finished Aug 09 05:15:03 PM PDT 24
Peak memory 200816 kb
Host smart-3d164519-d908-48f6-a5b0-546f2ee55caf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265206823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.3265206823
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.696732652
Short name T398
Test name
Test status
Simulation time 2059504782 ps
CPU time 1.39 seconds
Started Aug 09 05:15:01 PM PDT 24
Finished Aug 09 05:15:02 PM PDT 24
Peak memory 200768 kb
Host smart-98f55418-7669-4980-aab0-4de21b10c11f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696732652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_tes
t.696732652
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1224371257
Short name T21
Test name
Test status
Simulation time 3722494674 ps
CPU time 3.45 seconds
Started Aug 09 05:15:03 PM PDT 24
Finished Aug 09 05:15:06 PM PDT 24
Peak memory 200812 kb
Host smart-a4f2a72e-e695-4b9d-a26a-f7bfb77d7472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224371257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.1
224371257
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.2472992840
Short name T380
Test name
Test status
Simulation time 51585198521 ps
CPU time 63.7 seconds
Started Aug 09 05:15:03 PM PDT 24
Finished Aug 09 05:16:06 PM PDT 24
Peak memory 201088 kb
Host smart-9ccb389e-be3b-4666-b230-6aeff4e0e653
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472992840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.2472992840
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.43942594
Short name T766
Test name
Test status
Simulation time 3776934551 ps
CPU time 3.07 seconds
Started Aug 09 05:15:00 PM PDT 24
Finished Aug 09 05:15:03 PM PDT 24
Peak memory 200820 kb
Host smart-495fce9a-2096-4170-a519-4055c54961fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43942594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_ec_pwr_on_rst.43942594
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.2791232545
Short name T738
Test name
Test status
Simulation time 3024205208 ps
CPU time 2.75 seconds
Started Aug 09 05:15:02 PM PDT 24
Finished Aug 09 05:15:05 PM PDT 24
Peak memory 200784 kb
Host smart-a4a22927-1d95-4d07-b072-db1b5385fc61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791232545 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.2791232545
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3226580944
Short name T417
Test name
Test status
Simulation time 2618645108 ps
CPU time 3.82 seconds
Started Aug 09 05:15:02 PM PDT 24
Finished Aug 09 05:15:06 PM PDT 24
Peak memory 200816 kb
Host smart-1bdc8904-1a70-48ba-b45b-e7f8eacf5332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226580944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.3226580944
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.822114040
Short name T654
Test name
Test status
Simulation time 2470856133 ps
CPU time 2.25 seconds
Started Aug 09 05:15:02 PM PDT 24
Finished Aug 09 05:15:05 PM PDT 24
Peak memory 201092 kb
Host smart-684a2438-223c-46d4-af73-df4d7a819f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822114040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.822114040
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2688936432
Short name T501
Test name
Test status
Simulation time 2179118098 ps
CPU time 3.48 seconds
Started Aug 09 05:15:01 PM PDT 24
Finished Aug 09 05:15:05 PM PDT 24
Peak memory 200700 kb
Host smart-1ba839a2-f55f-4e5e-b374-6d540ba7cccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688936432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.2688936432
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.4146389311
Short name T540
Test name
Test status
Simulation time 2524434014 ps
CPU time 3.64 seconds
Started Aug 09 05:15:00 PM PDT 24
Finished Aug 09 05:15:04 PM PDT 24
Peak memory 200752 kb
Host smart-7c9cd756-14b7-4633-a8e7-c559ca17b2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146389311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.4146389311
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.2391933514
Short name T665
Test name
Test status
Simulation time 2116300271 ps
CPU time 3.21 seconds
Started Aug 09 05:15:00 PM PDT 24
Finished Aug 09 05:15:04 PM PDT 24
Peak memory 200692 kb
Host smart-7f5c69b5-c95b-4e71-91e7-f3b32cf4a93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391933514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.2391933514
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3759341698
Short name T282
Test name
Test status
Simulation time 57236465906 ps
CPU time 126.79 seconds
Started Aug 09 05:15:03 PM PDT 24
Finished Aug 09 05:17:10 PM PDT 24
Peak memory 209412 kb
Host smart-f46c5f02-85ac-4e18-9338-9cb201deb717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759341698 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.3759341698
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.1228203465
Short name T762
Test name
Test status
Simulation time 2028111869 ps
CPU time 1.79 seconds
Started Aug 09 05:15:09 PM PDT 24
Finished Aug 09 05:15:11 PM PDT 24
Peak memory 200764 kb
Host smart-06ed7782-49f4-4a35-9665-8566ade60257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228203465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.1228203465
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3354240573
Short name T473
Test name
Test status
Simulation time 3120176241 ps
CPU time 2.13 seconds
Started Aug 09 05:15:08 PM PDT 24
Finished Aug 09 05:15:10 PM PDT 24
Peak memory 200812 kb
Host smart-a1af3472-3c33-4ca6-9535-94fe656ac131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354240573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.3
354240573
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.664663259
Short name T104
Test name
Test status
Simulation time 66179866047 ps
CPU time 173.24 seconds
Started Aug 09 05:15:10 PM PDT 24
Finished Aug 09 05:18:03 PM PDT 24
Peak memory 201024 kb
Host smart-f1495f72-f3ea-4ac8-8766-0a26306f4b51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664663259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_combo_detect.664663259
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3912972448
Short name T244
Test name
Test status
Simulation time 101914411479 ps
CPU time 69.99 seconds
Started Aug 09 05:15:09 PM PDT 24
Finished Aug 09 05:16:19 PM PDT 24
Peak memory 201012 kb
Host smart-b5378585-74fe-4fbe-a150-b6ae8a521aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912972448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.3912972448
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.516500410
Short name T626
Test name
Test status
Simulation time 4625110436 ps
CPU time 6.64 seconds
Started Aug 09 05:15:10 PM PDT 24
Finished Aug 09 05:15:17 PM PDT 24
Peak memory 200840 kb
Host smart-2258ba30-ee75-4637-bb7e-360426577fcc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516500410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_ec_pwr_on_rst.516500410
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.3908327878
Short name T670
Test name
Test status
Simulation time 2632326340 ps
CPU time 1.87 seconds
Started Aug 09 05:15:08 PM PDT 24
Finished Aug 09 05:15:10 PM PDT 24
Peak memory 200744 kb
Host smart-5aacf8a7-4c4e-4e99-b668-9614b6e92034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908327878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.3908327878
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.637553293
Short name T547
Test name
Test status
Simulation time 2465405635 ps
CPU time 3.15 seconds
Started Aug 09 05:15:03 PM PDT 24
Finished Aug 09 05:15:06 PM PDT 24
Peak memory 201088 kb
Host smart-6cde67ad-810f-418d-81c8-6eed1b965cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637553293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.637553293
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.4145614303
Short name T556
Test name
Test status
Simulation time 2093799826 ps
CPU time 3.35 seconds
Started Aug 09 05:15:04 PM PDT 24
Finished Aug 09 05:15:07 PM PDT 24
Peak memory 200756 kb
Host smart-d435c4f8-8fee-4052-bf71-daa5006606e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145614303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.4145614303
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.23833920
Short name T784
Test name
Test status
Simulation time 2516504593 ps
CPU time 4.09 seconds
Started Aug 09 05:15:03 PM PDT 24
Finished Aug 09 05:15:07 PM PDT 24
Peak memory 200832 kb
Host smart-80479dd1-f3ba-4970-b7e2-fa452ed77380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23833920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.23833920
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.3190286632
Short name T736
Test name
Test status
Simulation time 2112914770 ps
CPU time 6.57 seconds
Started Aug 09 05:15:03 PM PDT 24
Finished Aug 09 05:15:09 PM PDT 24
Peak memory 200668 kb
Host smart-72052128-f2e4-4544-ad1e-4bac3843691c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190286632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.3190286632
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.2308809518
Short name T440
Test name
Test status
Simulation time 10821481511 ps
CPU time 8.02 seconds
Started Aug 09 05:15:13 PM PDT 24
Finished Aug 09 05:15:21 PM PDT 24
Peak memory 200760 kb
Host smart-9f7f5bdf-aa6f-44d6-babc-2f8214bf0cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308809518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s
tress_all.2308809518
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.4095738528
Short name T313
Test name
Test status
Simulation time 49542270145 ps
CPU time 64.86 seconds
Started Aug 09 05:15:09 PM PDT 24
Finished Aug 09 05:16:14 PM PDT 24
Peak memory 209512 kb
Host smart-9b7fdfb5-ae4f-4002-bd32-fdab443a50dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095738528 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.4095738528
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.218365045
Short name T464
Test name
Test status
Simulation time 3779464018 ps
CPU time 2.34 seconds
Started Aug 09 05:15:08 PM PDT 24
Finished Aug 09 05:15:11 PM PDT 24
Peak memory 200880 kb
Host smart-8e41c521-03e9-40b0-824b-544fa8b506f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218365045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_ultra_low_pwr.218365045
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.989479183
Short name T673
Test name
Test status
Simulation time 2010714597 ps
CPU time 5.55 seconds
Started Aug 09 05:15:14 PM PDT 24
Finished Aug 09 05:15:20 PM PDT 24
Peak memory 200704 kb
Host smart-34b941bf-dcb2-4ff1-8cea-8b74bcbd568c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989479183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_tes
t.989479183
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2870665031
Short name T252
Test name
Test status
Simulation time 3474622509 ps
CPU time 1.08 seconds
Started Aug 09 05:15:10 PM PDT 24
Finished Aug 09 05:15:11 PM PDT 24
Peak memory 200800 kb
Host smart-f07aea36-172c-4990-a401-b81a0530e196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870665031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.2
870665031
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.1646197233
Short name T381
Test name
Test status
Simulation time 100080743381 ps
CPU time 250.12 seconds
Started Aug 09 05:15:12 PM PDT 24
Finished Aug 09 05:19:23 PM PDT 24
Peak memory 201104 kb
Host smart-ed34c79c-e800-4d0c-9c63-41355a5b8f36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646197233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.1646197233
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1351439118
Short name T455
Test name
Test status
Simulation time 4112701753 ps
CPU time 11.32 seconds
Started Aug 09 05:15:09 PM PDT 24
Finished Aug 09 05:15:20 PM PDT 24
Peak memory 200664 kb
Host smart-7b9f4f76-a80c-4151-899d-0de87c13b46a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351439118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.1351439118
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.4168049129
Short name T153
Test name
Test status
Simulation time 4299628296 ps
CPU time 5.31 seconds
Started Aug 09 05:15:11 PM PDT 24
Finished Aug 09 05:15:16 PM PDT 24
Peak memory 200856 kb
Host smart-b8452ca8-6a17-42f5-9c65-b780c5e441e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168049129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_edge_detect.4168049129
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.62814608
Short name T522
Test name
Test status
Simulation time 2638833637 ps
CPU time 2.43 seconds
Started Aug 09 05:15:11 PM PDT 24
Finished Aug 09 05:15:14 PM PDT 24
Peak memory 200840 kb
Host smart-996d03bb-71e3-4eda-8402-c71f02d5a91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62814608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.62814608
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1600712139
Short name T306
Test name
Test status
Simulation time 2459988219 ps
CPU time 3.67 seconds
Started Aug 09 05:15:11 PM PDT 24
Finished Aug 09 05:15:14 PM PDT 24
Peak memory 200740 kb
Host smart-0909f7a0-9beb-499c-91e0-629a73116a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600712139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.1600712139
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3363434605
Short name T659
Test name
Test status
Simulation time 2251700211 ps
CPU time 3.3 seconds
Started Aug 09 05:15:10 PM PDT 24
Finished Aug 09 05:15:14 PM PDT 24
Peak memory 200808 kb
Host smart-c3de32c8-8774-4f09-ab4a-5c082747aa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363434605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.3363434605
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.2340394754
Short name T744
Test name
Test status
Simulation time 2577823692 ps
CPU time 1.46 seconds
Started Aug 09 05:15:11 PM PDT 24
Finished Aug 09 05:15:13 PM PDT 24
Peak memory 200752 kb
Host smart-77ff6199-12e0-4a60-be00-de827e93fb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340394754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.2340394754
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.33034526
Short name T420
Test name
Test status
Simulation time 2112681836 ps
CPU time 5.92 seconds
Started Aug 09 05:15:12 PM PDT 24
Finished Aug 09 05:15:19 PM PDT 24
Peak memory 200616 kb
Host smart-686a04ff-cd28-45ef-a066-cdf89fe84f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33034526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.33034526
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.2196478701
Short name T683
Test name
Test status
Simulation time 177380824087 ps
CPU time 73.21 seconds
Started Aug 09 05:15:11 PM PDT 24
Finished Aug 09 05:16:25 PM PDT 24
Peak memory 200756 kb
Host smart-847c93ac-3233-4d96-a4a3-2dca05d6dd25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196478701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s
tress_all.2196478701
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.4273800646
Short name T265
Test name
Test status
Simulation time 98576424046 ps
CPU time 63 seconds
Started Aug 09 05:15:08 PM PDT 24
Finished Aug 09 05:16:11 PM PDT 24
Peak memory 209376 kb
Host smart-0a87a549-cd1b-46d8-8336-9efb47a4985a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273800646 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.4273800646
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.788608436
Short name T119
Test name
Test status
Simulation time 7216162661 ps
CPU time 7.41 seconds
Started Aug 09 05:15:12 PM PDT 24
Finished Aug 09 05:15:19 PM PDT 24
Peak memory 200796 kb
Host smart-da2c9055-5fda-40aa-96ea-8370dbd297ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788608436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_ultra_low_pwr.788608436
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.3217120010
Short name T692
Test name
Test status
Simulation time 2098404402 ps
CPU time 0.99 seconds
Started Aug 09 05:15:11 PM PDT 24
Finished Aug 09 05:15:12 PM PDT 24
Peak memory 200820 kb
Host smart-a121ba42-97e2-4c08-9fe1-fe4ed3fd15c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217120010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.3217120010
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.636117529
Short name T586
Test name
Test status
Simulation time 145690773759 ps
CPU time 361.83 seconds
Started Aug 09 05:15:09 PM PDT 24
Finished Aug 09 05:21:11 PM PDT 24
Peak memory 200840 kb
Host smart-1f6dcfec-205e-4dfd-979b-2890a68dc548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636117529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.636117529
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.3005211545
Short name T505
Test name
Test status
Simulation time 141019387007 ps
CPU time 84.08 seconds
Started Aug 09 05:15:12 PM PDT 24
Finished Aug 09 05:16:36 PM PDT 24
Peak memory 201080 kb
Host smart-88f8bd80-cbfa-4db6-b3e9-46d4eb19cc0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005211545 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_combo_detect.3005211545
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3308240901
Short name T93
Test name
Test status
Simulation time 27836191210 ps
CPU time 35.74 seconds
Started Aug 09 05:15:12 PM PDT 24
Finished Aug 09 05:15:48 PM PDT 24
Peak memory 201184 kb
Host smart-cbe92064-cd0e-4225-a0f5-a9f4e3f062fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308240901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.3308240901
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1163162037
Short name T650
Test name
Test status
Simulation time 2998261871 ps
CPU time 8.23 seconds
Started Aug 09 05:15:10 PM PDT 24
Finished Aug 09 05:15:19 PM PDT 24
Peak memory 200744 kb
Host smart-5412a311-0722-4e23-9df1-c474d4d8beb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163162037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.1163162037
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.4218139478
Short name T11
Test name
Test status
Simulation time 4513592897 ps
CPU time 1.52 seconds
Started Aug 09 05:15:10 PM PDT 24
Finished Aug 09 05:15:12 PM PDT 24
Peak memory 200824 kb
Host smart-b2e275f4-cbb3-4ad0-8ba0-9202073d8f26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218139478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.4218139478
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2130587632
Short name T489
Test name
Test status
Simulation time 2623105431 ps
CPU time 2.48 seconds
Started Aug 09 05:15:14 PM PDT 24
Finished Aug 09 05:15:16 PM PDT 24
Peak memory 200704 kb
Host smart-f8d69562-22ec-4d32-a037-1696ef8b43c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130587632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.2130587632
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.4223020582
Short name T579
Test name
Test status
Simulation time 2452635658 ps
CPU time 6.97 seconds
Started Aug 09 05:15:10 PM PDT 24
Finished Aug 09 05:15:17 PM PDT 24
Peak memory 200768 kb
Host smart-9bec7a6f-4a97-45dc-8b0a-afcef92d68a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223020582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.4223020582
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.951910506
Short name T676
Test name
Test status
Simulation time 2170263203 ps
CPU time 3.19 seconds
Started Aug 09 05:15:08 PM PDT 24
Finished Aug 09 05:15:12 PM PDT 24
Peak memory 200720 kb
Host smart-30ce1774-2da6-46d3-af8e-1eeee4df221f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951910506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.951910506
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.127918460
Short name T497
Test name
Test status
Simulation time 2528505159 ps
CPU time 2.27 seconds
Started Aug 09 05:15:11 PM PDT 24
Finished Aug 09 05:15:13 PM PDT 24
Peak memory 200696 kb
Host smart-c3325f0a-d66a-47e3-a24e-4549ebf0214f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127918460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.127918460
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.3584490883
Short name T402
Test name
Test status
Simulation time 2114687115 ps
CPU time 3.23 seconds
Started Aug 09 05:15:10 PM PDT 24
Finished Aug 09 05:15:13 PM PDT 24
Peak memory 200652 kb
Host smart-da424081-8134-4454-9298-6d9c719da556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584490883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.3584490883
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.1369707263
Short name T735
Test name
Test status
Simulation time 9946208683 ps
CPU time 7.18 seconds
Started Aug 09 05:15:08 PM PDT 24
Finished Aug 09 05:15:15 PM PDT 24
Peak memory 200876 kb
Host smart-1c335fa6-a944-4198-8422-519486c8abeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369707263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.1369707263
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2114126490
Short name T141
Test name
Test status
Simulation time 32836618659 ps
CPU time 58.01 seconds
Started Aug 09 05:15:12 PM PDT 24
Finished Aug 09 05:16:10 PM PDT 24
Peak memory 209444 kb
Host smart-1e088a7f-33f7-4531-a507-2e6ce2ddbe5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114126490 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.2114126490
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1504229687
Short name T125
Test name
Test status
Simulation time 10531798740 ps
CPU time 8.01 seconds
Started Aug 09 05:15:12 PM PDT 24
Finished Aug 09 05:15:20 PM PDT 24
Peak memory 200840 kb
Host smart-099330b0-cc1c-4a7b-afda-48e7c0e62f0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504229687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.1504229687
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.4143768148
Short name T549
Test name
Test status
Simulation time 2010909367 ps
CPU time 6.02 seconds
Started Aug 09 05:15:19 PM PDT 24
Finished Aug 09 05:15:26 PM PDT 24
Peak memory 200804 kb
Host smart-af52659b-d182-4845-950f-757b6b6ce256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143768148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.4143768148
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.3516009691
Short name T548
Test name
Test status
Simulation time 3544408349 ps
CPU time 2.89 seconds
Started Aug 09 05:15:19 PM PDT 24
Finished Aug 09 05:15:22 PM PDT 24
Peak memory 200880 kb
Host smart-c4d151c2-898b-4f2d-92ac-45082b7f4f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516009691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.3
516009691
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.2537628741
Short name T617
Test name
Test status
Simulation time 180393847675 ps
CPU time 403.44 seconds
Started Aug 09 05:15:20 PM PDT 24
Finished Aug 09 05:22:04 PM PDT 24
Peak memory 201368 kb
Host smart-dea769bc-1cd6-4848-bce7-df2fb005e64c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537628741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_combo_detect.2537628741
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.2142684179
Short name T616
Test name
Test status
Simulation time 28081264756 ps
CPU time 73.26 seconds
Started Aug 09 05:15:20 PM PDT 24
Finished Aug 09 05:16:34 PM PDT 24
Peak memory 201040 kb
Host smart-86cf73b0-f5ea-408d-9ff7-3f81e86defc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142684179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.2142684179
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3827051124
Short name T664
Test name
Test status
Simulation time 3364574814 ps
CPU time 3.5 seconds
Started Aug 09 05:15:20 PM PDT 24
Finished Aug 09 05:15:24 PM PDT 24
Peak memory 200768 kb
Host smart-a6dabe25-0fef-45ac-8425-b9b58758be08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827051124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.3827051124
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.3653151717
Short name T148
Test name
Test status
Simulation time 4958717214 ps
CPU time 2.34 seconds
Started Aug 09 05:15:19 PM PDT 24
Finished Aug 09 05:15:22 PM PDT 24
Peak memory 200836 kb
Host smart-8c89d2df-5370-4c4d-93c4-12b89366f826
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653151717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.3653151717
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2171243256
Short name T640
Test name
Test status
Simulation time 2637009184 ps
CPU time 2.35 seconds
Started Aug 09 05:15:18 PM PDT 24
Finished Aug 09 05:15:21 PM PDT 24
Peak memory 200736 kb
Host smart-efaa24a7-180c-4495-8a83-a897a131cda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171243256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.2171243256
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.4108494440
Short name T643
Test name
Test status
Simulation time 2490030048 ps
CPU time 2.3 seconds
Started Aug 09 05:15:09 PM PDT 24
Finished Aug 09 05:15:11 PM PDT 24
Peak memory 201056 kb
Host smart-aef7e101-ddad-4be6-a6e1-2a5a4b633e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108494440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.4108494440
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1710189621
Short name T633
Test name
Test status
Simulation time 2088702434 ps
CPU time 1.42 seconds
Started Aug 09 05:15:18 PM PDT 24
Finished Aug 09 05:15:20 PM PDT 24
Peak memory 200704 kb
Host smart-ff73ff16-6370-4b98-a039-1f7325e9d2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710189621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.1710189621
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2725985244
Short name T539
Test name
Test status
Simulation time 2534941520 ps
CPU time 2.39 seconds
Started Aug 09 05:15:19 PM PDT 24
Finished Aug 09 05:15:22 PM PDT 24
Peak memory 200692 kb
Host smart-ab1b3bab-e756-4a64-bdd5-05c7678d6c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725985244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.2725985244
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.2267180014
Short name T179
Test name
Test status
Simulation time 2116549957 ps
CPU time 4.25 seconds
Started Aug 09 05:15:13 PM PDT 24
Finished Aug 09 05:15:17 PM PDT 24
Peak memory 200692 kb
Host smart-1a81215a-138d-4112-8eb6-c764eda98cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267180014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.2267180014
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.2656734498
Short name T722
Test name
Test status
Simulation time 7193940898 ps
CPU time 4.71 seconds
Started Aug 09 05:15:21 PM PDT 24
Finished Aug 09 05:15:25 PM PDT 24
Peak memory 200876 kb
Host smart-5c605bf7-8809-4992-a0ae-951b72100afd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656734498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.2656734498
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.4096690057
Short name T741
Test name
Test status
Simulation time 4098779406 ps
CPU time 0.92 seconds
Started Aug 09 05:15:20 PM PDT 24
Finished Aug 09 05:15:21 PM PDT 24
Peak memory 200828 kb
Host smart-912f3d40-c53e-4854-bf91-14e28b0cbb48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096690057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.4096690057
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.1502401399
Short name T466
Test name
Test status
Simulation time 2027193979 ps
CPU time 2 seconds
Started Aug 09 05:12:55 PM PDT 24
Finished Aug 09 05:12:57 PM PDT 24
Peak memory 200764 kb
Host smart-b25a7d13-62a7-460f-9c29-7695ee2760b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502401399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.1502401399
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1683801704
Short name T88
Test name
Test status
Simulation time 3732075223 ps
CPU time 2.99 seconds
Started Aug 09 05:12:55 PM PDT 24
Finished Aug 09 05:12:58 PM PDT 24
Peak memory 200784 kb
Host smart-6b52520f-61a1-4c47-8a3d-62cab9d889ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683801704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.1683801704
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1513081769
Short name T273
Test name
Test status
Simulation time 37167252883 ps
CPU time 6.74 seconds
Started Aug 09 05:12:55 PM PDT 24
Finished Aug 09 05:13:01 PM PDT 24
Peak memory 201048 kb
Host smart-4a2ed9d2-3f0a-4279-8688-ad7fb7086c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513081769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.1513081769
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1135735644
Short name T89
Test name
Test status
Simulation time 4269058623 ps
CPU time 2.58 seconds
Started Aug 09 05:12:54 PM PDT 24
Finished Aug 09 05:12:57 PM PDT 24
Peak memory 200680 kb
Host smart-becc577e-3ab6-4aa4-9460-cfab90d14864
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135735644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.1135735644
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.3225717814
Short name T720
Test name
Test status
Simulation time 4795592748 ps
CPU time 2.41 seconds
Started Aug 09 05:12:54 PM PDT 24
Finished Aug 09 05:12:57 PM PDT 24
Peak memory 200816 kb
Host smart-04c571d3-4455-48ca-b76e-2817f2677dd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225717814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.3225717814
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2019710854
Short name T544
Test name
Test status
Simulation time 2612826942 ps
CPU time 6.53 seconds
Started Aug 09 05:12:54 PM PDT 24
Finished Aug 09 05:13:01 PM PDT 24
Peak memory 200828 kb
Host smart-8ce34675-9428-4b97-a026-59e98f362c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019710854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.2019710854
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.353289124
Short name T538
Test name
Test status
Simulation time 2465371293 ps
CPU time 2.16 seconds
Started Aug 09 05:12:56 PM PDT 24
Finished Aug 09 05:12:58 PM PDT 24
Peak memory 200676 kb
Host smart-4d5fb8ec-ed4e-4fa0-b838-a8fddd4f47a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353289124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.353289124
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.2039870030
Short name T509
Test name
Test status
Simulation time 2098831103 ps
CPU time 6.31 seconds
Started Aug 09 05:12:54 PM PDT 24
Finished Aug 09 05:13:00 PM PDT 24
Peak memory 200652 kb
Host smart-7da41167-3372-42e5-90d4-0de8c4a27e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039870030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.2039870030
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3167609238
Short name T754
Test name
Test status
Simulation time 2521455976 ps
CPU time 3.26 seconds
Started Aug 09 05:12:55 PM PDT 24
Finished Aug 09 05:12:58 PM PDT 24
Peak memory 200764 kb
Host smart-ad5c929c-1988-4724-ab78-a41a6e4dd87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167609238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.3167609238
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.2524461154
Short name T300
Test name
Test status
Simulation time 2131054767 ps
CPU time 1.86 seconds
Started Aug 09 05:12:57 PM PDT 24
Finished Aug 09 05:12:59 PM PDT 24
Peak memory 200648 kb
Host smart-29a1061e-1125-42f1-b41a-74832bf4160f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524461154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.2524461154
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1291190371
Short name T71
Test name
Test status
Simulation time 25213253444 ps
CPU time 50.28 seconds
Started Aug 09 05:12:57 PM PDT 24
Finished Aug 09 05:13:47 PM PDT 24
Peak memory 210544 kb
Host smart-90fab0fe-233d-4bf7-988a-1f72dff72ebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291190371 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.1291190371
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1578211054
Short name T116
Test name
Test status
Simulation time 2767643492 ps
CPU time 6.57 seconds
Started Aug 09 05:12:54 PM PDT 24
Finished Aug 09 05:13:01 PM PDT 24
Peak memory 200864 kb
Host smart-687cf4ae-66ba-44e0-bee5-5f5cd64f8ff4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578211054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.1578211054
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.658462196
Short name T647
Test name
Test status
Simulation time 26078590854 ps
CPU time 67.5 seconds
Started Aug 09 05:15:18 PM PDT 24
Finished Aug 09 05:16:26 PM PDT 24
Peak memory 201172 kb
Host smart-f2e93a99-464c-4c9c-a90f-68ee6d42cb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658462196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_wi
th_pre_cond.658462196
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3686542425
Short name T356
Test name
Test status
Simulation time 45193835682 ps
CPU time 119.72 seconds
Started Aug 09 05:15:21 PM PDT 24
Finished Aug 09 05:17:21 PM PDT 24
Peak memory 201116 kb
Host smart-0f37c7d1-0c8b-420f-9ddb-5de5373c5dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686542425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.3686542425
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2608215201
Short name T656
Test name
Test status
Simulation time 29090170604 ps
CPU time 36.76 seconds
Started Aug 09 05:15:18 PM PDT 24
Finished Aug 09 05:15:55 PM PDT 24
Peak memory 201076 kb
Host smart-bb76c274-7d61-4f8b-a71e-d3d89d4b658e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608215201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_w
ith_pre_cond.2608215201
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1289667888
Short name T274
Test name
Test status
Simulation time 40581409218 ps
CPU time 9.3 seconds
Started Aug 09 05:15:18 PM PDT 24
Finished Aug 09 05:15:28 PM PDT 24
Peak memory 201108 kb
Host smart-fa3a890a-5f0e-4de7-9716-d8e7a2904ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289667888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_w
ith_pre_cond.1289667888
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.897870415
Short name T660
Test name
Test status
Simulation time 160275059914 ps
CPU time 104.91 seconds
Started Aug 09 05:15:19 PM PDT 24
Finished Aug 09 05:17:05 PM PDT 24
Peak memory 201152 kb
Host smart-82852872-544f-4f10-9967-1e50a1e280e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897870415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_wi
th_pre_cond.897870415
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.2015298530
Short name T108
Test name
Test status
Simulation time 2020828605 ps
CPU time 2.99 seconds
Started Aug 09 05:12:54 PM PDT 24
Finished Aug 09 05:12:57 PM PDT 24
Peak memory 200812 kb
Host smart-efe1908b-4eb6-4400-8346-5bafa18fd157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015298530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes
t.2015298530
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3788222430
Short name T752
Test name
Test status
Simulation time 3727232567 ps
CPU time 9.32 seconds
Started Aug 09 05:12:56 PM PDT 24
Finished Aug 09 05:13:05 PM PDT 24
Peak memory 200860 kb
Host smart-c1bc1f85-dc79-4891-8681-948de5d2ddcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788222430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.3788222430
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.3195037526
Short name T383
Test name
Test status
Simulation time 73472817191 ps
CPU time 184.75 seconds
Started Aug 09 05:12:54 PM PDT 24
Finished Aug 09 05:15:59 PM PDT 24
Peak memory 201028 kb
Host smart-a7faeef7-052d-42ce-a410-0b6c6885f61d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195037526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.3195037526
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1045749051
Short name T669
Test name
Test status
Simulation time 26342862558 ps
CPU time 16.95 seconds
Started Aug 09 05:12:55 PM PDT 24
Finished Aug 09 05:13:12 PM PDT 24
Peak memory 201068 kb
Host smart-9d0b9e1f-4750-478c-91be-44b16dfb68de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045749051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wi
th_pre_cond.1045749051
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2334125407
Short name T419
Test name
Test status
Simulation time 2828192965 ps
CPU time 2.49 seconds
Started Aug 09 05:12:57 PM PDT 24
Finished Aug 09 05:13:00 PM PDT 24
Peak memory 200824 kb
Host smart-e983eb29-4caf-45f7-be25-a885d8955ff3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334125407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.2334125407
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.2574820197
Short name T243
Test name
Test status
Simulation time 3340027406 ps
CPU time 2.47 seconds
Started Aug 09 05:12:59 PM PDT 24
Finished Aug 09 05:13:02 PM PDT 24
Peak memory 200880 kb
Host smart-1ee75b67-1fcd-44f1-91c8-db3aa492fe10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574820197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_edge_detect.2574820197
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2051701906
Short name T486
Test name
Test status
Simulation time 2664556036 ps
CPU time 1.44 seconds
Started Aug 09 05:12:56 PM PDT 24
Finished Aug 09 05:12:57 PM PDT 24
Peak memory 201056 kb
Host smart-5f210056-7312-4648-a4a1-398bcc88a6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051701906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.2051701906
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.3209558065
Short name T697
Test name
Test status
Simulation time 2454721972 ps
CPU time 6.35 seconds
Started Aug 09 05:12:53 PM PDT 24
Finished Aug 09 05:13:00 PM PDT 24
Peak memory 200800 kb
Host smart-b95ae62e-ab95-48c8-a0b9-8df60cd7dd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209558065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.3209558065
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1056251154
Short name T225
Test name
Test status
Simulation time 2213095654 ps
CPU time 5.68 seconds
Started Aug 09 05:12:55 PM PDT 24
Finished Aug 09 05:13:00 PM PDT 24
Peak memory 200696 kb
Host smart-7f5584b0-1f2b-4ea9-b73a-74ce2071d037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056251154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.1056251154
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.731829541
Short name T46
Test name
Test status
Simulation time 2510906366 ps
CPU time 7.35 seconds
Started Aug 09 05:12:54 PM PDT 24
Finished Aug 09 05:13:02 PM PDT 24
Peak memory 200804 kb
Host smart-293bc37a-aede-4cbe-a85c-9ac9a7736bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731829541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.731829541
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.2856258229
Short name T444
Test name
Test status
Simulation time 2112051370 ps
CPU time 6.01 seconds
Started Aug 09 05:12:55 PM PDT 24
Finished Aug 09 05:13:01 PM PDT 24
Peak memory 200696 kb
Host smart-5cd42785-86a0-44a8-8a49-9534902136d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856258229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.2856258229
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.1351757263
Short name T136
Test name
Test status
Simulation time 13045385809 ps
CPU time 18.45 seconds
Started Aug 09 05:12:54 PM PDT 24
Finished Aug 09 05:13:13 PM PDT 24
Peak memory 200784 kb
Host smart-b325a256-c907-4ab6-bb66-f7890ec3774c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351757263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.1351757263
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2440006572
Short name T201
Test name
Test status
Simulation time 37653407782 ps
CPU time 11.56 seconds
Started Aug 09 05:12:54 PM PDT 24
Finished Aug 09 05:13:06 PM PDT 24
Peak memory 201136 kb
Host smart-17439e1e-a4ba-49eb-bcd7-029106c7ba00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440006572 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.2440006572
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1867853059
Short name T267
Test name
Test status
Simulation time 65612044477 ps
CPU time 85.54 seconds
Started Aug 09 05:15:22 PM PDT 24
Finished Aug 09 05:16:47 PM PDT 24
Peak memory 201008 kb
Host smart-ad607dae-c64e-4d00-b206-5ffc66262a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867853059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w
ith_pre_cond.1867853059
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2305561358
Short name T699
Test name
Test status
Simulation time 24833631088 ps
CPU time 59.31 seconds
Started Aug 09 05:15:19 PM PDT 24
Finished Aug 09 05:16:19 PM PDT 24
Peak memory 201080 kb
Host smart-f5f548ab-5a06-492d-8cbb-f75d94c37711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305561358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.2305561358
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3296336296
Short name T98
Test name
Test status
Simulation time 30018561135 ps
CPU time 9.77 seconds
Started Aug 09 05:15:19 PM PDT 24
Finished Aug 09 05:15:29 PM PDT 24
Peak memory 201096 kb
Host smart-dc53f393-76c4-4342-9e32-7550e87bfe9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296336296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.3296336296
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3643308183
Short name T215
Test name
Test status
Simulation time 84146930927 ps
CPU time 195.27 seconds
Started Aug 09 05:15:20 PM PDT 24
Finished Aug 09 05:18:35 PM PDT 24
Peak memory 201008 kb
Host smart-4f79a9c7-a203-48ed-a122-80781dac588c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643308183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.3643308183
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3750641747
Short name T371
Test name
Test status
Simulation time 110149383507 ps
CPU time 36.12 seconds
Started Aug 09 05:15:19 PM PDT 24
Finished Aug 09 05:15:56 PM PDT 24
Peak memory 201060 kb
Host smart-9a222f38-005e-4567-acf3-5d5749060a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750641747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.3750641747
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1721402100
Short name T607
Test name
Test status
Simulation time 116170730995 ps
CPU time 316.85 seconds
Started Aug 09 05:15:20 PM PDT 24
Finished Aug 09 05:20:37 PM PDT 24
Peak memory 201184 kb
Host smart-9e99ed6d-39fb-4419-bbf3-8dec169865dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721402100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_w
ith_pre_cond.1721402100
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.412069071
Short name T377
Test name
Test status
Simulation time 109122951582 ps
CPU time 140.6 seconds
Started Aug 09 05:15:21 PM PDT 24
Finished Aug 09 05:17:41 PM PDT 24
Peak memory 201080 kb
Host smart-7f8c353d-cda3-44dd-8890-3f429751d2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412069071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_wi
th_pre_cond.412069071
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3648628541
Short name T553
Test name
Test status
Simulation time 112386208778 ps
CPU time 74.17 seconds
Started Aug 09 05:15:18 PM PDT 24
Finished Aug 09 05:16:32 PM PDT 24
Peak memory 201088 kb
Host smart-2df11f41-b2a8-411c-966e-f9b44a9521c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648628541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.3648628541
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3019108615
Short name T220
Test name
Test status
Simulation time 77527054907 ps
CPU time 206.23 seconds
Started Aug 09 05:15:20 PM PDT 24
Finished Aug 09 05:18:46 PM PDT 24
Peak memory 201124 kb
Host smart-9bcb9449-4110-4530-be63-75f69f2b0be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019108615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.3019108615
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.2680735402
Short name T657
Test name
Test status
Simulation time 2119191701 ps
CPU time 1.04 seconds
Started Aug 09 05:13:02 PM PDT 24
Finished Aug 09 05:13:03 PM PDT 24
Peak memory 200724 kb
Host smart-a2019e48-3d3e-4e63-b07c-6897c414723c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680735402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.2680735402
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.744598389
Short name T157
Test name
Test status
Simulation time 3868151911 ps
CPU time 8.91 seconds
Started Aug 09 05:13:04 PM PDT 24
Finished Aug 09 05:13:13 PM PDT 24
Peak memory 200884 kb
Host smart-3b6465a6-05b6-4835-810b-f694a37525e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744598389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.744598389
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.4144706901
Short name T344
Test name
Test status
Simulation time 103383094773 ps
CPU time 250.31 seconds
Started Aug 09 05:13:03 PM PDT 24
Finished Aug 09 05:17:14 PM PDT 24
Peak memory 201060 kb
Host smart-48e932e6-645c-43dd-991c-b78f61ca743b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144706901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.4144706901
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2576407688
Short name T237
Test name
Test status
Simulation time 64317800956 ps
CPU time 88.12 seconds
Started Aug 09 05:13:00 PM PDT 24
Finished Aug 09 05:14:28 PM PDT 24
Peak memory 201052 kb
Host smart-c6204b4d-c2ef-47fd-b472-68ea7b4465e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576407688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wi
th_pre_cond.2576407688
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2841234466
Short name T529
Test name
Test status
Simulation time 3173424676 ps
CPU time 9.26 seconds
Started Aug 09 05:13:02 PM PDT 24
Finished Aug 09 05:13:11 PM PDT 24
Peak memory 200752 kb
Host smart-a73b0e7b-e64d-4227-9821-b71ea06f2e95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841234466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ec_pwr_on_rst.2841234466
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.755035945
Short name T147
Test name
Test status
Simulation time 5172637749 ps
CPU time 4.11 seconds
Started Aug 09 05:13:01 PM PDT 24
Finished Aug 09 05:13:05 PM PDT 24
Peak memory 200852 kb
Host smart-7efd2635-91fa-461b-ae3e-5c1126844a37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755035945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl
_edge_detect.755035945
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2916134982
Short name T415
Test name
Test status
Simulation time 2629057641 ps
CPU time 2.26 seconds
Started Aug 09 05:13:04 PM PDT 24
Finished Aug 09 05:13:06 PM PDT 24
Peak memory 200764 kb
Host smart-07524e9d-7b16-4ec1-bc3c-1ed5f03d384d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916134982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.2916134982
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.3294314897
Short name T57
Test name
Test status
Simulation time 2476237182 ps
CPU time 4.06 seconds
Started Aug 09 05:13:00 PM PDT 24
Finished Aug 09 05:13:04 PM PDT 24
Peak memory 200672 kb
Host smart-aefd4d1f-7cc2-4783-a267-4ee669de31ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294314897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.3294314897
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1263468217
Short name T109
Test name
Test status
Simulation time 2215416945 ps
CPU time 1.88 seconds
Started Aug 09 05:13:00 PM PDT 24
Finished Aug 09 05:13:02 PM PDT 24
Peak memory 200720 kb
Host smart-b059ee57-be2f-4139-9276-38e81fb66ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263468217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.1263468217
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.3659018514
Short name T307
Test name
Test status
Simulation time 2547362387 ps
CPU time 1.77 seconds
Started Aug 09 05:13:01 PM PDT 24
Finished Aug 09 05:13:03 PM PDT 24
Peak memory 200720 kb
Host smart-98bfa1a0-07d7-469a-97f4-5e65681fffde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659018514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.3659018514
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.2850599172
Short name T757
Test name
Test status
Simulation time 2169138879 ps
CPU time 1.28 seconds
Started Aug 09 05:12:55 PM PDT 24
Finished Aug 09 05:12:56 PM PDT 24
Peak memory 200772 kb
Host smart-09646ed5-3147-41fd-864e-86a8ea1b9db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850599172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.2850599172
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.793903769
Short name T2
Test name
Test status
Simulation time 12547669982 ps
CPU time 14.8 seconds
Started Aug 09 05:13:02 PM PDT 24
Finished Aug 09 05:13:17 PM PDT 24
Peak memory 200852 kb
Host smart-cb4f29cb-38cc-4cb0-8846-a247512052b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793903769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_str
ess_all.793903769
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1733843168
Short name T118
Test name
Test status
Simulation time 1698192838216 ps
CPU time 319.59 seconds
Started Aug 09 05:13:02 PM PDT 24
Finished Aug 09 05:18:22 PM PDT 24
Peak memory 209320 kb
Host smart-3b6e1648-7e64-4361-b183-a3995352bcb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733843168 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.1733843168
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2402585930
Short name T360
Test name
Test status
Simulation time 71942669425 ps
CPU time 93.04 seconds
Started Aug 09 05:15:18 PM PDT 24
Finished Aug 09 05:16:51 PM PDT 24
Peak memory 201036 kb
Host smart-eee43cd9-35ae-4de6-b3de-5bb57d962eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402585930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.2402585930
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1127866477
Short name T187
Test name
Test status
Simulation time 44210020636 ps
CPU time 55.74 seconds
Started Aug 09 05:15:19 PM PDT 24
Finished Aug 09 05:16:15 PM PDT 24
Peak memory 201008 kb
Host smart-677e01fd-ba3c-4f00-9953-12e9b77c6166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127866477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.1127866477
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2094707204
Short name T221
Test name
Test status
Simulation time 67405194985 ps
CPU time 21.32 seconds
Started Aug 09 05:15:22 PM PDT 24
Finished Aug 09 05:15:43 PM PDT 24
Peak memory 201128 kb
Host smart-e5a94c45-79e7-41d4-9de6-1d05eb54a5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094707204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.2094707204
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.2459015443
Short name T227
Test name
Test status
Simulation time 60198070566 ps
CPU time 72.53 seconds
Started Aug 09 05:15:19 PM PDT 24
Finished Aug 09 05:16:33 PM PDT 24
Peak memory 201052 kb
Host smart-7340f897-3315-4af5-b441-68843b693a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459015443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.2459015443
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.3597995662
Short name T14
Test name
Test status
Simulation time 44657859121 ps
CPU time 59.29 seconds
Started Aug 09 05:15:21 PM PDT 24
Finished Aug 09 05:16:21 PM PDT 24
Peak memory 201200 kb
Host smart-1bdf63bf-1978-4722-9383-e4c74ed622a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597995662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.3597995662
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.2410432931
Short name T85
Test name
Test status
Simulation time 2015253417 ps
CPU time 5.74 seconds
Started Aug 09 05:13:02 PM PDT 24
Finished Aug 09 05:13:08 PM PDT 24
Peak memory 200716 kb
Host smart-5be2f50d-01ba-4605-891c-e26aea4c64cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410432931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.2410432931
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2211047630
Short name T295
Test name
Test status
Simulation time 3508066653 ps
CPU time 9.76 seconds
Started Aug 09 05:13:02 PM PDT 24
Finished Aug 09 05:13:12 PM PDT 24
Peak memory 200812 kb
Host smart-c837abdf-19e7-48d9-98c7-1f644d02f3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211047630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.2211047630
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.1890696564
Short name T335
Test name
Test status
Simulation time 144812706520 ps
CPU time 394.36 seconds
Started Aug 09 05:13:01 PM PDT 24
Finished Aug 09 05:19:35 PM PDT 24
Peak memory 200992 kb
Host smart-dfb770f5-b88f-425c-8c6b-99cbe8678e52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890696564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.1890696564
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2151667310
Short name T721
Test name
Test status
Simulation time 67332980768 ps
CPU time 43.73 seconds
Started Aug 09 05:13:01 PM PDT 24
Finished Aug 09 05:13:45 PM PDT 24
Peak memory 201008 kb
Host smart-50207983-bb4f-47fb-b6d3-8bcb9512f162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151667310 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wi
th_pre_cond.2151667310
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.890923210
Short name T452
Test name
Test status
Simulation time 3663601602 ps
CPU time 1.43 seconds
Started Aug 09 05:13:02 PM PDT 24
Finished Aug 09 05:13:03 PM PDT 24
Peak memory 200748 kb
Host smart-23637942-4fdf-4002-93bd-2d249f8b11d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890923210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_ec_pwr_on_rst.890923210
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.1446826851
Short name T132
Test name
Test status
Simulation time 4097316566 ps
CPU time 5.61 seconds
Started Aug 09 05:13:02 PM PDT 24
Finished Aug 09 05:13:07 PM PDT 24
Peak memory 200852 kb
Host smart-63bdbf24-cd0b-402f-b8d1-09ef04caf7b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446826851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.1446826851
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3004305868
Short name T570
Test name
Test status
Simulation time 2609603873 ps
CPU time 6.76 seconds
Started Aug 09 05:13:02 PM PDT 24
Finished Aug 09 05:13:09 PM PDT 24
Peak memory 201056 kb
Host smart-d03e9c60-0871-46f1-ae8c-a1d345a7be78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004305868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.3004305868
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1851986738
Short name T706
Test name
Test status
Simulation time 2474316999 ps
CPU time 2.47 seconds
Started Aug 09 05:13:02 PM PDT 24
Finished Aug 09 05:13:05 PM PDT 24
Peak memory 200764 kb
Host smart-5d49c68c-49df-47d6-8b6a-7fd7970b3971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851986738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.1851986738
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.700400655
Short name T572
Test name
Test status
Simulation time 2217812560 ps
CPU time 2.03 seconds
Started Aug 09 05:13:01 PM PDT 24
Finished Aug 09 05:13:03 PM PDT 24
Peak memory 200644 kb
Host smart-bf6f0bd0-4bba-467f-87b3-a2e190d3d407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700400655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.700400655
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.763730939
Short name T390
Test name
Test status
Simulation time 2520948569 ps
CPU time 3.98 seconds
Started Aug 09 05:13:04 PM PDT 24
Finished Aug 09 05:13:08 PM PDT 24
Peak memory 200736 kb
Host smart-8ba43b68-8b52-49d3-9ca2-8c722bcad257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763730939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.763730939
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.3735658555
Short name T396
Test name
Test status
Simulation time 2134759561 ps
CPU time 1.93 seconds
Started Aug 09 05:13:04 PM PDT 24
Finished Aug 09 05:13:06 PM PDT 24
Peak memory 200740 kb
Host smart-18523241-b8af-4a95-b590-7571d4dcc0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735658555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.3735658555
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.515972883
Short name T43
Test name
Test status
Simulation time 8127231893 ps
CPU time 11.44 seconds
Started Aug 09 05:13:04 PM PDT 24
Finished Aug 09 05:13:15 PM PDT 24
Peak memory 200788 kb
Host smart-6c558045-bb88-465f-800c-f12f0c209678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515972883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_str
ess_all.515972883
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1754142958
Short name T296
Test name
Test status
Simulation time 183513294503 ps
CPU time 123.31 seconds
Started Aug 09 05:13:03 PM PDT 24
Finished Aug 09 05:15:07 PM PDT 24
Peak memory 200988 kb
Host smart-ef9fd102-4430-47a9-857e-9e22c71d92dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754142958 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.1754142958
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1850638773
Short name T69
Test name
Test status
Simulation time 5963543862 ps
CPU time 5.62 seconds
Started Aug 09 05:13:03 PM PDT 24
Finished Aug 09 05:13:08 PM PDT 24
Peak memory 200780 kb
Host smart-ff0d18f9-7b5d-4ac2-91c7-9474f8927bb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850638773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.1850638773
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2804890831
Short name T715
Test name
Test status
Simulation time 39404378739 ps
CPU time 99.75 seconds
Started Aug 09 05:15:31 PM PDT 24
Finished Aug 09 05:17:11 PM PDT 24
Peak memory 201032 kb
Host smart-9df0e1dd-6fd3-4c92-92f7-8fd1ac2cac4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804890831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.2804890831
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1892506949
Short name T594
Test name
Test status
Simulation time 68288089581 ps
CPU time 24.62 seconds
Started Aug 09 05:15:29 PM PDT 24
Finished Aug 09 05:15:54 PM PDT 24
Peak memory 201108 kb
Host smart-f8c5fcbd-005b-4b55-a6f6-c97ac7cf823c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892506949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w
ith_pre_cond.1892506949
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3997983544
Short name T78
Test name
Test status
Simulation time 206326020286 ps
CPU time 544.89 seconds
Started Aug 09 05:15:28 PM PDT 24
Finished Aug 09 05:24:33 PM PDT 24
Peak memory 201108 kb
Host smart-e4e0cdb3-cd99-4b7c-98ab-dfe59e0e1abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997983544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w
ith_pre_cond.3997983544
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.255525347
Short name T591
Test name
Test status
Simulation time 78937127516 ps
CPU time 52.99 seconds
Started Aug 09 05:15:24 PM PDT 24
Finished Aug 09 05:16:17 PM PDT 24
Peak memory 201076 kb
Host smart-e580bc91-29f4-4b21-9b08-f16687ec8f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255525347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_wi
th_pre_cond.255525347
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3327759408
Short name T97
Test name
Test status
Simulation time 44089457241 ps
CPU time 61.3 seconds
Started Aug 09 05:15:29 PM PDT 24
Finished Aug 09 05:16:30 PM PDT 24
Peak memory 201104 kb
Host smart-6daa79e3-f17c-419d-9f9a-a8405ed1c111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327759408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.3327759408
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.53697629
Short name T94
Test name
Test status
Simulation time 25859242035 ps
CPU time 18.26 seconds
Started Aug 09 05:15:28 PM PDT 24
Finished Aug 09 05:15:46 PM PDT 24
Peak memory 201004 kb
Host smart-604307eb-b5f8-4629-9da6-cc9e921bab06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53697629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_wit
h_pre_cond.53697629
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3205613698
Short name T76
Test name
Test status
Simulation time 47930482234 ps
CPU time 61.54 seconds
Started Aug 09 05:15:31 PM PDT 24
Finished Aug 09 05:16:33 PM PDT 24
Peak memory 201408 kb
Host smart-aeacf1e6-2f3d-4481-9326-b97e8b364b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205613698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.3205613698
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.1030591748
Short name T515
Test name
Test status
Simulation time 2090056109 ps
CPU time 1 seconds
Started Aug 09 05:13:01 PM PDT 24
Finished Aug 09 05:13:02 PM PDT 24
Peak memory 200816 kb
Host smart-696309b4-4fe5-4572-9a6d-535816f3073c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030591748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.1030591748
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2004414751
Short name T405
Test name
Test status
Simulation time 3501912474 ps
CPU time 2.12 seconds
Started Aug 09 05:13:01 PM PDT 24
Finished Aug 09 05:13:03 PM PDT 24
Peak memory 200828 kb
Host smart-5cf91523-ced3-4987-adf9-5a4c131c9525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004414751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.2004414751
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.2781109321
Short name T337
Test name
Test status
Simulation time 139303090288 ps
CPU time 352.62 seconds
Started Aug 09 05:13:02 PM PDT 24
Finished Aug 09 05:18:55 PM PDT 24
Peak memory 201076 kb
Host smart-525a8217-4667-481b-83e9-d95e60c02003
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781109321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.2781109321
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3624789105
Short name T555
Test name
Test status
Simulation time 27080671723 ps
CPU time 64.36 seconds
Started Aug 09 05:13:04 PM PDT 24
Finished Aug 09 05:14:09 PM PDT 24
Peak memory 201004 kb
Host smart-7621a05e-547a-4f11-a93a-441e0ba6b0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624789105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.3624789105
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1150860490
Short name T408
Test name
Test status
Simulation time 2946422927 ps
CPU time 8.1 seconds
Started Aug 09 05:13:05 PM PDT 24
Finished Aug 09 05:13:13 PM PDT 24
Peak memory 200820 kb
Host smart-d26be1f1-36d6-449d-93b6-3411c1eeb405
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150860490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.1150860490
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.2825042380
Short name T195
Test name
Test status
Simulation time 2973974532 ps
CPU time 1.48 seconds
Started Aug 09 05:13:03 PM PDT 24
Finished Aug 09 05:13:05 PM PDT 24
Peak memory 200896 kb
Host smart-7d4868f3-b1cd-4021-a5ee-31989a0270c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825042380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.2825042380
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.205279128
Short name T450
Test name
Test status
Simulation time 2629041783 ps
CPU time 2.06 seconds
Started Aug 09 05:13:03 PM PDT 24
Finished Aug 09 05:13:05 PM PDT 24
Peak memory 200772 kb
Host smart-49efb780-d372-42e2-bc64-542ed22219c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205279128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.205279128
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.2129496709
Short name T700
Test name
Test status
Simulation time 2460611485 ps
CPU time 6.27 seconds
Started Aug 09 05:13:03 PM PDT 24
Finished Aug 09 05:13:09 PM PDT 24
Peak memory 200824 kb
Host smart-99c51b37-83e1-490d-a2c5-03e40e810516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129496709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.2129496709
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.230570264
Short name T608
Test name
Test status
Simulation time 2222788560 ps
CPU time 5.76 seconds
Started Aug 09 05:13:02 PM PDT 24
Finished Aug 09 05:13:08 PM PDT 24
Peak memory 200768 kb
Host smart-003f5d0a-cc50-466a-8b23-dd036824f025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230570264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.230570264
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3793097197
Short name T445
Test name
Test status
Simulation time 2508917216 ps
CPU time 6.67 seconds
Started Aug 09 05:13:02 PM PDT 24
Finished Aug 09 05:13:09 PM PDT 24
Peak memory 200704 kb
Host smart-cae7febf-6817-4a4d-87a1-eac70fbd4774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793097197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.3793097197
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.3937338478
Short name T310
Test name
Test status
Simulation time 2110367631 ps
CPU time 5.4 seconds
Started Aug 09 05:13:03 PM PDT 24
Finished Aug 09 05:13:09 PM PDT 24
Peak memory 200740 kb
Host smart-d0d342d3-fbad-4e56-bdf2-62936718fd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937338478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.3937338478
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.1433132949
Short name T217
Test name
Test status
Simulation time 8257997820 ps
CPU time 10.62 seconds
Started Aug 09 05:13:01 PM PDT 24
Finished Aug 09 05:13:12 PM PDT 24
Peak memory 200888 kb
Host smart-860ffe0c-6647-4d7f-878d-8fc743ec7b20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433132949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.1433132949
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.303320243
Short name T727
Test name
Test status
Simulation time 74954610684 ps
CPU time 173.59 seconds
Started Aug 09 05:13:02 PM PDT 24
Finished Aug 09 05:15:56 PM PDT 24
Peak memory 209476 kb
Host smart-2538684c-f8f1-4b17-9fc6-1758a9f4b85b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303320243 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.303320243
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.4191457604
Short name T130
Test name
Test status
Simulation time 3419986954 ps
CPU time 2.26 seconds
Started Aug 09 05:13:02 PM PDT 24
Finished Aug 09 05:13:05 PM PDT 24
Peak memory 200868 kb
Host smart-f449c91e-7011-404e-a43a-6b1ae590872c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191457604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ultra_low_pwr.4191457604
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1976468362
Short name T65
Test name
Test status
Simulation time 23112715395 ps
CPU time 15.52 seconds
Started Aug 09 05:15:27 PM PDT 24
Finished Aug 09 05:15:43 PM PDT 24
Peak memory 201076 kb
Host smart-2f43a563-1cdc-4dd5-b8e5-b95f2737e0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976468362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.1976468362
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3014225426
Short name T169
Test name
Test status
Simulation time 29661228830 ps
CPU time 20.27 seconds
Started Aug 09 05:15:30 PM PDT 24
Finished Aug 09 05:15:50 PM PDT 24
Peak memory 201008 kb
Host smart-a4178cb4-ed1a-4346-85cb-3423cf358578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014225426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.3014225426
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1573422884
Short name T164
Test name
Test status
Simulation time 41356268050 ps
CPU time 57.03 seconds
Started Aug 09 05:15:27 PM PDT 24
Finished Aug 09 05:16:25 PM PDT 24
Peak memory 201028 kb
Host smart-96f9d824-297c-41e5-8ed8-c3786924594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573422884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_w
ith_pre_cond.1573422884
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1011888848
Short name T357
Test name
Test status
Simulation time 132975078686 ps
CPU time 358.21 seconds
Started Aug 09 05:15:30 PM PDT 24
Finished Aug 09 05:21:28 PM PDT 24
Peak memory 201096 kb
Host smart-43e94014-cfe3-44a4-a493-052d56450506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011888848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.1011888848
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.1747118285
Short name T95
Test name
Test status
Simulation time 25332756693 ps
CPU time 66.63 seconds
Started Aug 09 05:15:27 PM PDT 24
Finished Aug 09 05:16:34 PM PDT 24
Peak memory 201004 kb
Host smart-3d74ac0b-1eb4-4778-8b2c-d6d4a906df83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747118285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w
ith_pre_cond.1747118285
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3380906166
Short name T385
Test name
Test status
Simulation time 117417492272 ps
CPU time 274.86 seconds
Started Aug 09 05:15:27 PM PDT 24
Finished Aug 09 05:20:02 PM PDT 24
Peak memory 201408 kb
Host smart-e00bf662-62f4-4e45-aa0b-6b2abb730bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380906166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.3380906166
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2001578074
Short name T348
Test name
Test status
Simulation time 111066489184 ps
CPU time 135.49 seconds
Started Aug 09 05:15:26 PM PDT 24
Finished Aug 09 05:17:41 PM PDT 24
Peak memory 201016 kb
Host smart-9bbcb88f-8476-45b4-a1a9-855d581a7233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001578074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.2001578074
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest
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