| | | | | | |
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.aDataKnown_M
| 0 | 0 | 1161875389 | 1935746 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A
| 0 | 0 | 1161874828 | 5049 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.contigMask_M
| 0 | 0 | 1161875389 | 12762395 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.dDataKnown_A
| 0 | 0 | 1161875389 | 197182 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A
| 0 | 0 | 1161874828 | 5198 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAParam_M
| 0 | 0 | 1161875389 | 14525309 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalDParam_A
| 0 | 0 | 1161875389 | 571983 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M
| 0 | 0 | 1161875389 | 14525309 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A
| 0 | 0 | 1161875389 | 571983 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respOpcode_A
| 0 | 0 | 1161875389 | 571983 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A
| 0 | 0 | 1161875389 | 571983 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A
| 0 | 0 | 1161874828 | 3159 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A
| 0 | 0 | 1161874828 | 3148 | 0 | 0 |
|
tb.dut.tlul_assert_device.p_dbw.TlDbw_A
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.u_reg.en2addrHit
| 0 | 0 | 1161874828 | 269884 | 0 | 0 |
|
tb.dut.u_reg.reAfterRv
| 0 | 0 | 1161874828 | 269884 | 0 | 0 |
|
tb.dut.u_reg.rePulse
| 0 | 0 | 1161874828 | 141820 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1334900 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1482 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1482 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1482 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1430 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1489 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1163130 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1254 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1254 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1254 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1199 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1259 | 0 | 0 |
|
tb.dut.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1852359 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1950 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1950 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1950 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1892 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1956 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1750339 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1846 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1846 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1846 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1788 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1852 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1792708 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1877 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1877 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1877 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1822 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1884 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1750716 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1861 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1861 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1861 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1809 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1867 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1812891 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1942 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1942 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1942 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1887 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1949 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1751825 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1867 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1867 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1867 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1810 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1873 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1751474 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1886 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1886 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1886 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1831 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1893 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1740888 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1851 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1851 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1851 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1797 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1859 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1193508 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1278 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1278 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1278 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1225 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1286 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1161445 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1270 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1270 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1270 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1216 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1276 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1170067 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1292 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1292 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1292 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1238 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1296 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1131186 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1236 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1236 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1236 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1179 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1246 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 5531955 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 7114 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 7114 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 7114 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 7059 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 7122 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 5435269 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 7085 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 7085 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 7085 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 7027 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 7091 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 5451454 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 7108 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 7108 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 7108 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 7049 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 7115 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 5365514 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 7124 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 7124 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 7124 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 7063 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 7131 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 6264438 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 7813 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 7813 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 7813 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 7756 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 7820 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 6091056 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 7674 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 7674 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 7674 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 7617 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 7682 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 6071587 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 7700 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 7700 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 7700 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 7641 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 7706 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 6025016 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 7733 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 7733 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 7733 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 7677 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 7740 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1815451 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1994 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1994 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1994 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1939 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 2000 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1033552 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1098 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1098 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1098 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1040 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1104 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1884604 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 2066 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 2066 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 2066 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 2012 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 2073 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 2778066 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 3019 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 3019 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 3019 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 2962 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 3025 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 5285212 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 6632 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 6632 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 6632 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 6579 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 6643 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 6380215 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 7772 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 7772 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 7772 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 7716 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 7782 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 5196603 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 6500 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 6500 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 6500 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 6443 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 6510 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 911 | 911 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1061656 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1097 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1097 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1097 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1041 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1104 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1018376 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1065 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1065 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1065 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1013 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1071 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1042129 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1079 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1079 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1079 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1024 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1086 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1029046 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1069 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1161874828 | 1069 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8150300 | 1069 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1012 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1075 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.BusySrcReqChk_A
| 0 | 0 | 1161874828 | 1055366 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.DstReqKnown_A
| 0 | 0 | 8150300 | 7300854 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.SrcAckBusyChk_A
| 0 | 0 | 1161874828 | 1173 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.SrcBusyKnown_A
| 0 | 0 | 1161874828 | 1161436421 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 8150300 | 779 | 0 | 911 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 8150300 | 779 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 1161874828 | 1952 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 8150300 | 1049 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8150300 | 1119 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1161874828 | 1180 | 0 | 0 |
|
tb.dut.u_reg.wePulse
| 0 | 0 | 1161874828 | 128064 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.CntClr_A
| 0 | 0 | 7886385 | 278 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.CntIncr_A
| 0 | 0 | 7886385 | 184750 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.CntNoWrap_A
| 0 | 0 | 7886385 | 7229552 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DetectStDropOut_A
| 0 | 0 | 7886385 | 2 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DetectedOut_A
| 0 | 0 | 7886385 | 794 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DetectedPulseOut_A
| 0 | 0 | 7886385 | 126 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DisabledIdleSt_A
| 0 | 0 | 7886385 | 7038514 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DisabledNoDetection_A
| 0 | 0 | 7886385 | 7040816 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.EnterDebounceSt_A
| 0 | 0 | 7886385 | 154 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.EnterDetectSt_A
| 0 | 0 | 7886385 | 128 | 0 | 0 |
|