Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T13,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T13,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T13,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T17
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T13,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T13,T17
0	1	Covered	T81,T100
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T13,T17
0	1	Covered	T1,T13,T17
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T13,T17
1	-	Covered	T1,T13,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T13,T17
DetectSt	168	Covered	T1,T13,T17
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T13,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T13,T17
DebounceSt->IdleSt	163	Covered	T12,T124,T37
DetectSt->IdleSt	186	Covered	T81,T100
DetectSt->StableSt	191	Covered	T1,T13,T17
IdleSt->DebounceSt	148	Covered	T1,T13,T17
StableSt->IdleSt	206	Covered	T1,T13,T17

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T13,T17
0	1	Covered	T1,T13,T17
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T17
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T13,T17
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T13,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T124,T118
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T13,T17
DetectSt	-	-	-	-	1	-	-	Covered	T81,T100
DetectSt	-	-	-	-	0	1	-	Covered	T1,T13,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T13,T17
StableSt	-	-	-	-	-	-	0	Covered	T1,T13,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	278	0	0
CntIncr_A	7886385	184750	0	0
CntNoWrap_A	7886385	7229552	0	0
DetectStDropOut_A	7886385	2	0	0
DetectedOut_A	7886385	794	0	0
DetectedPulseOut_A	7886385	126	0	0
DisabledIdleSt_A	7886385	7038514	0	0
DisabledNoDetection_A	7886385	7040816	0	0
EnterDebounceSt_A	7886385	154	0	0
EnterDetectSt_A	7886385	128	0	0
EnterStableSt_A	7886385	126	0	0
PulseIsPulse_A	7886385	126	0	0
StayInStableSt	7886385	668	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7886385	6949	0	0
gen_low_level_sva.LowLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	126	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	278	0	0
T1	3823	4	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	3	0	0
T13	801	4	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	4	0	0
T18	10193	0	0	0
T19	760	4	0	0
T43	0	2	0	0
T44	0	6	0	0
T45	0	4	0	0
T46	0	2	0	0
T47	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	184750	0	0
T1	3823	58	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	43010	0	0
T13	801	155	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	170	0	0
T18	10193	0	0	0
T19	760	133	0	0
T43	0	68	0	0
T44	0	55521	0	0
T45	0	82	0	0
T46	0	80	0	0
T47	0	16	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229552	0	0
T1	3823	1414	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	396	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	377	0	0
T18	10193	9790	0	0
T19	760	355	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	2	0	0
T81	121523	1	0	0
T95	16383	0	0	0
T100	0	1	0	0
T108	414	0	0	0
T109	502	0	0	0
T110	422	0	0	0
T111	795	0	0	0
T112	404	0	0	0
T113	6162	0	0	0
T114	522	0	0	0
T115	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	794	0	0
T1	3823	18	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	4	0	0
T13	801	16	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	12	0	0
T18	10193	0	0	0
T19	760	22	0	0
T43	0	12	0	0
T44	0	17	0	0
T45	0	7	0	0
T46	0	4	0	0
T47	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	126	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	1	0	0
T13	801	2	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	2	0	0
T18	10193	0	0	0
T19	760	2	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7038514	0	0
T1	3823	1270	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	146	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	124	0	0
T18	10193	9790	0	0
T19	760	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7040816	0	0
T1	3823	1275	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	146	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	125	0	0
T18	10193	9792	0	0
T19	760	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	154	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	2	0	0
T13	801	2	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	2	0	0
T18	10193	0	0	0
T19	760	2	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	128	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	1	0	0
T13	801	2	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	2	0	0
T18	10193	0	0	0
T19	760	2	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	126	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	1	0	0
T13	801	2	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	2	0	0
T18	10193	0	0	0
T19	760	2	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	126	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	1	0	0
T13	801	2	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	2	0	0
T18	10193	0	0	0
T19	760	2	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	668	0	0
T1	3823	16	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	3	0	0
T13	801	14	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	10	0	0
T18	10193	0	0	0
T19	760	20	0	0
T43	0	11	0	0
T44	0	14	0	0
T45	0	5	0	0
T46	0	3	0	0
T47	0	3	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6949	0	0
T1	3823	17	0	0
T4	502	5	0	0
T5	423	1	0	0
T13	801	3	0	0
T14	502	5	0	0
T15	406	0	0	0
T16	527	5	0	0
T17	782	3	0	0
T18	10193	28	0	0
T19	760	3	0	0
T43	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	126	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	1	0	0
T13	801	2	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	2	0	0
T18	10193	0	0	0
T19	760	2	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T11,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T24,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T23,T24
1	0	Covered	T1,T4,T5
1	1	Covered	T11,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T24,T33
0	1	Covered	T37,T61,T40
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T24,T33
0	1	Unreachable
1	0	Covered	T11,T24,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T23,T24
DetectSt	168	Covered	T11,T24,T33
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T11,T24,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T24,T33
DebounceSt->IdleSt	163	Covered	T23,T61,T76
DetectSt->IdleSt	186	Covered	T37,T61,T40
DetectSt->StableSt	191	Covered	T11,T24,T33
IdleSt->DebounceSt	148	Covered	T11,T23,T24
StableSt->IdleSt	206	Covered	T11,T24,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T23,T24
0	1	Covered	T11,T23,T24
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T24,T33
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T24,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T61,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T37,T61,T40
DetectSt	-	-	-	-	0	1	-	Covered	T11,T24,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T24,T33
StableSt	-	-	-	-	-	-	0	Covered	T11,T24,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	169	0	0
CntIncr_A	7886385	229930	0	0
CntNoWrap_A	7886385	7229661	0	0
DetectStDropOut_A	7886385	21	0	0
DetectedOut_A	7886385	671334	0	0
DetectedPulseOut_A	7886385	49	0	0
DisabledIdleSt_A	7886385	5551404	0	0
DisabledNoDetection_A	7886385	5553743	0	0
EnterDebounceSt_A	7886385	100	0	0
EnterDetectSt_A	7886385	70	0	0
EnterStableSt_A	7886385	49	0	0
PulseIsPulse_A	7886385	49	0	0
StayInStableSt	7886385	671285	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7886385	6949	0	0
gen_low_level_sva.LowLevelEvent_A	7886385	7232171	0	0
gen_sticky_sva.StableStDropOut_A	7886385	764518	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	169	0	0
T11	16131	2	0	0
T12	45124	0	0	0
T23	1426	1	0	0
T24	233341	4	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	2	0	0
T37	0	6	0	0
T40	0	4	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	4	0	0
T61	0	5	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	1	0	0
T77	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	229930	0	0
T11	16131	67	0	0
T12	45124	0	0	0
T23	1426	96	0	0
T24	233341	196	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	75	0	0
T37	0	33	0	0
T40	0	86	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	86	0	0
T61	0	156	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	68	0	0
T77	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229661	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	21	0	0
T37	12758	2	0	0
T38	627	0	0	0
T39	866	0	0	0
T40	0	1	0	0
T61	11686	2	0	0
T72	16268	0	0	0
T73	475	0	0	0
T88	4271	0	0	0
T104	439	0	0	0
T105	426	0	0	0
T111	0	1	0	0
T125	0	4	0	0
T126	0	2	0	0
T127	0	1	0	0
T128	0	5	0	0
T129	0	3	0	0
T130	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	671334	0	0
T11	16131	110	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	38	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	525	0	0
T37	0	25	0	0
T40	0	88	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	351	0	0
T62	423	0	0	0
T63	440	0	0	0
T77	0	25	0	0
T87	0	17	0	0
T118	0	425	0	0
T119	0	506	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	49	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	2	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	2	0	0
T62	423	0	0	0
T63	440	0	0	0
T77	0	1	0	0
T87	0	1	0	0
T118	0	1	0	0
T119	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	5551404	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	5553743	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	100	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	1	0	0
T24	233341	2	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	1	0	0
T37	0	3	0	0
T40	0	2	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	2	0	0
T61	0	3	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	1	0	0
T77	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	70	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	2	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	1	0	0
T37	0	3	0	0
T40	0	2	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	423	0	0	0
T63	440	0	0	0
T77	0	1	0	0
T87	0	1	0	0
T118	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	49	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	2	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	2	0	0
T62	423	0	0	0
T63	440	0	0	0
T77	0	1	0	0
T87	0	1	0	0
T118	0	1	0	0
T119	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	49	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	2	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	2	0	0
T62	423	0	0	0
T63	440	0	0	0
T77	0	1	0	0
T87	0	1	0	0
T118	0	1	0	0
T119	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	671285	0	0
T11	16131	109	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	36	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	524	0	0
T37	0	24	0	0
T40	0	87	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	349	0	0
T62	423	0	0	0
T63	440	0	0	0
T77	0	24	0	0
T87	0	16	0	0
T118	0	424	0	0
T119	0	504	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6949	0	0
T1	3823	17	0	0
T4	502	5	0	0
T5	423	1	0	0
T13	801	3	0	0
T14	502	5	0	0
T15	406	0	0	0
T16	527	5	0	0
T17	782	3	0	0
T18	10193	28	0	0
T19	760	3	0	0
T43	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	764518	0	0
T11	16131	61	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	92892	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	87	0	0
T37	0	454	0	0
T40	0	218	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	322	0	0
T62	423	0	0	0
T63	440	0	0	0
T77	0	118	0	0
T87	0	84	0	0
T118	0	462	0	0
T119	0	571	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T11,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T24,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T23,T24
1	0	Covered	T1,T4,T5
1	1	Covered	T11,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T33,T60
0	1	Covered	T11,T24,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T33,T60
0	1	Unreachable
1	0	Covered	T11,T33,T60

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T23,T24
DetectSt	168	Covered	T11,T24,T33
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T11,T33,T60

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T24,T33
DebounceSt->IdleSt	163	Covered	T23,T24,T40
DetectSt->IdleSt	186	Covered	T11,T24,T87
DetectSt->StableSt	191	Covered	T11,T33,T60
IdleSt->DebounceSt	148	Covered	T11,T23,T24
StableSt->IdleSt	206	Covered	T11,T33,T60

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T23,T24
0	1	Covered	T11,T23,T24
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T24,T33
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T24,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T24,T40
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T11,T24,T87
DetectSt	-	-	-	-	0	1	-	Covered	T11,T33,T60
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T33,T60
StableSt	-	-	-	-	-	-	0	Covered	T11,T33,T60
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	152	0	0
CntIncr_A	7886385	361688	0	0
CntNoWrap_A	7886385	7229678	0	0
DetectStDropOut_A	7886385	7	0	0
DetectedOut_A	7886385	467382	0	0
DetectedPulseOut_A	7886385	48	0	0
DisabledIdleSt_A	7886385	5551404	0	0
DisabledNoDetection_A	7886385	5553743	0	0
EnterDebounceSt_A	7886385	98	0	0
EnterDetectSt_A	7886385	55	0	0
EnterStableSt_A	7886385	48	0	0
PulseIsPulse_A	7886385	48	0	0
StayInStableSt	7886385	467334	0	0
gen_high_level_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_sticky_sva.StableStDropOut_A	7886385	600298	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	152	0	0
T11	16131	6	0	0
T12	45124	0	0	0
T23	1426	1	0	0
T24	233341	3	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	2	0	0
T37	0	2	0	0
T40	0	4	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	4	0	0
T61	0	2	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	2	0	0
T77	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	361688	0	0
T11	16131	258	0	0
T12	45124	0	0	0
T23	1426	51	0	0
T24	233341	93094	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	10	0	0
T37	0	81	0	0
T40	0	352	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	102	0	0
T61	0	23	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	36	0	0
T77	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229678	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7	0	0
T11	16131	2	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	1	0	0
T26	498	0	0	0
T32	36601	0	0	0
T42	15182	0	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T87	0	2	0	0
T128	0	1	0	0
T131	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	467382	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	68	0	0
T37	0	627	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	440	0	0
T61	0	59	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	23	0	0
T77	0	72	0	0
T118	0	120	0	0
T120	0	1	0	0
T121	0	65	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	48	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	1	0	0
T37	0	1	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T118	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	5551404	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	5553743	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	98	0	0
T11	16131	3	0	0
T12	45124	0	0	0
T23	1426	1	0	0
T24	233341	2	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	1	0	0
T37	0	1	0	0
T40	0	4	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	1	0	0
T77	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	55	0	0
T11	16131	3	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	1	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	1	0	0
T37	0	1	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T87	0	2	0	0
T118	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	48	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	1	0	0
T37	0	1	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T118	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	48	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	1	0	0
T37	0	1	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T118	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	467334	0	0
T33	9459	67	0	0
T35	18013	0	0	0
T37	0	626	0	0
T60	0	438	0	0
T61	0	58	0	0
T65	498	0	0	0
T66	495	0	0	0
T76	0	22	0	0
T77	0	71	0	0
T118	0	119	0	0
T121	0	64	0	0
T123	0	228	0	0
T124	39028	0	0	0
T125	0	875	0	0
T132	857	0	0	0
T133	752	0	0	0
T134	695	0	0	0
T135	421	0	0	0
T136	941	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	600298	0	0
T11	16131	40	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	614	0	0
T37	0	94	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	219	0	0
T61	0	217	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	98	0	0
T77	0	236	0	0
T118	0	792	0	0
T120	0	86	0	0
T121	0	166	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T11,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T24,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T23,T24
1	0	Covered	T1,T4,T5
1	1	Covered	T11,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T37,T40
0	1	Covered	T24,T33,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T37,T40
0	1	Unreachable
1	0	Covered	T11,T37,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T23,T24
DetectSt	168	Covered	T11,T24,T33
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T11,T37,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T24,T33
DebounceSt->IdleSt	163	Covered	T23,T24,T33
DetectSt->IdleSt	186	Covered	T24,T33,T85
DetectSt->StableSt	191	Covered	T11,T37,T40
IdleSt->DebounceSt	148	Covered	T11,T23,T24
StableSt->IdleSt	206	Covered	T11,T37,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T23,T24
0	1	Covered	T11,T23,T24
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T24,T33
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T24,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T24,T33
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T24,T33,T85
DetectSt	-	-	-	-	0	1	-	Covered	T11,T37,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T37,T40
StableSt	-	-	-	-	-	-	0	Covered	T11,T37,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	149	0	0
CntIncr_A	7886385	89732	0	0
CntNoWrap_A	7886385	7229681	0	0
DetectStDropOut_A	7886385	6	0	0
DetectedOut_A	7886385	234394	0	0
DetectedPulseOut_A	7886385	45	0	0
DisabledIdleSt_A	7886385	5551404	0	0
DisabledNoDetection_A	7886385	5553743	0	0
EnterDebounceSt_A	7886385	99	0	0
EnterDetectSt_A	7886385	51	0	0
EnterStableSt_A	7886385	45	0	0
PulseIsPulse_A	7886385	45	0	0
StayInStableSt	7886385	234349	0	0
gen_high_event_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_high_level_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_sticky_sva.StableStDropOut_A	7886385	584821	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	149	0	0
T11	16131	2	0	0
T12	45124	0	0	0
T23	1426	1	0	0
T24	233341	3	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	7	0	0
T37	0	2	0	0
T40	0	2	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	8	0	0
T61	0	1	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	2	0	0
T77	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	89732	0	0
T11	16131	36	0	0
T12	45124	0	0	0
T23	1426	87	0	0
T24	233341	64	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	324	0	0
T37	0	38	0	0
T40	0	49	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	688	0	0
T61	0	22	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	64	0	0
T77	0	97	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229681	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6	0	0
T24	233341	1	0	0
T33	0	3	0	0
T34	39976	0	0	0
T48	481	0	0	0
T58	1245	0	0	0
T63	440	0	0	0
T85	0	1	0	0
T127	0	1	0	0
T137	25927	0	0	0
T138	425	0	0	0
T139	128684	0	0	0
T140	444	0	0	0
T141	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	234394	0	0
T11	16131	128	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T37	0	336	0	0
T40	0	230	0	0
T42	15182	0	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	36	0	0
T77	0	213	0	0
T119	0	511	0	0
T120	0	1	0	0
T121	0	105	0	0
T122	0	88	0	0
T123	0	259	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	45	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	15182	0	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T119	0	2	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	5551404	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	5553743	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	99	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	1	0	0
T24	233341	2	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	4	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	15182	0	0	0
T57	779	0	0	0
T60	0	8	0	0
T61	0	1	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	1	0	0
T77	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	51	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	1	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	3	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	15182	0	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T119	0	2	0	0
T120	0	1	0	0
T121	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	45	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	15182	0	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T119	0	2	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	45	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	15182	0	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T119	0	2	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	234349	0	0
T11	16131	127	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T37	0	335	0	0
T40	0	229	0	0
T42	15182	0	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	35	0	0
T77	0	212	0	0
T119	0	509	0	0
T121	0	104	0	0
T122	0	87	0	0
T123	0	258	0	0
T125	0	411	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	584821	0	0
T11	16131	183	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T37	0	431	0	0
T40	0	178	0	0
T42	15182	0	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T76	0	65	0	0
T77	0	34	0	0
T119	0	604	0	0
T120	0	119	0	0
T121	0	131	0	0
T122	0	635	0	0
T123	0	158	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T11,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T8,T11,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T11,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T12
1	0	Covered	T1,T4,T5
1	1	Covered	T8,T11,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T40
0	1	Covered	T11,T40,T142
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T11,T40
1	-	Covered	T11,T40,T142

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T40
DetectSt	168	Covered	T8,T11,T40
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T8,T11,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T11,T40
DebounceSt->IdleSt	163	Covered	T143,T144,T78
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T11,T40
IdleSt->DebounceSt	148	Covered	T8,T11,T40
StableSt->IdleSt	206	Covered	T11,T40,T142

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T40
0	1	Covered	T8,T11,T40
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T40
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T40
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T11,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T143,T144
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T11,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T40,T142
StableSt	-	-	-	-	-	-	0	Covered	T8,T11,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	77	0	0
CntIncr_A	7886385	2079	0	0
CntNoWrap_A	7886385	7229753	0	0
DetectStDropOut_A	7886385	0	0	0
DetectedOut_A	7886385	2812	0	0
DetectedPulseOut_A	7886385	37	0	0
DisabledIdleSt_A	7886385	7197897	0	0
DisabledNoDetection_A	7886385	7200180	0	0
EnterDebounceSt_A	7886385	40	0	0
EnterDetectSt_A	7886385	37	0	0
EnterStableSt_A	7886385	37	0	0
PulseIsPulse_A	7886385	37	0	0
StayInStableSt	7886385	2754	0	0
gen_high_level_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	77	0	0
T8	489	2	0	0
T9	20346	0	0	0
T11	0	2	0	0
T25	2839	0	0	0
T28	507	0	0	0
T40	0	2	0	0
T45	650	0	0	0
T46	678	0	0	0
T47	685	0	0	0
T54	0	2	0	0
T56	648	0	0	0
T68	422	0	0	0
T70	506	0	0	0
T87	0	2	0	0
T125	0	4	0	0
T142	0	2	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	2079	0	0
T8	489	15	0	0
T9	20346	0	0	0
T11	0	31	0	0
T25	2839	0	0	0
T28	507	0	0	0
T40	0	75	0	0
T45	650	0	0	0
T46	678	0	0	0
T47	685	0	0	0
T54	0	20	0	0
T56	648	0	0	0
T68	422	0	0	0
T70	506	0	0	0
T87	0	98	0	0
T125	0	44	0	0
T142	0	44	0	0
T145	0	65	0	0
T146	0	67	0	0
T147	0	87	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229753	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	2812	0	0
T8	489	48	0	0
T9	20346	0	0	0
T11	0	74	0	0
T25	2839	0	0	0
T28	507	0	0	0
T40	0	172	0	0
T45	650	0	0	0
T46	678	0	0	0
T47	685	0	0	0
T54	0	10	0	0
T56	648	0	0	0
T68	422	0	0	0
T70	506	0	0	0
T87	0	201	0	0
T125	0	173	0	0
T142	0	37	0	0
T145	0	41	0	0
T146	0	12	0	0
T147	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	37	0	0
T8	489	1	0	0
T9	20346	0	0	0
T11	0	1	0	0
T25	2839	0	0	0
T28	507	0	0	0
T40	0	1	0	0
T45	650	0	0	0
T46	678	0	0	0
T47	685	0	0	0
T54	0	1	0	0
T56	648	0	0	0
T68	422	0	0	0
T70	506	0	0	0
T87	0	1	0	0
T125	0	2	0	0
T142	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7197897	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7200180	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	40	0	0
T8	489	1	0	0
T9	20346	0	0	0
T11	0	1	0	0
T25	2839	0	0	0
T28	507	0	0	0
T40	0	1	0	0
T45	650	0	0	0
T46	678	0	0	0
T47	685	0	0	0
T54	0	1	0	0
T56	648	0	0	0
T68	422	0	0	0
T70	506	0	0	0
T87	0	1	0	0
T125	0	2	0	0
T142	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	37	0	0
T8	489	1	0	0
T9	20346	0	0	0
T11	0	1	0	0
T25	2839	0	0	0
T28	507	0	0	0
T40	0	1	0	0
T45	650	0	0	0
T46	678	0	0	0
T47	685	0	0	0
T54	0	1	0	0
T56	648	0	0	0
T68	422	0	0	0
T70	506	0	0	0
T87	0	1	0	0
T125	0	2	0	0
T142	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	37	0	0
T8	489	1	0	0
T9	20346	0	0	0
T11	0	1	0	0
T25	2839	0	0	0
T28	507	0	0	0
T40	0	1	0	0
T45	650	0	0	0
T46	678	0	0	0
T47	685	0	0	0
T54	0	1	0	0
T56	648	0	0	0
T68	422	0	0	0
T70	506	0	0	0
T87	0	1	0	0
T125	0	2	0	0
T142	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	37	0	0
T8	489	1	0	0
T9	20346	0	0	0
T11	0	1	0	0
T25	2839	0	0	0
T28	507	0	0	0
T40	0	1	0	0
T45	650	0	0	0
T46	678	0	0	0
T47	685	0	0	0
T54	0	1	0	0
T56	648	0	0	0
T68	422	0	0	0
T70	506	0	0	0
T87	0	1	0	0
T125	0	2	0	0
T142	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	2754	0	0
T8	489	46	0	0
T9	20346	0	0	0
T11	0	73	0	0
T25	2839	0	0	0
T28	507	0	0	0
T40	0	171	0	0
T45	650	0	0	0
T46	678	0	0	0
T47	685	0	0	0
T54	0	9	0	0
T56	648	0	0	0
T68	422	0	0	0
T70	506	0	0	0
T87	0	200	0	0
T125	0	170	0	0
T142	0	36	0	0
T145	0	39	0	0
T146	0	11	0	0
T147	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	15	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T40	0	1	0	0
T42	15182	0	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T87	0	1	0	0
T125	0	1	0	0
T142	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T6,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T11
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T6,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T11
0	1	Covered	T151,T152
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T11
0	1	Covered	T6,T153,T154
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T6,T11
1	-	Covered	T6,T153,T154

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T11
DetectSt	168	Covered	T1,T6,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T6,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T11
DebounceSt->IdleSt	163	Covered	T11,T155,T156
DetectSt->IdleSt	186	Covered	T151,T152
DetectSt->StableSt	191	Covered	T1,T6,T11
IdleSt->DebounceSt	148	Covered	T1,T6,T11
StableSt->IdleSt	206	Covered	T1,T6,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T11
0	1	Covered	T1,T6,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T155,T156
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T11
DetectSt	-	-	-	-	1	-	-	Covered	T151,T152
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T153,T154
StableSt	-	-	-	-	-	-	0	Covered	T1,T6,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	142	0	0
CntIncr_A	7886385	42652	0	0
CntNoWrap_A	7886385	7229688	0	0
DetectStDropOut_A	7886385	2	0	0
DetectedOut_A	7886385	57439	0	0
DetectedPulseOut_A	7886385	67	0	0
DisabledIdleSt_A	7886385	7052247	0	0
DisabledNoDetection_A	7886385	7054524	0	0
EnterDebounceSt_A	7886385	73	0	0
EnterDetectSt_A	7886385	69	0	0
EnterStableSt_A	7886385	67	0	0
PulseIsPulse_A	7886385	67	0	0
StayInStableSt	7886385	57342	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7886385	2708	0	0
gen_low_level_sva.LowLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	142	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	0	2	0	0
T11	0	5	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	2	0	0
T37	0	2	0	0
T86	0	2	0	0
T142	0	4	0	0
T153	0	2	0	0
T154	0	4	0	0
T157	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	42652	0	0
T1	3823	77	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	0	42	0	0
T11	0	6369	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	47	0	0
T37	0	12	0	0
T86	0	74	0	0
T142	0	88	0	0
T153	0	22	0	0
T154	0	122	0	0
T157	0	41	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229688	0	0
T1	3823	1416	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	2	0	0
T151	865	1	0	0
T152	0	1	0	0
T158	701	0	0	0
T159	16293	0	0	0
T160	5691	0	0	0
T161	10184	0	0	0
T162	421	0	0	0
T163	424	0	0	0
T164	521	0	0	0
T165	491	0	0	0
T166	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	57439	0	0
T1	3823	186	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	0	84	0	0
T11	0	81	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	41	0	0
T37	0	53	0	0
T86	0	332	0	0
T142	0	262	0	0
T153	0	41	0	0
T154	0	93	0	0
T157	0	51	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	67	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	0	1	0	0
T11	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T86	0	1	0	0
T142	0	2	0	0
T153	0	1	0	0
T154	0	2	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7052247	0	0
T1	3823	683	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7054524	0	0
T1	3823	687	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	73	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	0	1	0	0
T11	0	3	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T86	0	1	0	0
T142	0	2	0	0
T153	0	1	0	0
T154	0	2	0	0
T157	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	69	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	0	1	0	0
T11	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T86	0	1	0	0
T142	0	2	0	0
T153	0	1	0	0
T154	0	2	0	0
T157	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	67	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	0	1	0	0
T11	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T86	0	1	0	0
T142	0	2	0	0
T153	0	1	0	0
T154	0	2	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	67	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	0	1	0	0
T11	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T86	0	1	0	0
T142	0	2	0	0
T153	0	1	0	0
T154	0	2	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	57342	0	0
T1	3823	184	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	0	83	0	0
T11	0	77	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	39	0	0
T37	0	51	0	0
T86	0	330	0	0
T142	0	259	0	0
T153	0	40	0	0
T154	0	90	0	0
T157	0	49	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	2708	0	0
T1	3823	10	0	0
T4	502	6	0	0
T5	423	2	0	0
T6	0	1	0	0
T13	801	0	0	0
T14	502	6	0	0
T15	406	0	0	0
T16	527	6	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T51	0	8	0	0
T52	0	2	0	0
T53	0	3	0	0
T55	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	36	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T41	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T82	0	1	0	0
T125	0	1	0	0
T142	0	1	0	0
T147	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	422	0	0	0