Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	90.12	93.48	90.48		83.33	90.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	90.21	93.48	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	90.21	93.48	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	91.56	95.65	90.48		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	97.61	97.83	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
90.21	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.61	97.83

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
90.21	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
91.56	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
90.12	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T2,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T2,T3
1	0	Covered	T1,T18,T2
1	1	Covered	T18,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T2,T3
0	1	Covered	T2,T7,T34
1	0	Covered	T54,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T49,T54,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T2,T3
1	-	Covered	T2,T3,T7

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
90.21	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.61	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
90.21	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T13,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T13,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T13,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T17
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T13,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T13,T17
0	1	Covered	T80,T81,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T13,T17
0	1	Covered	T1,T13,T17
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T13,T17
1	-	Covered	T1,T13,T17

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T3,T9
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T3,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T3,T9
1	0	Covered	T18,T3,T9
1	1	Covered	T18,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T3,T9
0	1	Covered	T18,T49,T71
1	0	Covered	T18,T42,T49

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T3,T9
0	1	Covered	T18,T3,T9
1	0	Covered	T9,T83,T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T3,T9
1	-	Covered	T18,T3,T9

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T24,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T23,T24
1	0	Covered	T1,T4,T5
1	1	Covered	T11,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T37,T40
0	1	Covered	T24,T33,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T37,T40
0	1	Unreachable
1	0	Covered	T11,T37,T40

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
91.56	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
90.12	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T11
0	1	Covered	T6,T86,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T11
0	1	Covered	T1,T11,T12
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T11
1	-	Covered	T1,T11,T12

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T24,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T23,T24
1	0	Covered	T1,T4,T5
1	1	Covered	T11,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T33,T60
0	1	Covered	T11,T24,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T33,T60
0	1	Unreachable
1	0	Covered	T11,T33,T60

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T24,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T23,T24
1	0	Covered	T1,T4,T5
1	1	Covered	T11,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T24,T33
0	1	Covered	T37,T61,T40
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T24,T33
0	1	Unreachable
1	0	Covered	T11,T24,T33

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T13,T17
DetectSt	168	Covered	T1,T13,T17
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T13,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T13,T17
DebounceSt->IdleSt	163	Covered	T8,T11,T12
DetectSt->IdleSt	186	Covered	T11,T24,T33
DetectSt->StableSt	191	Covered	T1,T13,T17
IdleSt->DebounceSt	148	Covered	T1,T13,T17
StableSt->IdleSt	206	Covered	T1,T13,T17

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
90.21	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
90.21	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
91.56	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
90.12	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T13,T17
0	1	Covered	T1,T13,T17
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T17
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T13,T17
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T13,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T11,T12
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T13,T17
DetectSt	-	-	-	-	1	-	-	Covered	T11,T24,T37
DetectSt	-	-	-	-	0	1	-	Covered	T1,T13,T17
DetectSt	-	-	-	-	0	0	-	Covered	T18,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T13,T17
StableSt	-	-	-	-	-	-	0	Covered	T1,T13,T17
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T3,T9
0	1	Covered	T18,T3,T9
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T3,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T3,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T24,T33
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T3,T9
DetectSt	-	-	-	-	1	-	-	Covered	T18,T42,T24
DetectSt	-	-	-	-	0	1	-	Covered	T18,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T18,T3,T9
StableSt	-	-	-	-	-	-	1	Covered	T18,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T18,T3,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	205046010	17740	0	0
CntIncr_A	205046010	2199629	0	0
CntNoWrap_A	205046010	187957840	0	0
DetectStDropOut_A	205046010	2042	0	0
DetectedOut_A	205046010	2169664	0	0
DetectedPulseOut_A	205046010	5622	0	0
DisabledIdleSt_A	205046010	176828548	0	0
DisabledNoDetection_A	205046010	176885167	0	0
EnterDebounceSt_A	205046010	9170	0	0
EnterDetectSt_A	205046010	8585	0	0
EnterStableSt_A	205046010	5622	0	0
PulseIsPulse_A	205046010	5622	0	0
StayInStableSt	205046010	2163262	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	70977465	52094	0	0
gen_high_event_sva.HighLevelEvent_A	39431925	36160855	0	0
gen_high_level_sva.HighLevelEvent_A	134068545	122946907	0	0
gen_low_level_sva.LowLevelEvent_A	70977465	65089539	0	0
gen_not_sticky_sva.StableStDropOut_A	181386855	4586	0	0
gen_sticky_sva.StableStDropOut_A	23659155	1949637	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205046010	17740	0	0
T1	3823	4	0	0
T2	45750	5	0	0
T3	76950	32	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	2058	0	0	0
T7	17776	13	0	0
T9	0	22	0	0
T12	0	4	0	0
T13	801	4	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	4	0	0
T18	30579	42	0	0
T19	2280	4	0	0
T27	0	1	0	0
T33	0	2	0	0
T34	0	10	0	0
T35	0	6	0	0
T42	0	30	0	0
T43	1474	2	0	0
T44	56028	6	0	0
T45	0	4	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T50	2694	0	0	0
T51	1566	0	0	0
T52	1272	0	0	0
T53	1272	0	0	0
T55	507	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205046010	2199629	0	0
T1	3823	58	0	0
T2	45750	280	0	0
T3	76950	992	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	2058	0	0	0
T7	17776	643	0	0
T9	0	605	0	0
T12	0	43030	0	0
T13	801	155	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	170	0	0
T18	30579	1130	0	0
T19	2280	133	0	0
T27	0	20	0	0
T33	0	40	0	0
T34	0	840	0	0
T35	0	168	0	0
T42	0	852	0	0
T43	1474	68	0	0
T44	56028	55521	0	0
T45	0	82	0	0
T46	0	80	0	0
T47	0	16	0	0
T48	0	25	0	0
T50	2694	0	0	0
T51	1566	0	0	0
T52	1272	0	0	0
T53	1272	0	0	0
T55	507	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205046010	187957840	0	0
T1	99398	36844	0	0
T4	13052	2626	0	0
T5	10998	572	0	0
T13	20826	10396	0	0
T14	13052	2626	0	0
T15	10556	130	0	0
T16	13702	3276	0	0
T17	20332	9902	0	0
T18	265018	254398	0	0
T19	19760	9330	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205046010	2042	0	0
T38	627	0	0	0
T39	866	0	0	0
T40	22074	0	0	0
T49	39327	6	0	0
T54	0	1	0	0
T61	11686	0	0	0
T74	6608	23	0	0
T81	121523	1	0	0
T84	0	4	0	0
T88	4271	1	0	0
T89	0	14	0	0
T90	0	20	0	0
T91	0	13	0	0
T92	0	13	0	0
T93	0	1	0	0
T94	0	7	0	0
T95	16383	6	0	0
T96	0	1	0	0
T97	0	14	0	0
T98	0	1	0	0
T99	0	3	0	0
T100	0	1	0	0
T101	0	3	0	0
T102	0	2	0	0
T103	0	5	0	0
T104	439	0	0	0
T105	426	0	0	0
T106	426	0	0	0
T107	422	0	0	0
T108	414	0	0	0
T109	502	0	0	0
T110	422	0	0	0
T111	795	0	0	0
T112	404	0	0	0
T113	6162	0	0	0
T114	522	0	0	0
T115	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205046010	2169664	0	0
T1	3823	18	0	0
T2	45750	8	0	0
T3	76950	1629	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	2058	0	0	0
T7	17776	28	0	0
T9	0	403	0	0
T12	0	4	0	0
T13	801	16	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	12	0	0
T18	30579	2138	0	0
T19	2280	22	0	0
T34	0	41	0	0
T35	0	796	0	0
T43	1474	12	0	0
T44	56028	17	0	0
T45	0	7	0	0
T46	0	4	0	0
T47	0	4	0	0
T48	0	3	0	0
T50	2694	0	0	0
T51	1566	0	0	0
T52	1272	0	0	0
T53	1272	0	0	0
T55	507	0	0	0
T71	0	322	0	0
T72	0	961	0	0
T116	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205046010	5622	0	0
T1	3823	2	0	0
T2	45750	2	0	0
T3	76950	16	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	2058	0	0	0
T7	17776	6	0	0
T9	0	11	0	0
T12	0	1	0	0
T13	801	2	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	2	0	0
T18	30579	21	0	0
T19	2280	2	0	0
T34	0	5	0	0
T35	0	4	0	0
T43	1474	1	0	0
T44	56028	3	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	2694	0	0	0
T51	1566	0	0	0
T52	1272	0	0	0
T53	1272	0	0	0
T55	507	0	0	0
T71	0	16	0	0
T72	0	12	0	0
T116	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205046010	176828548	0	0
T1	99398	31575	0	0
T4	13052	2626	0	0
T5	10998	572	0	0
T13	20826	10146	0	0
T14	13052	2626	0	0
T15	10556	130	0	0
T16	13702	3276	0	0
T17	20332	9649	0	0
T18	265018	234097	0	0
T19	19760	9099	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205046010	176885167	0	0
T1	99398	31698	0	0
T4	13052	2652	0	0
T5	10998	598	0	0
T13	20826	10171	0	0
T14	13052	2652	0	0
T15	10556	156	0	0
T16	13702	3302	0	0
T17	20332	9675	0	0
T18	265018	234143	0	0
T19	19760	9125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205046010	9170	0	0
T1	3823	2	0	0
T2	45750	3	0	0
T3	76950	16	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	2058	0	0	0
T7	17776	7	0	0
T9	0	11	0	0
T12	0	3	0	0
T13	801	2	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	2	0	0
T18	30579	21	0	0
T19	2280	2	0	0
T27	0	1	0	0
T33	0	2	0	0
T34	0	5	0	0
T35	0	3	0	0
T42	0	15	0	0
T43	1474	1	0	0
T44	56028	3	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	2694	0	0	0
T51	1566	0	0	0
T52	1272	0	0	0
T53	1272	0	0	0
T55	507	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205046010	8585	0	0
T1	3823	2	0	0
T2	45750	2	0	0
T3	76950	16	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	2058	0	0	0
T7	17776	6	0	0
T9	0	11	0	0
T12	0	1	0	0
T13	801	2	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	2	0	0
T18	30579	21	0	0
T19	2280	2	0	0
T34	0	5	0	0
T35	0	4	0	0
T42	0	15	0	0
T43	1474	1	0	0
T44	56028	3	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	2694	0	0	0
T51	1566	0	0	0
T52	1272	0	0	0
T53	1272	0	0	0
T55	507	0	0	0
T71	0	16	0	0
T116	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205046010	5622	0	0
T1	3823	2	0	0
T2	45750	2	0	0
T3	76950	16	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	2058	0	0	0
T7	17776	6	0	0
T9	0	11	0	0
T12	0	1	0	0
T13	801	2	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	2	0	0
T18	30579	21	0	0
T19	2280	2	0	0
T34	0	5	0	0
T35	0	4	0	0
T43	1474	1	0	0
T44	56028	3	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	2694	0	0	0
T51	1566	0	0	0
T52	1272	0	0	0
T53	1272	0	0	0
T55	507	0	0	0
T71	0	16	0	0
T72	0	12	0	0
T116	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205046010	5622	0	0
T1	3823	2	0	0
T2	45750	2	0	0
T3	76950	16	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	2058	0	0	0
T7	17776	6	0	0
T9	0	11	0	0
T12	0	1	0	0
T13	801	2	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	2	0	0
T18	30579	21	0	0
T19	2280	2	0	0
T34	0	5	0	0
T35	0	4	0	0
T43	1474	1	0	0
T44	56028	3	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	2694	0	0	0
T51	1566	0	0	0
T52	1272	0	0	0
T53	1272	0	0	0
T55	507	0	0	0
T71	0	16	0	0
T72	0	12	0	0
T116	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	205046010	2163262	0	0
T1	3823	16	0	0
T2	45750	6	0	0
T3	76950	1605	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	2058	0	0	0
T7	17776	22	0	0
T9	0	391	0	0
T12	0	3	0	0
T13	801	14	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	10	0	0
T18	30579	2115	0	0
T19	2280	20	0	0
T34	0	36	0	0
T35	0	791	0	0
T43	1474	11	0	0
T44	56028	14	0	0
T45	0	5	0	0
T46	0	3	0	0
T47	0	3	0	0
T48	0	2	0	0
T50	2694	0	0	0
T51	1566	0	0	0
T52	1272	0	0	0
T53	1272	0	0	0
T55	507	0	0	0
T71	0	305	0	0
T72	0	949	0	0
T116	0	75	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70977465	52094	0	0
T1	34407	115	0	0
T2	0	44	0	0
T3	0	120	0	0
T4	4518	46	0	0
T5	3807	14	0	0
T6	0	7	0	0
T13	7209	9	0	0
T14	4518	46	0	0
T15	3654	0	0	0
T16	4743	44	0	0
T17	7038	9	0	0
T18	91737	193	0	0
T19	6840	9	0	0
T43	0	9	0	0
T50	0	4	0	0
T51	0	31	0	0
T52	0	8	0	0
T53	0	9	0	0
T55	0	7	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39431925	36160855	0	0
T1	19115	7115	0	0
T4	2510	510	0	0
T5	2115	115	0	0
T13	4005	2005	0	0
T14	2510	510	0	0
T15	2030	30	0	0
T16	2635	635	0	0
T17	3910	1910	0	0
T18	50965	48960	0	0
T19	3800	1800	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134068545	122946907	0	0
T1	64991	24191	0	0
T4	8534	1734	0	0
T5	7191	391	0	0
T13	13617	6817	0	0
T14	8534	1734	0	0
T15	6902	102	0	0
T16	8959	2159	0	0
T17	13294	6494	0	0
T18	173281	166464	0	0
T19	12920	6120	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70977465	65089539	0	0
T1	34407	12807	0	0
T4	4518	918	0	0
T5	3807	207	0	0
T13	7209	3609	0	0
T14	4518	918	0	0
T15	3654	54	0	0
T16	4743	1143	0	0
T17	7038	3438	0	0
T18	91737	88128	0	0
T19	6840	3240	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181386855	4586	0	0
T1	3823	2	0	0
T2	30500	2	0	0
T3	51300	0	0	0
T4	502	0	0	0
T5	423	0	0	0
T6	1372	0	0	0
T7	17776	6	0	0
T9	0	10	0	0
T12	0	1	0	0
T13	801	2	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	2	0	0
T18	20386	19	0	0
T19	1520	2	0	0
T34	0	5	0	0
T35	0	3	0	0
T40	0	3	0	0
T43	737	1	0	0
T44	56028	3	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	1796	0	0	0
T51	1044	0	0	0
T52	848	0	0	0
T53	848	0	0	0
T55	507	0	0	0
T71	0	15	0	0
T116	0	7	0	0
T117	0	1	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23659155	1949637	0	0
T11	48393	284	0	0
T12	135372	0	0	0
T23	4278	0	0	0
T24	700023	92892	0	0
T26	1494	0	0	0
T32	109803	0	0	0
T33	0	701	0	0
T37	0	979	0	0
T40	0	396	0	0
T42	45546	0	0	0
T57	2337	0	0	0
T60	0	541	0	0
T61	0	217	0	0
T62	1269	0	0	0
T63	1320	0	0	0
T76	0	163	0	0
T77	0	388	0	0
T87	0	84	0	0
T118	0	1254	0	0
T119	0	1175	0	0
T120	0	205	0	0
T121	0	297	0	0
T122	0	635	0	0
T123	0	158	0	0