Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.12	93.48	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.12	93.48	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T8,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T37
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T8,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T41
0	1	Covered	T41,T125,T170
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T41
1	-	Covered	T41,T125,T170

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T41
DetectSt	168	Covered	T1,T8,T41
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T8,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T41
DebounceSt->IdleSt	163	Covered	T78
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T8,T41
IdleSt->DebounceSt	148	Covered	T1,T8,T41
StableSt->IdleSt	206	Covered	T1,T41,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T41
0	1	Covered	T1,T8,T41
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T41
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T41
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T41
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T54,T125
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	77	0	0
CntIncr_A	7886385	49985	0	0
CntNoWrap_A	7886385	7229753	0	0
DetectStDropOut_A	7886385	0	0	0
DetectedOut_A	7886385	54787	0	0
DetectedPulseOut_A	7886385	38	0	0
DisabledIdleSt_A	7886385	7022835	0	0
DisabledNoDetection_A	7886385	7025120	0	0
EnterDebounceSt_A	7886385	39	0	0
EnterDetectSt_A	7886385	38	0	0
EnterStableSt_A	7886385	38	0	0
PulseIsPulse_A	7886385	38	0	0
StayInStableSt	7886385	54727	0	0
gen_high_level_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	77	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T41	0	2	0	0
T54	0	2	0	0
T125	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T170	0	2	0	0
T171	0	2	0	0
T172	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	49985	0	0
T1	3823	77	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	15	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T41	0	17775	0	0
T54	0	20	0	0
T125	0	44	0	0
T145	0	65	0	0
T146	0	67	0	0
T170	0	77	0	0
T171	0	23	0	0
T172	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229753	0	0
T1	3823	1416	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	54787	0	0
T1	3823	538	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	49	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T41	0	36747	0	0
T54	0	11	0	0
T125	0	84	0	0
T145	0	162	0	0
T146	0	12	0	0
T170	0	72	0	0
T171	0	59	0	0
T172	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	38	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T41	0	1	0	0
T54	0	1	0	0
T125	0	2	0	0
T145	0	1	0	0
T146	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7022835	0	0
T1	3823	683	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7025120	0	0
T1	3823	687	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	39	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T41	0	1	0	0
T54	0	1	0	0
T125	0	2	0	0
T145	0	1	0	0
T146	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	38	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T41	0	1	0	0
T54	0	1	0	0
T125	0	2	0	0
T145	0	1	0	0
T146	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	38	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T41	0	1	0	0
T54	0	1	0	0
T125	0	2	0	0
T145	0	1	0	0
T146	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	38	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T41	0	1	0	0
T54	0	1	0	0
T125	0	2	0	0
T145	0	1	0	0
T146	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	54727	0	0
T1	3823	536	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	47	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T41	0	36746	0	0
T54	0	10	0	0
T125	0	81	0	0
T145	0	160	0	0
T146	0	11	0	0
T170	0	71	0	0
T171	0	57	0	0
T172	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	15	0	0
T41	96900	1	0	0
T84	14509	0	0	0
T119	2235	0	0	0
T120	1559	0	0	0
T125	0	1	0	0
T146	0	1	0	0
T151	0	2	0	0
T167	0	1	0	0
T170	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	405	0	0	0
T178	926	0	0	0
T179	422	0	0	0
T180	503	0	0	0
T181	21095	0	0	0
T182	422	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T8,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T12,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T11
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T8,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T37
0	1	Covered	T80,T151,T175
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T37
0	1	Covered	T1,T12,T153
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T12,T37
1	-	Covered	T1,T12,T153

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T12
DetectSt	168	Covered	T1,T12,T37
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T12,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T37
DebounceSt->IdleSt	163	Covered	T8,T87,T170
DetectSt->IdleSt	186	Covered	T80,T151,T175
DetectSt->StableSt	191	Covered	T1,T12,T37
IdleSt->DebounceSt	148	Covered	T1,T8,T12
StableSt->IdleSt	206	Covered	T1,T12,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T12
0	1	Covered	T1,T8,T12
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T37
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T87,T170
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T12
DetectSt	-	-	-	-	1	-	-	Covered	T80,T151,T175
DetectSt	-	-	-	-	0	1	-	Covered	T1,T12,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T12,T153
StableSt	-	-	-	-	-	-	0	Covered	T1,T12,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	139	0	0
CntIncr_A	7886385	86606	0	0
CntNoWrap_A	7886385	7229691	0	0
DetectStDropOut_A	7886385	4	0	0
DetectedOut_A	7886385	12005	0	0
DetectedPulseOut_A	7886385	62	0	0
DisabledIdleSt_A	7886385	7020092	0	0
DisabledNoDetection_A	7886385	7022374	0	0
EnterDebounceSt_A	7886385	73	0	0
EnterDetectSt_A	7886385	66	0	0
EnterStableSt_A	7886385	62	0	0
PulseIsPulse_A	7886385	62	0	0
StayInStableSt	7886385	11916	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7886385	3094	0	0
gen_low_level_sva.LowLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	139	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T12	0	4	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	2	0	0
T41	0	4	0	0
T87	0	3	0	0
T142	0	6	0	0
T153	0	2	0	0
T183	0	2	0	0
T184	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	86606	0	0
T1	3823	77	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	15	0	0
T12	0	44	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	12	0	0
T41	0	35550	0	0
T87	0	196	0	0
T142	0	132	0	0
T153	0	22	0	0
T183	0	90	0	0
T184	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229691	0	0
T1	3823	1416	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	4	0	0
T80	634	1	0	0
T125	20407	0	0	0
T129	0	1	0	0
T151	0	1	0	0
T175	0	1	0	0
T185	502	0	0	0
T186	404	0	0	0
T187	507	0	0	0
T188	404	0	0	0
T189	425	0	0	0
T190	456	0	0	0
T191	522	0	0	0
T192	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	12005	0	0
T1	3823	36	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	84	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	53	0	0
T41	0	6417	0	0
T87	0	39	0	0
T142	0	156	0	0
T153	0	14	0	0
T178	0	74	0	0
T183	0	52	0	0
T184	0	217	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	62	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	1	0	0
T41	0	2	0	0
T87	0	1	0	0
T142	0	3	0	0
T153	0	1	0	0
T178	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7020092	0	0
T1	3823	683	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7022374	0	0
T1	3823	687	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	73	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T12	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	1	0	0
T41	0	2	0	0
T87	0	2	0	0
T142	0	3	0	0
T153	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	66	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	1	0	0
T41	0	2	0	0
T87	0	1	0	0
T142	0	3	0	0
T153	0	1	0	0
T178	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	62	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	1	0	0
T41	0	2	0	0
T87	0	1	0	0
T142	0	3	0	0
T153	0	1	0	0
T178	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	62	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	1	0	0
T41	0	2	0	0
T87	0	1	0	0
T142	0	3	0	0
T153	0	1	0	0
T178	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	11916	0	0
T1	3823	35	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	81	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	51	0	0
T41	0	6414	0	0
T87	0	37	0	0
T142	0	152	0	0
T153	0	13	0	0
T178	0	73	0	0
T183	0	50	0	0
T184	0	215	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	3094	0	0
T1	3823	14	0	0
T4	502	6	0	0
T5	423	3	0	0
T6	0	2	0	0
T13	801	0	0	0
T14	502	6	0	0
T15	406	0	0	0
T16	527	5	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T50	0	4	0	0
T51	0	5	0	0
T52	0	3	0	0
T53	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	34	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T41	0	1	0	0
T142	0	2	0	0
T146	0	1	0	0
T153	0	1	0	0
T170	0	1	0	0
T172	0	1	0	0
T178	0	1	0	0
T193	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T11
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T11
0	1	Covered	T155,T144,T194
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T11
0	1	Covered	T1,T12,T34
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T11
1	-	Covered	T1,T12,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T11
DetectSt	168	Covered	T1,T8,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T11
DebounceSt->IdleSt	163	Covered	T11,T142,T41
DetectSt->IdleSt	186	Covered	T155,T144,T194
DetectSt->StableSt	191	Covered	T1,T8,T11
IdleSt->DebounceSt	148	Covered	T1,T8,T11
StableSt->IdleSt	206	Covered	T1,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T11
0	1	Covered	T1,T8,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T142,T41
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T155,T144,T194
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T12,T34
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	136	0	0
CntIncr_A	7886385	107135	0	0
CntNoWrap_A	7886385	7229694	0	0
DetectStDropOut_A	7886385	3	0	0
DetectedOut_A	7886385	41153	0	0
DetectedPulseOut_A	7886385	62	0	0
DisabledIdleSt_A	7886385	6958701	0	0
DisabledNoDetection_A	7886385	6960981	0	0
EnterDebounceSt_A	7886385	71	0	0
EnterDetectSt_A	7886385	65	0	0
EnterStableSt_A	7886385	62	0	0
PulseIsPulse_A	7886385	62	0	0
StayInStableSt	7886385	41064	0	0
gen_high_level_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	136	0	0
T1	3823	4	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	2	0	0
T11	0	3	0	0
T12	0	4	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	2	0	0
T37	0	2	0	0
T40	0	2	0	0
T41	0	3	0	0
T142	0	1	0	0
T184	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	107135	0	0
T1	3823	154	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	15	0	0
T11	0	6338	0	0
T12	0	44	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	47	0	0
T37	0	12	0	0
T40	0	75	0	0
T41	0	35550	0	0
T142	0	44	0	0
T184	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229694	0	0
T1	3823	1414	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	3	0	0
T144	0	1	0	0
T149	103711	0	0	0
T155	47813	1	0	0
T194	0	1	0	0
T195	6274	0	0	0
T196	522	0	0	0
T197	492	0	0	0
T198	4337	0	0	0
T199	1694	0	0	0
T200	409	0	0	0
T201	260061	0	0	0
T202	1052	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	41153	0	0
T1	3823	223	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	65	0	0
T11	0	7643	0	0
T12	0	136	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	1	0	0
T37	0	3	0	0
T40	0	332	0	0
T41	0	24185	0	0
T121	0	33	0	0
T184	0	103	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	62	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T121	0	1	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6958701	0	0
T1	3823	683	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6960981	0	0
T1	3823	687	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	71	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T142	0	1	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	65	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T121	0	1	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	62	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T121	0	1	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	62	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T121	0	1	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	41064	0	0
T1	3823	220	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	63	0	0
T11	0	7641	0	0
T12	0	134	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	2	0	0
T40	0	331	0	0
T41	0	24184	0	0
T54	0	9	0	0
T121	0	32	0	0
T184	0	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	34	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T121	0	1	0	0
T145	0	1	0	0
T184	0	1	0	0
T193	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T12,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T12,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T12,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T12
1	0	Covered	T1,T4,T14
1	1	Covered	T6,T12,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T12,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T12,T39
0	1	Covered	T12,T39,T86
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T12,T39
1	-	Covered	T12,T39,T86

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T12,T39
DetectSt	168	Covered	T6,T12,T39
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T12,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T12,T39
DebounceSt->IdleSt	163	Covered	T78
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6,T12,T39
IdleSt->DebounceSt	148	Covered	T6,T12,T39
StableSt->IdleSt	206	Covered	T12,T39,T86

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T12,T39
0	1	Covered	T6,T12,T39
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T12,T39
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T12,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T12,T39
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T12,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T6,T12,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T39,T86
StableSt	-	-	-	-	-	-	0	Covered	T6,T12,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	57	0	0
CntIncr_A	7886385	63049	0	0
CntNoWrap_A	7886385	7229773	0	0
DetectStDropOut_A	7886385	0	0	0
DetectedOut_A	7886385	17401	0	0
DetectedPulseOut_A	7886385	28	0	0
DisabledIdleSt_A	7886385	7027325	0	0
DisabledNoDetection_A	7886385	7029617	0	0
EnterDebounceSt_A	7886385	29	0	0
EnterDetectSt_A	7886385	28	0	0
EnterStableSt_A	7886385	28	0	0
PulseIsPulse_A	7886385	28	0	0
StayInStableSt	7886385	17358	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7886385	6626	0	0
gen_low_level_sva.LowLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	57	0	0
T6	686	2	0	0
T7	17776	0	0	0
T8	489	0	0	0
T12	0	4	0	0
T39	0	2	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T54	0	2	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	2	0	0
T142	0	2	0	0
T145	0	2	0	0
T155	0	4	0	0
T169	422	0	0	0
T170	0	4	0	0
T184	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	63049	0	0
T6	686	42	0	0
T7	17776	0	0	0
T8	489	0	0	0
T12	0	44	0	0
T39	0	78	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T54	0	20	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	74	0	0
T142	0	44	0	0
T145	0	65	0	0
T155	0	14652	0	0
T169	422	0	0	0
T170	0	154	0	0
T184	0	55	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229773	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	17401	0	0
T6	686	191	0	0
T7	17776	0	0	0
T8	489	0	0	0
T12	0	46	0	0
T39	0	43	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T54	0	10	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	139	0	0
T142	0	360	0	0
T145	0	162	0	0
T155	0	15493	0	0
T169	422	0	0	0
T170	0	111	0	0
T184	0	119	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	28	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T12	0	2	0	0
T39	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T54	0	1	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	1	0	0
T142	0	1	0	0
T145	0	1	0	0
T155	0	2	0	0
T169	422	0	0	0
T170	0	2	0	0
T184	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7027325	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7029617	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	29	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T12	0	2	0	0
T39	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T54	0	1	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	1	0	0
T142	0	1	0	0
T145	0	1	0	0
T155	0	2	0	0
T169	422	0	0	0
T170	0	2	0	0
T184	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	28	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T12	0	2	0	0
T39	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T54	0	1	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	1	0	0
T142	0	1	0	0
T145	0	1	0	0
T155	0	2	0	0
T169	422	0	0	0
T170	0	2	0	0
T184	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	28	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T12	0	2	0	0
T39	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T54	0	1	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	1	0	0
T142	0	1	0	0
T145	0	1	0	0
T155	0	2	0	0
T169	422	0	0	0
T170	0	2	0	0
T184	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	28	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T12	0	2	0	0
T39	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T54	0	1	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	1	0	0
T142	0	1	0	0
T145	0	1	0	0
T155	0	2	0	0
T169	422	0	0	0
T170	0	2	0	0
T184	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	17358	0	0
T6	686	189	0	0
T7	17776	0	0	0
T8	489	0	0	0
T12	0	43	0	0
T39	0	42	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T54	0	9	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	138	0	0
T142	0	358	0	0
T145	0	160	0	0
T155	0	15490	0	0
T169	422	0	0	0
T170	0	108	0	0
T184	0	115	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6626	0	0
T1	3823	12	0	0
T2	0	11	0	0
T3	0	32	0	0
T4	502	4	0	0
T5	423	0	0	0
T6	0	1	0	0
T13	801	0	0	0
T14	502	4	0	0
T15	406	0	0	0
T16	527	6	0	0
T17	782	0	0	0
T18	10193	20	0	0
T19	760	0	0	0
T51	0	4	0	0
T52	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	12	0	0
T12	45124	1	0	0
T24	233341	0	0	0
T34	39976	0	0	0
T39	0	1	0	0
T48	481	0	0	0
T58	1245	0	0	0
T63	440	0	0	0
T86	0	1	0	0
T137	25927	0	0	0
T138	425	0	0	0
T139	128684	0	0	0
T140	444	0	0	0
T149	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T170	0	1	0	0
T174	0	1	0	0
T176	0	1	0	0
T203	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T12,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T12
1	0	Covered	T1,T4,T5
1	1	Covered	T6,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T34
0	1	Covered	T80,T125,T204
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T34
0	1	Covered	T12,T40,T86
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T34
1	-	Covered	T12,T40,T86

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T11,T12
DetectSt	168	Covered	T11,T12,T34
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T11,T12,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T12,T34
DebounceSt->IdleSt	163	Covered	T6,T118,T205
DetectSt->IdleSt	186	Covered	T80,T125,T204
DetectSt->StableSt	191	Covered	T11,T12,T34
IdleSt->DebounceSt	148	Covered	T6,T11,T12
StableSt->IdleSt	206	Covered	T12,T34,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T11,T12
0	1	Covered	T6,T11,T12
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T34
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T12,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T118,T205
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T11,T12
DetectSt	-	-	-	-	1	-	-	Covered	T80,T125,T204
DetectSt	-	-	-	-	0	1	-	Covered	T11,T12,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T40,T86
StableSt	-	-	-	-	-	-	0	Covered	T11,T12,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	161	0	0
CntIncr_A	7886385	28241	0	0
CntNoWrap_A	7886385	7229669	0	0
DetectStDropOut_A	7886385	5	0	0
DetectedOut_A	7886385	5194	0	0
DetectedPulseOut_A	7886385	72	0	0
DisabledIdleSt_A	7886385	7068117	0	0
DisabledNoDetection_A	7886385	7070395	0	0
EnterDebounceSt_A	7886385	84	0	0
EnterDetectSt_A	7886385	77	0	0
EnterStableSt_A	7886385	72	0	0
PulseIsPulse_A	7886385	72	0	0
StayInStableSt	7886385	5087	0	0
gen_high_level_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	161	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	2	0	0
T12	0	4	0	0
T34	0	2	0	0
T40	0	4	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T54	0	2	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	4	0	0
T118	0	1	0	0
T145	0	2	0	0
T169	422	0	0	0
T184	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	28241	0	0
T6	686	42	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	31	0	0
T12	0	44	0	0
T34	0	47	0	0
T40	0	150	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T54	0	20	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	148	0	0
T118	0	52	0	0
T145	0	65	0	0
T169	422	0	0	0
T184	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229669	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	5	0	0
T80	634	1	0	0
T125	20407	1	0	0
T152	0	1	0	0
T185	502	0	0	0
T186	404	0	0	0
T187	507	0	0	0
T188	404	0	0	0
T189	425	0	0	0
T190	456	0	0	0
T191	522	0	0	0
T192	523	0	0	0
T204	0	1	0	0
T206	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	5194	0	0
T11	16131	149	0	0
T12	45124	95	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T34	0	41	0	0
T40	0	93	0	0
T42	15182	0	0	0
T54	0	9	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T86	0	89	0	0
T125	0	147	0	0
T145	0	337	0	0
T184	0	216	0	0
T192	0	76	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	72	0	0
T11	16131	1	0	0
T12	45124	2	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T34	0	1	0	0
T40	0	2	0	0
T42	15182	0	0	0
T54	0	1	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T86	0	2	0	0
T125	0	3	0	0
T145	0	1	0	0
T184	0	1	0	0
T192	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7068117	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7070395	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	84	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T34	0	1	0	0
T40	0	2	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T54	0	1	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	2	0	0
T118	0	1	0	0
T145	0	1	0	0
T169	422	0	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	77	0	0
T11	16131	1	0	0
T12	45124	2	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T34	0	1	0	0
T40	0	2	0	0
T42	15182	0	0	0
T54	0	1	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T80	0	1	0	0
T86	0	2	0	0
T125	0	4	0	0
T145	0	1	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	72	0	0
T11	16131	1	0	0
T12	45124	2	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T34	0	1	0	0
T40	0	2	0	0
T42	15182	0	0	0
T54	0	1	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T86	0	2	0	0
T125	0	3	0	0
T145	0	1	0	0
T184	0	1	0	0
T192	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	72	0	0
T11	16131	1	0	0
T12	45124	2	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T34	0	1	0	0
T40	0	2	0	0
T42	15182	0	0	0
T54	0	1	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T86	0	2	0	0
T125	0	3	0	0
T145	0	1	0	0
T184	0	1	0	0
T192	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	5087	0	0
T11	16131	147	0	0
T12	45124	92	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T34	0	39	0	0
T40	0	90	0	0
T42	15182	0	0	0
T54	0	8	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T86	0	86	0	0
T125	0	143	0	0
T145	0	335	0	0
T184	0	214	0	0
T192	0	74	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	36	0	0
T12	45124	1	0	0
T24	233341	0	0	0
T34	39976	0	0	0
T40	0	1	0	0
T48	481	0	0	0
T58	1245	0	0	0
T63	440	0	0	0
T86	0	1	0	0
T98	0	1	0	0
T125	0	2	0	0
T137	25927	0	0	0
T138	425	0	0	0
T139	128684	0	0	0
T140	444	0	0	0
T147	0	1	0	0
T151	0	2	0	0
T168	0	2	0	0
T170	0	3	0	0
T207	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T11
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T11
0	1	Covered	T151,T175
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T11
0	1	Covered	T1,T12,T40
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T11
1	-	Covered	T1,T12,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T11
DetectSt	168	Covered	T1,T8,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T11
DebounceSt->IdleSt	163	Covered	T78
DetectSt->IdleSt	186	Covered	T151,T175
DetectSt->StableSt	191	Covered	T1,T8,T11
IdleSt->DebounceSt	148	Covered	T1,T8,T11
StableSt->IdleSt	206	Covered	T1,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T11
0	1	Covered	T1,T8,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T11
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T151,T175
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T12,T40
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	81	0	0
CntIncr_A	7886385	40969	0	0
CntNoWrap_A	7886385	7229749	0	0
DetectStDropOut_A	7886385	2	0	0
DetectedOut_A	7886385	11506	0	0
DetectedPulseOut_A	7886385	38	0	0
DisabledIdleSt_A	7886385	7053721	0	0
DisabledNoDetection_A	7886385	7056003	0	0
EnterDebounceSt_A	7886385	41	0	0
EnterDetectSt_A	7886385	40	0	0
EnterStableSt_A	7886385	38	0	0
PulseIsPulse_A	7886385	38	0	0
StayInStableSt	7886385	11452	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7886385	6272	0	0
gen_low_level_sva.LowLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	81	0	0
T1	3823	4	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	2	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T54	0	2	0	0
T86	0	2	0	0
T87	0	4	0	0
T153	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	40969	0	0
T1	3823	154	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	15	0	0
T11	0	6307	0	0
T12	0	22	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T40	0	75	0	0
T41	0	17775	0	0
T54	0	20	0	0
T86	0	74	0	0
T87	0	196	0	0
T153	0	22	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229749	0	0
T1	3823	1414	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	2	0	0
T151	865	1	0	0
T158	701	0	0	0
T159	16293	0	0	0
T160	5691	0	0	0
T161	10184	0	0	0
T162	421	0	0	0
T163	424	0	0	0
T164	521	0	0	0
T165	491	0	0	0
T166	507	0	0	0
T175	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	11506	0	0
T1	3823	80	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	49	0	0
T11	0	37	0	0
T12	0	70	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T40	0	53	0	0
T41	0	9563	0	0
T54	0	10	0	0
T86	0	20	0	0
T87	0	71	0	0
T153	0	59	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	38	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T54	0	1	0	0
T86	0	1	0	0
T87	0	2	0	0
T153	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7053721	0	0
T1	3823	683	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7056003	0	0
T1	3823	687	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	41	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T54	0	1	0	0
T86	0	1	0	0
T87	0	2	0	0
T153	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	40	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T54	0	1	0	0
T86	0	1	0	0
T87	0	2	0	0
T153	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	38	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T54	0	1	0	0
T86	0	1	0	0
T87	0	2	0	0
T153	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	38	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T54	0	1	0	0
T86	0	1	0	0
T87	0	2	0	0
T153	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	11452	0	0
T1	3823	78	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	47	0	0
T11	0	35	0	0
T12	0	69	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T40	0	52	0	0
T41	0	9561	0	0
T54	0	9	0	0
T86	0	19	0	0
T87	0	69	0	0
T153	0	57	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6272	0	0
T1	3823	11	0	0
T2	0	8	0	0
T3	0	27	0	0
T4	502	5	0	0
T5	423	3	0	0
T6	0	1	0	0
T13	801	0	0	0
T14	502	5	0	0
T15	406	0	0	0
T16	527	4	0	0
T17	782	0	0	0
T18	10193	29	0	0
T19	760	0	0	0
T51	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	21	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T12	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T40	0	1	0	0
T86	0	1	0	0
T87	0	2	0	0
T125	0	1	0	0
T143	0	1	0	0
T146	0	1	0	0
T155	0	1	0	0
T170	0	2	0	0