Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T11,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T11,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T11,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T33
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T11,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T33
0	1	Covered	T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T33
0	1	Covered	T11,T33,T38
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T33
1	-	Covered	T11,T33,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T11,T33
DetectSt	168	Covered	T1,T11,T33
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T11,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T11,T33
DebounceSt->IdleSt	163	Covered	T142,T157,T193
DetectSt->IdleSt	186	Covered	T86
DetectSt->StableSt	191	Covered	T1,T11,T33
IdleSt->DebounceSt	148	Covered	T1,T11,T33
StableSt->IdleSt	206	Covered	T1,T11,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T11,T33
0	1	Covered	T1,T11,T33
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T33
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T11,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T11,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T142,T157,T193
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T11,T33
DetectSt	-	-	-	-	1	-	-	Covered	T86
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T33,T38
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	139	0	0
CntIncr_A	7886385	92711	0	0
CntNoWrap_A	7886385	7229691	0	0
DetectStDropOut_A	7886385	1	0	0
DetectedOut_A	7886385	59056	0	0
DetectedPulseOut_A	7886385	65	0	0
DisabledIdleSt_A	7886385	7005341	0	0
DisabledNoDetection_A	7886385	7007616	0	0
EnterDebounceSt_A	7886385	74	0	0
EnterDetectSt_A	7886385	66	0	0
EnterStableSt_A	7886385	65	0	0
PulseIsPulse_A	7886385	65	0	0
StayInStableSt	7886385	58954	0	0
gen_high_level_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	139	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T11	0	4	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T33	0	4	0	0
T38	0	4	0	0
T41	0	4	0	0
T86	0	4	0	0
T142	0	5	0	0
T157	0	1	0	0
T178	0	4	0	0
T183	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	92711	0	0
T1	3823	77	0	0
T4	502	0	0	0
T5	423	0	0	0
T11	0	6338	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T33	0	22	0	0
T38	0	64	0	0
T41	0	35550	0	0
T86	0	148	0	0
T142	0	132	0	0
T157	0	41	0	0
T178	0	172	0	0
T183	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229691	0	0
T1	3823	1416	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	1	0	0
T86	816	1	0	0
T208	503	0	0	0
T209	522	0	0	0
T210	449	0	0	0
T211	426	0	0	0
T212	7523	0	0	0
T213	723	0	0	0
T214	12810	0	0	0
T215	403	0	0	0
T216	440	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	59056	0	0
T1	3823	304	0	0
T4	502	0	0	0
T5	423	0	0	0
T11	0	1340	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T33	0	58	0	0
T38	0	80	0	0
T41	0	51563	0	0
T54	0	9	0	0
T86	0	141	0	0
T142	0	52	0	0
T178	0	79	0	0
T183	0	77	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	65	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T11	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T33	0	2	0	0
T38	0	2	0	0
T41	0	2	0	0
T54	0	1	0	0
T86	0	1	0	0
T142	0	2	0	0
T178	0	2	0	0
T183	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7005341	0	0
T1	3823	683	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7007616	0	0
T1	3823	687	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	74	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T11	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T33	0	2	0	0
T38	0	2	0	0
T41	0	2	0	0
T86	0	2	0	0
T142	0	3	0	0
T157	0	1	0	0
T178	0	2	0	0
T183	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	66	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T11	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T33	0	2	0	0
T38	0	2	0	0
T41	0	2	0	0
T54	0	1	0	0
T86	0	2	0	0
T142	0	2	0	0
T178	0	2	0	0
T183	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	65	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T11	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T33	0	2	0	0
T38	0	2	0	0
T41	0	2	0	0
T54	0	1	0	0
T86	0	1	0	0
T142	0	2	0	0
T178	0	2	0	0
T183	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	65	0	0
T1	3823	1	0	0
T4	502	0	0	0
T5	423	0	0	0
T11	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T33	0	2	0	0
T38	0	2	0	0
T41	0	2	0	0
T54	0	1	0	0
T86	0	1	0	0
T142	0	2	0	0
T178	0	2	0	0
T183	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	58954	0	0
T1	3823	302	0	0
T4	502	0	0	0
T5	423	0	0	0
T11	0	1338	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T33	0	55	0	0
T38	0	77	0	0
T41	0	51560	0	0
T54	0	8	0	0
T86	0	139	0	0
T142	0	50	0	0
T178	0	76	0	0
T183	0	75	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	27	0	0
T11	16131	2	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	15182	0	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T82	0	1	0	0
T142	0	2	0	0
T168	0	1	0	0
T170	0	1	0	0
T178	0	1	0	0
T193	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T12,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T39,T40
1	0	Covered	T1,T4,T5
1	1	Covered	T12,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T39,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T39,T40
0	1	Covered	T142,T193,T146
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T39,T40
1	-	Covered	T142,T193,T146

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T39,T40
DetectSt	168	Covered	T12,T39,T40
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T12,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T39,T40
DebounceSt->IdleSt	163	Covered	T41,T78
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T12,T39,T40
IdleSt->DebounceSt	148	Covered	T12,T39,T40
StableSt->IdleSt	206	Covered	T12,T142,T87

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T39,T40
0	1	Covered	T12,T39,T40
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T39,T40
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T41
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T39,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T142,T54,T193
StableSt	-	-	-	-	-	-	0	Covered	T12,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	66	0	0
CntIncr_A	7886385	19572	0	0
CntNoWrap_A	7886385	7229764	0	0
DetectStDropOut_A	7886385	0	0	0
DetectedOut_A	7886385	2427	0	0
DetectedPulseOut_A	7886385	32	0	0
DisabledIdleSt_A	7886385	7118149	0	0
DisabledNoDetection_A	7886385	7120444	0	0
EnterDebounceSt_A	7886385	34	0	0
EnterDetectSt_A	7886385	32	0	0
EnterStableSt_A	7886385	32	0	0
PulseIsPulse_A	7886385	32	0	0
StayInStableSt	7886385	2375	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7886385	6244	0	0
gen_low_level_sva.LowLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	66	0	0
T12	45124	2	0	0
T24	233341	0	0	0
T34	39976	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T48	481	0	0	0
T54	0	2	0	0
T58	1245	0	0	0
T63	440	0	0	0
T87	0	2	0	0
T125	0	2	0	0
T137	25927	0	0	0
T138	425	0	0	0
T139	128684	0	0	0
T140	444	0	0	0
T142	0	6	0	0
T157	0	2	0	0
T193	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	19572	0	0
T12	45124	22	0	0
T24	233341	0	0	0
T34	39976	0	0	0
T39	0	78	0	0
T40	0	75	0	0
T41	0	17775	0	0
T48	481	0	0	0
T54	0	20	0	0
T58	1245	0	0	0
T63	440	0	0	0
T87	0	98	0	0
T125	0	22	0	0
T137	25927	0	0	0
T138	425	0	0	0
T139	128684	0	0	0
T140	444	0	0	0
T142	0	132	0	0
T157	0	41	0	0
T193	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229764	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	2427	0	0
T12	45124	211	0	0
T24	233341	0	0	0
T34	39976	0	0	0
T39	0	47	0	0
T40	0	297	0	0
T48	481	0	0	0
T54	0	11	0	0
T58	1245	0	0	0
T63	440	0	0	0
T87	0	612	0	0
T125	0	79	0	0
T137	25927	0	0	0
T138	425	0	0	0
T139	128684	0	0	0
T140	444	0	0	0
T142	0	128	0	0
T146	0	127	0	0
T157	0	39	0	0
T193	0	21	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	32	0	0
T12	45124	1	0	0
T24	233341	0	0	0
T34	39976	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T48	481	0	0	0
T54	0	1	0	0
T58	1245	0	0	0
T63	440	0	0	0
T87	0	1	0	0
T125	0	1	0	0
T137	25927	0	0	0
T138	425	0	0	0
T139	128684	0	0	0
T140	444	0	0	0
T142	0	3	0	0
T146	0	3	0	0
T157	0	1	0	0
T193	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7118149	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7120444	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	34	0	0
T12	45124	1	0	0
T24	233341	0	0	0
T34	39976	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T48	481	0	0	0
T54	0	1	0	0
T58	1245	0	0	0
T63	440	0	0	0
T87	0	1	0	0
T125	0	1	0	0
T137	25927	0	0	0
T138	425	0	0	0
T139	128684	0	0	0
T140	444	0	0	0
T142	0	3	0	0
T157	0	1	0	0
T193	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	32	0	0
T12	45124	1	0	0
T24	233341	0	0	0
T34	39976	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T48	481	0	0	0
T54	0	1	0	0
T58	1245	0	0	0
T63	440	0	0	0
T87	0	1	0	0
T125	0	1	0	0
T137	25927	0	0	0
T138	425	0	0	0
T139	128684	0	0	0
T140	444	0	0	0
T142	0	3	0	0
T146	0	3	0	0
T157	0	1	0	0
T193	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	32	0	0
T12	45124	1	0	0
T24	233341	0	0	0
T34	39976	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T48	481	0	0	0
T54	0	1	0	0
T58	1245	0	0	0
T63	440	0	0	0
T87	0	1	0	0
T125	0	1	0	0
T137	25927	0	0	0
T138	425	0	0	0
T139	128684	0	0	0
T140	444	0	0	0
T142	0	3	0	0
T146	0	3	0	0
T157	0	1	0	0
T193	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	32	0	0
T12	45124	1	0	0
T24	233341	0	0	0
T34	39976	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T48	481	0	0	0
T54	0	1	0	0
T58	1245	0	0	0
T63	440	0	0	0
T87	0	1	0	0
T125	0	1	0	0
T137	25927	0	0	0
T138	425	0	0	0
T139	128684	0	0	0
T140	444	0	0	0
T142	0	3	0	0
T146	0	3	0	0
T157	0	1	0	0
T193	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	2375	0	0
T12	45124	209	0	0
T24	233341	0	0	0
T34	39976	0	0	0
T39	0	45	0	0
T40	0	295	0	0
T48	481	0	0	0
T54	0	10	0	0
T58	1245	0	0	0
T63	440	0	0	0
T87	0	610	0	0
T125	0	77	0	0
T137	25927	0	0	0
T138	425	0	0	0
T139	128684	0	0	0
T140	444	0	0	0
T142	0	124	0	0
T146	0	123	0	0
T157	0	37	0	0
T193	0	20	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6244	0	0
T1	3823	7	0	0
T2	0	14	0	0
T3	0	27	0	0
T4	502	6	0	0
T5	423	1	0	0
T6	0	1	0	0
T13	801	0	0	0
T14	502	6	0	0
T15	406	0	0	0
T16	527	5	0	0
T17	782	0	0	0
T18	10193	32	0	0
T19	760	0	0	0
T51	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	11	0	0
T118	11915	0	0	0
T142	843	2	0	0
T146	0	2	0	0
T147	0	1	0	0
T150	0	1	0	0
T173	0	1	0	0
T174	0	2	0	0
T184	5671	0	0	0
T193	0	1	0	0
T203	0	1	0	0
T217	494	0	0	0
T218	406	0	0	0
T219	465	0	0	0
T220	667	0	0	0
T221	423	0	0	0
T222	25936	0	0	0
T223	826	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T11
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T11
0	1	Covered	T151,T173
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T38
0	1	Covered	T1,T11,T37
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T38
1	-	Covered	T1,T11,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T11
DetectSt	168	Covered	T1,T8,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T11
DebounceSt->IdleSt	163	Covered	T184,T173,T175
DetectSt->IdleSt	186	Covered	T151,T173
DetectSt->StableSt	191	Covered	T1,T8,T11
IdleSt->DebounceSt	148	Covered	T1,T8,T11
StableSt->IdleSt	206	Covered	T1,T11,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T11
0	1	Covered	T1,T8,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T184,T173,T175
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T151,T173
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T11,T37
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	108	0	0
CntIncr_A	7886385	76198	0	0
CntNoWrap_A	7886385	7229722	0	0
DetectStDropOut_A	7886385	2	0	0
DetectedOut_A	7886385	34071	0	0
DetectedPulseOut_A	7886385	50	0	0
DisabledIdleSt_A	7886385	6930532	0	0
DisabledNoDetection_A	7886385	6932821	0	0
EnterDebounceSt_A	7886385	56	0	0
EnterDetectSt_A	7886385	52	0	0
EnterStableSt_A	7886385	50	0	0
PulseIsPulse_A	7886385	50	0	0
StayInStableSt	7886385	33996	0	0
gen_high_level_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	108	0	0
T1	3823	4	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	2	0	0
T11	0	2	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T41	0	4	0	0
T54	0	2	0	0
T154	0	4	0	0
T184	0	1	0	0
T224	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	76198	0	0
T1	3823	154	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	15	0	0
T11	0	31	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	12	0	0
T38	0	32	0	0
T41	0	35550	0	0
T54	0	20	0	0
T154	0	122	0	0
T184	0	22	0	0
T224	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229722	0	0
T1	3823	1414	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	2	0	0
T151	865	1	0	0
T158	701	0	0	0
T159	16293	0	0	0
T160	5691	0	0	0
T161	10184	0	0	0
T162	421	0	0	0
T163	424	0	0	0
T164	521	0	0	0
T165	491	0	0	0
T166	507	0	0	0
T173	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	34071	0	0
T1	3823	223	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	65	0	0
T11	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	1	0	0
T38	0	77	0	0
T41	0	93	0	0
T54	0	11	0	0
T145	0	109	0	0
T154	0	256	0	0
T224	0	83	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	50	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	2	0	0
T54	0	1	0	0
T145	0	1	0	0
T154	0	2	0	0
T224	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6930532	0	0
T1	3823	683	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6932821	0	0
T1	3823	687	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	56	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	2	0	0
T54	0	1	0	0
T154	0	2	0	0
T184	0	1	0	0
T224	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	52	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	2	0	0
T54	0	1	0	0
T145	0	1	0	0
T154	0	2	0	0
T224	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	50	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	2	0	0
T54	0	1	0	0
T145	0	1	0	0
T154	0	2	0	0
T224	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	50	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	2	0	0
T54	0	1	0	0
T145	0	1	0	0
T154	0	2	0	0
T224	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	33996	0	0
T1	3823	221	0	0
T4	502	0	0	0
T5	423	0	0	0
T8	0	63	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T38	0	75	0	0
T41	0	90	0	0
T54	0	10	0	0
T125	0	222	0	0
T145	0	108	0	0
T154	0	253	0	0
T224	0	80	0	0
T225	0	60	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	24	0	0
T1	3823	2	0	0
T4	502	0	0	0
T5	423	0	0	0
T11	0	1	0	0
T13	801	0	0	0
T14	502	0	0	0
T15	406	0	0	0
T16	527	0	0	0
T17	782	0	0	0
T18	10193	0	0	0
T19	760	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T81	0	1	0	0
T125	0	2	0	0
T145	0	1	0	0
T154	0	1	0	0
T170	0	1	0	0
T224	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T11,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T11,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T11,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T11
1	0	Covered	T1,T4,T5
1	1	Covered	T6,T11,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T37
0	1	Covered	T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T37
0	1	Covered	T6,T40,T154
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T11,T37
1	-	Covered	T6,T40,T154

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T11,T37
DetectSt	168	Covered	T6,T11,T37
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T11,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T11,T37
DebounceSt->IdleSt	163	Covered	T226,T78
DetectSt->IdleSt	186	Covered	T82
DetectSt->StableSt	191	Covered	T6,T11,T37
IdleSt->DebounceSt	148	Covered	T6,T11,T37
StableSt->IdleSt	206	Covered	T6,T37,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T11,T37
0	1	Covered	T6,T11,T37
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T11,T37
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T11,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T11,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T226
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T11,T37
DetectSt	-	-	-	-	1	-	-	Covered	T82
DetectSt	-	-	-	-	0	1	-	Covered	T6,T11,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T40,T154
StableSt	-	-	-	-	-	-	0	Covered	T6,T11,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	74	0	0
CntIncr_A	7886385	19932	0	0
CntNoWrap_A	7886385	7229756	0	0
DetectStDropOut_A	7886385	1	0	0
DetectedOut_A	7886385	21078	0	0
DetectedPulseOut_A	7886385	35	0	0
DisabledIdleSt_A	7886385	7057819	0	0
DisabledNoDetection_A	7886385	7060103	0	0
EnterDebounceSt_A	7886385	38	0	0
EnterDetectSt_A	7886385	36	0	0
EnterStableSt_A	7886385	35	0	0
PulseIsPulse_A	7886385	35	0	0
StayInStableSt	7886385	21022	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7886385	6303	0	0
gen_low_level_sva.LowLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	74	0	0
T6	686	2	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	2	0	0
T37	0	2	0	0
T40	0	4	0	0
T41	0	2	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T121	0	2	0	0
T153	0	2	0	0
T154	0	2	0	0
T157	0	2	0	0
T169	422	0	0	0
T184	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	19932	0	0
T6	686	42	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	31	0	0
T37	0	12	0	0
T40	0	150	0	0
T41	0	17775	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T121	0	83	0	0
T153	0	22	0	0
T154	0	61	0	0
T157	0	41	0	0
T169	422	0	0	0
T184	0	22	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229756	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	1	0	0
T82	894	1	0	0
T96	42442	0	0	0
T97	12365	0	0	0
T227	422	0	0	0
T228	1703	0	0	0
T229	629	0	0	0
T230	23479	0	0	0
T231	589	0	0	0
T232	2616	0	0	0
T233	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	21078	0	0
T6	686	39	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	42	0	0
T37	0	39	0	0
T40	0	187	0	0
T41	0	18928	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T121	0	37	0	0
T153	0	60	0	0
T154	0	34	0	0
T157	0	39	0	0
T169	422	0	0	0
T184	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	35	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	1	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T121	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T157	0	1	0	0
T169	422	0	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7057819	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7060103	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	38	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	1	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T121	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T157	0	1	0	0
T169	422	0	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	36	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	1	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T121	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T157	0	1	0	0
T169	422	0	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	35	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	1	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T121	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T157	0	1	0	0
T169	422	0	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	35	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	1	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T121	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T157	0	1	0	0
T169	422	0	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	21022	0	0
T6	686	38	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	40	0	0
T37	0	37	0	0
T40	0	184	0	0
T41	0	18927	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T121	0	35	0	0
T153	0	58	0	0
T154	0	33	0	0
T157	0	37	0	0
T169	422	0	0	0
T184	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6303	0	0
T1	3823	10	0	0
T2	0	11	0	0
T3	0	34	0	0
T4	502	4	0	0
T5	423	2	0	0
T6	0	1	0	0
T13	801	0	0	0
T14	502	4	0	0
T15	406	0	0	0
T16	527	3	0	0
T17	782	0	0	0
T18	10193	28	0	0
T19	760	0	0	0
T51	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	13	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T125	0	1	0	0
T144	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T169	422	0	0	0
T174	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T12
1	0	Covered	T1,T4,T5
1	1	Covered	T6,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T12
0	1	Covered	T6,T234,T235
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T12
0	1	Covered	T6,T11,T12
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T11,T12
1	-	Covered	T6,T11,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T11,T12
DetectSt	168	Covered	T6,T11,T12
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T11,T12
DebounceSt->IdleSt	163	Covered	T192,T236,T78
DetectSt->IdleSt	186	Covered	T6,T234,T235
DetectSt->StableSt	191	Covered	T6,T11,T12
IdleSt->DebounceSt	148	Covered	T6,T11,T12
StableSt->IdleSt	206	Covered	T6,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T11,T12
0	1	Covered	T6,T11,T12
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T11,T12
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T192,T236,T237
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T11,T12
DetectSt	-	-	-	-	1	-	-	Covered	T6,T234,T235
DetectSt	-	-	-	-	0	1	-	Covered	T6,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T11,T12
StableSt	-	-	-	-	-	-	0	Covered	T6,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	146	0	0
CntIncr_A	7886385	82480	0	0
CntNoWrap_A	7886385	7229684	0	0
DetectStDropOut_A	7886385	4	0	0
DetectedOut_A	7886385	123615	0	0
DetectedPulseOut_A	7886385	67	0	0
DisabledIdleSt_A	7886385	6958530	0	0
DisabledNoDetection_A	7886385	6960810	0	0
EnterDebounceSt_A	7886385	75	0	0
EnterDetectSt_A	7886385	71	0	0
EnterStableSt_A	7886385	67	0	0
PulseIsPulse_A	7886385	67	0	0
StayInStableSt	7886385	123519	0	0
gen_high_level_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	146	0	0
T6	686	4	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	2	0	0
T12	0	4	0	0
T33	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	2	0	0
T153	0	4	0	0
T169	422	0	0	0
T183	0	2	0	0
T184	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	82480	0	0
T6	686	84	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	6307	0	0
T12	0	44	0	0
T33	0	11	0	0
T39	0	78	0	0
T40	0	75	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	74	0	0
T153	0	44	0	0
T169	422	0	0	0
T183	0	90	0	0
T184	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229684	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	4	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T169	422	0	0	0
T194	0	1	0	0
T234	0	1	0	0
T235	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	123615	0	0
T6	686	25	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	1297	0	0
T12	0	162	0	0
T33	0	6	0	0
T39	0	379	0	0
T40	0	137	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	258	0	0
T153	0	100	0	0
T169	422	0	0	0
T183	0	78	0	0
T184	0	217	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	67	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T33	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	1	0	0
T153	0	2	0	0
T169	422	0	0	0
T183	0	1	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6958530	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6960810	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	75	0	0
T6	686	2	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T33	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	1	0	0
T153	0	2	0	0
T169	422	0	0	0
T183	0	1	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	71	0	0
T6	686	2	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T33	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	1	0	0
T153	0	2	0	0
T169	422	0	0	0
T183	0	1	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	67	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T33	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	1	0	0
T153	0	2	0	0
T169	422	0	0	0
T183	0	1	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	67	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T33	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	1	0	0
T153	0	2	0	0
T169	422	0	0	0
T183	0	1	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	123519	0	0
T6	686	24	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	1296	0	0
T12	0	159	0	0
T33	0	5	0	0
T39	0	377	0	0
T40	0	136	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T86	0	256	0	0
T153	0	97	0	0
T169	422	0	0	0
T183	0	76	0	0
T184	0	215	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	37	0	0
T6	686	1	0	0
T7	17776	0	0	0
T8	489	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T33	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T70	506	0	0	0
T87	0	2	0	0
T153	0	1	0	0
T169	422	0	0	0
T178	0	1	0	0
T193	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T37,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T11,T37,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T37
1	0	Covered	T1,T4,T5
1	1	Covered	T11,T37,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T37,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T37,T38
0	1	Covered	T154,T178,T170
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T37,T38
1	-	Covered	T154,T178,T170

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T37,T38
DetectSt	168	Covered	T11,T37,T38
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T11,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T37,T38
DebounceSt->IdleSt	163	Covered	T78
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T37,T38
IdleSt->DebounceSt	148	Covered	T11,T37,T38
StableSt->IdleSt	206	Covered	T11,T37,T154

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T37,T38
0	1	Covered	T11,T37,T38
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T37,T38
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T37,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T37,T38
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T37,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T154,T178,T54
StableSt	-	-	-	-	-	-	0	Covered	T11,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	91	0	0
CntIncr_A	7886385	31753	0	0
CntNoWrap_A	7886385	7229739	0	0
DetectStDropOut_A	7886385	0	0	0
DetectedOut_A	7886385	3107	0	0
DetectedPulseOut_A	7886385	45	0	0
DisabledIdleSt_A	7886385	7105155	0	0
DisabledNoDetection_A	7886385	7107438	0	0
EnterDebounceSt_A	7886385	46	0	0
EnterDetectSt_A	7886385	45	0	0
EnterStableSt_A	7886385	45	0	0
PulseIsPulse_A	7886385	45	0	0
StayInStableSt	7886385	3036	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7886385	6949	0	0
gen_low_level_sva.LowLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	91	0	0
T11	16131	2	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T42	15182	0	0	0
T54	0	2	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T145	0	2	0	0
T154	0	4	0	0
T157	0	2	0	0
T178	0	2	0	0
T193	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	31753	0	0
T11	16131	6307	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T37	0	12	0	0
T38	0	32	0	0
T40	0	75	0	0
T42	15182	0	0	0
T54	0	20	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T145	0	65	0	0
T154	0	122	0	0
T157	0	41	0	0
T178	0	86	0	0
T193	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229739	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	3107	0	0
T11	16131	37	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T37	0	38	0	0
T38	0	44	0	0
T40	0	298	0	0
T42	15182	0	0	0
T54	0	11	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T145	0	163	0	0
T154	0	93	0	0
T157	0	39	0	0
T178	0	74	0	0
T193	0	48	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	45	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	15182	0	0	0
T54	0	1	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T145	0	1	0	0
T154	0	2	0	0
T157	0	1	0	0
T178	0	1	0	0
T193	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7105155	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7107438	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	46	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	15182	0	0	0
T54	0	1	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T145	0	1	0	0
T154	0	2	0	0
T157	0	1	0	0
T178	0	1	0	0
T193	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	45	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	15182	0	0	0
T54	0	1	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T145	0	1	0	0
T154	0	2	0	0
T157	0	1	0	0
T178	0	1	0	0
T193	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	45	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	15182	0	0	0
T54	0	1	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T145	0	1	0	0
T154	0	2	0	0
T157	0	1	0	0
T178	0	1	0	0
T193	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	45	0	0
T11	16131	1	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	15182	0	0	0
T54	0	1	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T145	0	1	0	0
T154	0	2	0	0
T157	0	1	0	0
T178	0	1	0	0
T193	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	3036	0	0
T11	16131	35	0	0
T12	45124	0	0	0
T23	1426	0	0	0
T24	233341	0	0	0
T26	498	0	0	0
T32	36601	0	0	0
T37	0	36	0	0
T38	0	42	0	0
T40	0	296	0	0
T42	15182	0	0	0
T54	0	10	0	0
T57	779	0	0	0
T62	423	0	0	0
T63	440	0	0	0
T145	0	161	0	0
T154	0	90	0	0
T157	0	37	0	0
T178	0	73	0	0
T193	0	46	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6949	0	0
T1	3823	17	0	0
T4	502	5	0	0
T5	423	1	0	0
T13	801	3	0	0
T14	502	5	0	0
T15	406	0	0	0
T16	527	5	0	0
T17	782	3	0	0
T18	10193	28	0	0
T19	760	3	0	0
T43	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	18	0	0
T86	816	0	0	0
T144	0	2	0	0
T146	0	2	0	0
T149	0	1	0	0
T151	0	1	0	0
T154	947	1	0	0
T168	0	1	0	0
T170	0	1	0	0
T178	0	1	0	0
T203	0	1	0	0
T208	503	0	0	0
T209	522	0	0	0
T210	449	0	0	0
T211	426	0	0	0
T212	7523	0	0	0
T236	0	1	0	0
T238	492	0	0	0
T239	525	0	0	0
T240	502	0	0	0