Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T3,T9
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T3,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T3,T9
1	0	Covered	T18,T3,T9
1	1	Covered	T18,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T3,T9
0	1	Covered	T49,T74,T89
1	0	Covered	T42,T49,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T3,T9
0	1	Covered	T18,T3,T9
1	0	Covered	T54,T241

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T3,T9
1	-	Covered	T18,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T3,T9
DetectSt	168	Covered	T18,T3,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T18,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T3,T9
DebounceSt->IdleSt	163	Covered	T242,T54,T94
DetectSt->IdleSt	186	Covered	T42,T49,T74
DetectSt->StableSt	191	Covered	T18,T3,T9
IdleSt->DebounceSt	148	Covered	T18,T3,T9
StableSt->IdleSt	206	Covered	T18,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T3,T9
0	1	Covered	T18,T3,T9
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T3,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T18,T3,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T3,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T242,T54,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T3,T9
DetectSt	-	-	-	-	1	-	-	Covered	T42,T49,T74
DetectSt	-	-	-	-	0	1	-	Covered	T18,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T18,T3,T9
StableSt	-	-	-	-	-	-	1	Covered	T18,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T18,T3,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	2989	0	0
CntIncr_A	7886385	103633	0	0
CntNoWrap_A	7886385	7226841	0	0
DetectStDropOut_A	7886385	420	0	0
DetectedOut_A	7886385	73467	0	0
DetectedPulseOut_A	7886385	794	0	0
DisabledIdleSt_A	7886385	6779841	0	0
DisabledNoDetection_A	7886385	6782019	0	0
EnterDebounceSt_A	7886385	1513	0	0
EnterDetectSt_A	7886385	1477	0	0
EnterStableSt_A	7886385	794	0	0
PulseIsPulse_A	7886385	794	0	0
StayInStableSt	7886385	72602	0	0
gen_high_event_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_high_level_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	721	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	2989	0	0
T2	15250	0	0	0
T3	25650	24	0	0
T6	686	0	0	0
T9	0	20	0	0
T18	10193	40	0	0
T19	760	0	0	0
T35	0	6	0	0
T42	0	30	0	0
T43	737	0	0	0
T49	0	22	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	30	0	0
T72	0	24	0	0
T73	0	2	0	0
T74	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	103633	0	0
T2	15250	0	0	0
T3	25650	804	0	0
T6	686	0	0	0
T9	0	540	0	0
T18	10193	1060	0	0
T19	760	0	0	0
T35	0	168	0	0
T42	0	852	0	0
T43	737	0	0	0
T49	0	4738	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	930	0	0
T72	0	624	0	0
T73	0	21	0	0
T74	0	1147	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7226841	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9750	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	420	0	0
T37	12758	0	0	0
T49	39327	6	0	0
T54	0	1	0	0
T71	13315	0	0	0
T72	16268	0	0	0
T73	475	0	0	0
T74	0	23	0	0
T84	0	4	0	0
T89	0	14	0	0
T90	0	20	0	0
T91	0	13	0	0
T92	0	13	0	0
T93	0	1	0	0
T94	0	7	0	0
T116	53091	0	0	0
T130	422	0	0	0
T243	1043	0	0	0
T244	433	0	0	0
T245	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	73467	0	0
T2	15250	0	0	0
T3	25650	1311	0	0
T6	686	0	0	0
T9	0	363	0	0
T18	10193	2077	0	0
T19	760	0	0	0
T35	0	477	0	0
T43	737	0	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	262	0	0
T72	0	961	0	0
T73	0	50	0	0
T75	0	750	0	0
T83	0	126	0	0
T246	0	1974	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	794	0	0
T2	15250	0	0	0
T3	25650	12	0	0
T6	686	0	0	0
T9	0	10	0	0
T18	10193	20	0	0
T19	760	0	0	0
T35	0	3	0	0
T43	737	0	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	15	0	0
T72	0	12	0	0
T73	0	1	0	0
T75	0	18	0	0
T83	0	11	0	0
T246	0	32	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6779841	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	4044	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6782019	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	4044	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	1513	0	0
T2	15250	0	0	0
T3	25650	12	0	0
T6	686	0	0	0
T9	0	10	0	0
T18	10193	20	0	0
T19	760	0	0	0
T35	0	3	0	0
T42	0	15	0	0
T43	737	0	0	0
T49	0	11	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	15	0	0
T72	0	12	0	0
T73	0	1	0	0
T74	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	1477	0	0
T2	15250	0	0	0
T3	25650	12	0	0
T6	686	0	0	0
T9	0	10	0	0
T18	10193	20	0	0
T19	760	0	0	0
T35	0	3	0	0
T42	0	15	0	0
T43	737	0	0	0
T49	0	11	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	15	0	0
T72	0	12	0	0
T73	0	1	0	0
T74	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	794	0	0
T2	15250	0	0	0
T3	25650	12	0	0
T6	686	0	0	0
T9	0	10	0	0
T18	10193	20	0	0
T19	760	0	0	0
T35	0	3	0	0
T43	737	0	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	15	0	0
T72	0	12	0	0
T73	0	1	0	0
T75	0	18	0	0
T83	0	11	0	0
T246	0	32	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	794	0	0
T2	15250	0	0	0
T3	25650	12	0	0
T6	686	0	0	0
T9	0	10	0	0
T18	10193	20	0	0
T19	760	0	0	0
T35	0	3	0	0
T43	737	0	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	15	0	0
T72	0	12	0	0
T73	0	1	0	0
T75	0	18	0	0
T83	0	11	0	0
T246	0	32	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	72602	0	0
T2	15250	0	0	0
T3	25650	1295	0	0
T6	686	0	0	0
T9	0	352	0	0
T18	10193	2056	0	0
T19	760	0	0	0
T35	0	473	0	0
T43	737	0	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	246	0	0
T72	0	949	0	0
T73	0	48	0	0
T75	0	731	0	0
T83	0	115	0	0
T246	0	1942	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	721	0	0
T2	15250	0	0	0
T3	25650	8	0	0
T6	686	0	0	0
T9	0	9	0	0
T18	10193	19	0	0
T19	760	0	0	0
T35	0	2	0	0
T43	737	0	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	14	0	0
T72	0	12	0	0
T75	0	17	0	0
T83	0	11	0	0
T246	0	32	0	0
T247	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T2,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T18,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T2,T3
1	0	Covered	T1,T18,T2
1	1	Covered	T18,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T2,T3
0	1	Covered	T88,T95,T96
1	0	Covered	T54,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T2,T3
0	1	Covered	T2,T7,T9
1	0	Covered	T54,T79,T248

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T2,T3
1	-	Covered	T2,T7,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T2,T3
DetectSt	168	Covered	T18,T2,T3
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T18,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T2,T3
DebounceSt->IdleSt	163	Covered	T2,T7,T12
DetectSt->IdleSt	186	Covered	T88,T54,T95
DetectSt->StableSt	191	Covered	T18,T2,T3
IdleSt->DebounceSt	148	Covered	T18,T2,T3
StableSt->IdleSt	206	Covered	T18,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T2,T3
0	1	Covered	T18,T2,T3
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T7,T12
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T88,T54,T95
DetectSt	-	-	-	-	0	1	-	Covered	T18,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T18,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T9
StableSt	-	-	-	-	-	-	0	Covered	T18,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	926	0	0
CntIncr_A	7886385	48162	0	0
CntNoWrap_A	7886385	7228904	0	0
DetectStDropOut_A	7886385	36	0	0
DetectedOut_A	7886385	13701	0	0
DetectedPulseOut_A	7886385	384	0	0
DisabledIdleSt_A	7886385	6858765	0	0
DisabledNoDetection_A	7886385	6860404	0	0
EnterDebounceSt_A	7886385	504	0	0
EnterDetectSt_A	7886385	424	0	0
EnterStableSt_A	7886385	384	0	0
PulseIsPulse_A	7886385	384	0	0
StayInStableSt	7886385	13288	0	0
gen_high_level_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	349	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	926	0	0
T2	15250	5	0	0
T3	25650	8	0	0
T6	686	0	0	0
T7	0	13	0	0
T9	0	2	0	0
T12	0	1	0	0
T18	10193	2	0	0
T19	760	0	0	0
T27	0	1	0	0
T33	0	2	0	0
T34	0	10	0	0
T43	737	0	0	0
T48	0	2	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	48162	0	0
T2	15250	280	0	0
T3	25650	188	0	0
T6	686	0	0	0
T7	0	643	0	0
T9	0	65	0	0
T12	0	20	0	0
T18	10193	70	0	0
T19	760	0	0	0
T27	0	20	0	0
T33	0	40	0	0
T34	0	840	0	0
T43	737	0	0	0
T48	0	25	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7228904	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9788	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	36	0	0
T38	627	0	0	0
T39	866	0	0	0
T40	22074	0	0	0
T61	11686	0	0	0
T74	6608	0	0	0
T88	4271	1	0	0
T95	0	6	0	0
T96	0	1	0	0
T97	0	14	0	0
T98	0	1	0	0
T99	0	3	0	0
T101	0	3	0	0
T102	0	2	0	0
T103	0	5	0	0
T104	439	0	0	0
T105	426	0	0	0
T106	426	0	0	0
T107	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	13701	0	0
T2	15250	8	0	0
T3	25650	318	0	0
T6	686	0	0	0
T7	0	28	0	0
T9	0	40	0	0
T18	10193	61	0	0
T19	760	0	0	0
T34	0	41	0	0
T35	0	319	0	0
T43	737	0	0	0
T48	0	3	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	60	0	0
T116	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	384	0	0
T2	15250	2	0	0
T3	25650	4	0	0
T6	686	0	0	0
T7	0	6	0	0
T9	0	1	0	0
T18	10193	1	0	0
T19	760	0	0	0
T34	0	5	0	0
T35	0	1	0	0
T43	737	0	0	0
T48	0	1	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	1	0	0
T116	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6858765	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	7714	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6860404	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	7715	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	504	0	0
T2	15250	3	0	0
T3	25650	4	0	0
T6	686	0	0	0
T7	0	7	0	0
T9	0	1	0	0
T12	0	1	0	0
T18	10193	1	0	0
T19	760	0	0	0
T27	0	1	0	0
T33	0	2	0	0
T34	0	5	0	0
T43	737	0	0	0
T48	0	1	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	424	0	0
T2	15250	2	0	0
T3	25650	4	0	0
T6	686	0	0	0
T7	0	6	0	0
T9	0	1	0	0
T18	10193	1	0	0
T19	760	0	0	0
T34	0	5	0	0
T35	0	1	0	0
T43	737	0	0	0
T48	0	1	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	1	0	0
T116	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	384	0	0
T2	15250	2	0	0
T3	25650	4	0	0
T6	686	0	0	0
T7	0	6	0	0
T9	0	1	0	0
T18	10193	1	0	0
T19	760	0	0	0
T34	0	5	0	0
T35	0	1	0	0
T43	737	0	0	0
T48	0	1	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	1	0	0
T116	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	384	0	0
T2	15250	2	0	0
T3	25650	4	0	0
T6	686	0	0	0
T7	0	6	0	0
T9	0	1	0	0
T18	10193	1	0	0
T19	760	0	0	0
T34	0	5	0	0
T35	0	1	0	0
T43	737	0	0	0
T48	0	1	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	1	0	0
T116	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	13288	0	0
T2	15250	6	0	0
T3	25650	310	0	0
T6	686	0	0	0
T7	0	22	0	0
T9	0	39	0	0
T18	10193	59	0	0
T19	760	0	0	0
T34	0	36	0	0
T35	0	318	0	0
T43	737	0	0	0
T48	0	2	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	59	0	0
T116	0	75	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	349	0	0
T2	15250	2	0	0
T3	25650	0	0	0
T6	686	0	0	0
T7	17776	6	0	0
T9	0	1	0	0
T34	0	5	0	0
T35	0	1	0	0
T40	0	3	0	0
T44	56028	0	0	0
T48	0	1	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	1	0	0
T116	0	7	0	0
T117	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T3,T9
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T3,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T3,T9
1	0	Covered	T18,T3,T9
1	1	Covered	T18,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T3,T9
0	1	Covered	T71,T72,T74
1	0	Covered	T18,T71,T72

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T42
0	1	Covered	T3,T9,T42
1	0	Covered	T9,T84,T249

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T42
1	-	Covered	T3,T9,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T3,T9
DetectSt	168	Covered	T18,T3,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T9,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T3,T9
DebounceSt->IdleSt	163	Covered	T242,T54,T94
DetectSt->IdleSt	186	Covered	T18,T71,T72
DetectSt->StableSt	191	Covered	T3,T9,T42
IdleSt->DebounceSt	148	Covered	T18,T3,T9
StableSt->IdleSt	206	Covered	T3,T9,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T3,T9
0	1	Covered	T18,T3,T9
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T3,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T18,T3,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T3,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T242,T54,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T3,T9
DetectSt	-	-	-	-	1	-	-	Covered	T18,T71,T72
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T42
DetectSt	-	-	-	-	0	0	-	Covered	T18,T3,T9
StableSt	-	-	-	-	-	-	1	Covered	T3,T9,T42
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T42
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	3195	0	0
CntIncr_A	7886385	106664	0	0
CntNoWrap_A	7886385	7226635	0	0
DetectStDropOut_A	7886385	442	0	0
DetectedOut_A	7886385	84960	0	0
DetectedPulseOut_A	7886385	891	0	0
DisabledIdleSt_A	7886385	6773201	0	0
DisabledNoDetection_A	7886385	6775362	0	0
EnterDebounceSt_A	7886385	1616	0	0
EnterDetectSt_A	7886385	1579	0	0
EnterStableSt_A	7886385	891	0	0
PulseIsPulse_A	7886385	891	0	0
StayInStableSt	7886385	83981	0	0
gen_high_event_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_high_level_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	766	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	3195	0	0
T2	15250	0	0	0
T3	25650	24	0	0
T6	686	0	0	0
T9	0	42	0	0
T18	10193	40	0	0
T19	760	0	0	0
T35	0	10	0	0
T42	0	40	0	0
T43	737	0	0	0
T49	0	10	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	22	0	0
T72	0	44	0	0
T74	0	44	0	0
T75	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	106664	0	0
T2	15250	0	0	0
T3	25650	852	0	0
T6	686	0	0	0
T9	0	1071	0	0
T18	10193	1579	0	0
T19	760	0	0	0
T35	0	280	0	0
T42	0	780	0	0
T43	737	0	0	0
T49	0	1315	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	686	0	0
T72	0	1508	0	0
T74	0	1015	0	0
T75	0	1512	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7226635	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9750	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	442	0	0
T37	12758	0	0	0
T38	627	0	0	0
T39	866	0	0	0
T54	0	1	0	0
T61	11686	0	0	0
T71	13315	2	0	0
T72	16268	8	0	0
T73	475	0	0	0
T74	0	20	0	0
T83	0	7	0	0
T88	4271	0	0	0
T89	0	13	0	0
T92	0	25	0	0
T94	0	5	0	0
T104	439	0	0	0
T130	422	0	0	0
T247	0	22	0	0
T250	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	84960	0	0
T3	25650	886	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T9	0	539	0	0
T35	0	161	0	0
T42	0	1882	0	0
T44	56028	0	0	0
T49	0	2514	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T75	0	1617	0	0
T90	0	1522	0	0
T91	0	1682	0	0
T169	422	0	0	0
T246	0	239	0	0
T251	0	2995	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	891	0	0
T3	25650	12	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T9	0	21	0	0
T35	0	5	0	0
T42	0	20	0	0
T44	56028	0	0	0
T49	0	5	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T75	0	27	0	0
T90	0	17	0	0
T91	0	24	0	0
T169	422	0	0	0
T246	0	7	0	0
T251	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6773201	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	5625	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6775362	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	5626	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	1616	0	0
T2	15250	0	0	0
T3	25650	12	0	0
T6	686	0	0	0
T9	0	21	0	0
T18	10193	20	0	0
T19	760	0	0	0
T35	0	5	0	0
T42	0	20	0	0
T43	737	0	0	0
T49	0	5	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	11	0	0
T72	0	22	0	0
T74	0	22	0	0
T75	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	1579	0	0
T2	15250	0	0	0
T3	25650	12	0	0
T6	686	0	0	0
T9	0	21	0	0
T18	10193	20	0	0
T19	760	0	0	0
T35	0	5	0	0
T42	0	20	0	0
T43	737	0	0	0
T49	0	5	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	11	0	0
T72	0	22	0	0
T74	0	22	0	0
T75	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	891	0	0
T3	25650	12	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T9	0	21	0	0
T35	0	5	0	0
T42	0	20	0	0
T44	56028	0	0	0
T49	0	5	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T75	0	27	0	0
T90	0	17	0	0
T91	0	24	0	0
T169	422	0	0	0
T246	0	7	0	0
T251	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	891	0	0
T3	25650	12	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T9	0	21	0	0
T35	0	5	0	0
T42	0	20	0	0
T44	56028	0	0	0
T49	0	5	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T75	0	27	0	0
T90	0	17	0	0
T91	0	24	0	0
T169	422	0	0	0
T246	0	7	0	0
T251	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	83981	0	0
T3	25650	874	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T9	0	518	0	0
T35	0	156	0	0
T42	0	1859	0	0
T44	56028	0	0	0
T49	0	2508	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T75	0	1588	0	0
T90	0	1505	0	0
T91	0	1658	0	0
T169	422	0	0	0
T246	0	232	0	0
T251	0	2970	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	766	0	0
T3	25650	12	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T9	0	8	0	0
T35	0	5	0	0
T42	0	17	0	0
T44	56028	0	0	0
T49	0	4	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T75	0	25	0	0
T90	0	17	0	0
T91	0	24	0	0
T169	422	0	0	0
T246	0	7	0	0
T251	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T2,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T2,T3
1	0	Covered	T1,T18,T2
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T116,T88,T36
1	0	Covered	T54,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
1	0	Covered	T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T7
1	-	Covered	T2,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T7
DetectSt	168	Covered	T2,T3,T7
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T7
DebounceSt->IdleSt	163	Covered	T2,T7,T34
DetectSt->IdleSt	186	Covered	T116,T88,T36
DetectSt->StableSt	191	Covered	T2,T3,T7
IdleSt->DebounceSt	148	Covered	T2,T3,T7
StableSt->IdleSt	206	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T7,T34
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T116,T88,T36
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	787	0	0
CntIncr_A	7886385	42446	0	0
CntNoWrap_A	7886385	7229043	0	0
DetectStDropOut_A	7886385	61	0	0
DetectedOut_A	7886385	15186	0	0
DetectedPulseOut_A	7886385	305	0	0
DisabledIdleSt_A	7886385	6852589	0	0
DisabledNoDetection_A	7886385	6854265	0	0
EnterDebounceSt_A	7886385	419	0	0
EnterDetectSt_A	7886385	369	0	0
EnterStableSt_A	7886385	305	0	0
PulseIsPulse_A	7886385	305	0	0
StayInStableSt	7886385	14862	0	0
gen_high_level_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	281	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	787	0	0
T2	15250	9	0	0
T3	25650	2	0	0
T6	686	0	0	0
T7	17776	7	0	0
T10	0	4	0	0
T34	0	25	0	0
T40	0	2	0	0
T42	0	6	0	0
T44	56028	0	0	0
T49	0	2	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T88	0	14	0	0
T116	0	13	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	42446	0	0
T2	15250	468	0	0
T3	25650	72	0	0
T6	686	0	0	0
T7	17776	250	0	0
T10	0	110	0	0
T34	0	1535	0	0
T40	0	89	0	0
T42	0	189	0	0
T44	56028	0	0	0
T49	0	246	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T88	0	508	0	0
T116	0	607	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229043	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	61	0	0
T36	0	4	0	0
T37	12758	0	0	0
T38	627	0	0	0
T71	13315	0	0	0
T72	16268	0	0	0
T73	475	0	0	0
T88	4271	7	0	0
T95	0	3	0	0
T104	439	0	0	0
T116	53091	5	0	0
T130	422	0	0	0
T149	0	2	0	0
T222	0	10	0	0
T245	526	0	0	0
T252	0	4	0	0
T253	0	12	0	0
T254	0	12	0	0
T255	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	15186	0	0
T2	15250	26	0	0
T3	25650	56	0	0
T6	686	0	0	0
T7	17776	100	0	0
T10	0	79	0	0
T34	0	667	0	0
T40	0	74	0	0
T42	0	144	0	0
T44	56028	0	0	0
T49	0	79	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T75	0	175	0	0
T116	0	70	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	305	0	0
T2	15250	4	0	0
T3	25650	1	0	0
T6	686	0	0	0
T7	17776	3	0	0
T10	0	2	0	0
T34	0	12	0	0
T40	0	1	0	0
T42	0	3	0	0
T44	56028	0	0	0
T49	0	1	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T75	0	2	0	0
T116	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6852589	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9789	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6854265	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9791	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	419	0	0
T2	15250	5	0	0
T3	25650	1	0	0
T6	686	0	0	0
T7	17776	4	0	0
T10	0	2	0	0
T34	0	13	0	0
T40	0	1	0	0
T42	0	3	0	0
T44	56028	0	0	0
T49	0	1	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T88	0	7	0	0
T116	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	369	0	0
T2	15250	4	0	0
T3	25650	1	0	0
T6	686	0	0	0
T7	17776	3	0	0
T10	0	2	0	0
T34	0	12	0	0
T40	0	1	0	0
T42	0	3	0	0
T44	56028	0	0	0
T49	0	1	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T88	0	7	0	0
T116	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	305	0	0
T2	15250	4	0	0
T3	25650	1	0	0
T6	686	0	0	0
T7	17776	3	0	0
T10	0	2	0	0
T34	0	12	0	0
T40	0	1	0	0
T42	0	3	0	0
T44	56028	0	0	0
T49	0	1	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T75	0	2	0	0
T116	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	305	0	0
T2	15250	4	0	0
T3	25650	1	0	0
T6	686	0	0	0
T7	17776	3	0	0
T10	0	2	0	0
T34	0	12	0	0
T40	0	1	0	0
T42	0	3	0	0
T44	56028	0	0	0
T49	0	1	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T75	0	2	0	0
T116	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	14862	0	0
T2	15250	22	0	0
T3	25650	55	0	0
T6	686	0	0	0
T7	17776	97	0	0
T10	0	77	0	0
T34	0	655	0	0
T40	0	73	0	0
T42	0	138	0	0
T44	56028	0	0	0
T49	0	78	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T75	0	173	0	0
T116	0	69	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	281	0	0
T2	15250	4	0	0
T3	25650	1	0	0
T6	686	0	0	0
T7	17776	3	0	0
T10	0	2	0	0
T34	0	12	0	0
T40	0	1	0	0
T44	56028	0	0	0
T49	0	1	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T75	0	2	0	0
T90	0	1	0	0
T116	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T3,T9
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T3,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T3,T9
1	0	Covered	T18,T3,T9
1	1	Covered	T18,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T3,T9
0	1	Covered	T72,T74,T90
1	0	Covered	T72,T90,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T3,T9
0	1	Covered	T18,T3,T9
1	0	Covered	T83,T256,T257

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T3,T9
1	-	Covered	T18,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T3,T9
DetectSt	168	Covered	T18,T3,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T18,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T3,T9
DebounceSt->IdleSt	163	Covered	T242,T54,T94
DetectSt->IdleSt	186	Covered	T72,T74,T90
DetectSt->StableSt	191	Covered	T18,T3,T9
IdleSt->DebounceSt	148	Covered	T18,T3,T9
StableSt->IdleSt	206	Covered	T18,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T3,T9
0	1	Covered	T18,T3,T9
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T3,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T18,T3,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T3,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T242,T54,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T3,T9
DetectSt	-	-	-	-	1	-	-	Covered	T72,T74,T90
DetectSt	-	-	-	-	0	1	-	Covered	T18,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T18,T3,T9
StableSt	-	-	-	-	-	-	1	Covered	T18,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T18,T3,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	3122	0	0
CntIncr_A	7886385	106580	0	0
CntNoWrap_A	7886385	7226708	0	0
DetectStDropOut_A	7886385	487	0	0
DetectedOut_A	7886385	69391	0	0
DetectedPulseOut_A	7886385	867	0	0
DisabledIdleSt_A	7886385	6779687	0	0
DisabledNoDetection_A	7886385	6781858	0	0
EnterDebounceSt_A	7886385	1581	0	0
EnterDetectSt_A	7886385	1542	0	0
EnterStableSt_A	7886385	867	0	0
PulseIsPulse_A	7886385	867	0	0
StayInStableSt	7886385	68445	0	0
gen_high_event_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_high_level_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	745	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	3122	0	0
T2	15250	0	0	0
T3	25650	24	0	0
T6	686	0	0	0
T9	0	64	0	0
T18	10193	10	0	0
T19	760	0	0	0
T35	0	48	0	0
T42	0	30	0	0
T43	737	0	0	0
T49	0	20	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	54	0	0
T72	0	38	0	0
T74	0	40	0	0
T75	0	58	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	106580	0	0
T2	15250	0	0	0
T3	25650	828	0	0
T6	686	0	0	0
T9	0	1888	0	0
T18	10193	285	0	0
T19	760	0	0	0
T35	0	1320	0	0
T42	0	825	0	0
T43	737	0	0	0
T49	0	2340	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	1647	0	0
T72	0	1299	0	0
T74	0	923	0	0
T75	0	1189	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7226708	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9780	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	487	0	0
T38	627	0	0	0
T39	866	0	0	0
T40	22074	0	0	0
T54	0	1	0	0
T61	11686	0	0	0
T72	16268	5	0	0
T73	475	0	0	0
T74	0	20	0	0
T83	0	11	0	0
T84	0	7	0	0
T88	4271	0	0	0
T90	0	20	0	0
T92	0	28	0	0
T94	0	6	0	0
T104	439	0	0	0
T105	426	0	0	0
T130	422	0	0	0
T247	0	9	0	0
T258	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	69391	0	0
T2	15250	0	0	0
T3	25650	925	0	0
T6	686	0	0	0
T9	0	2334	0	0
T18	10193	117	0	0
T19	760	0	0	0
T35	0	5697	0	0
T42	0	511	0	0
T43	737	0	0	0
T49	0	2997	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	1515	0	0
T75	0	2493	0	0
T89	0	2261	0	0
T246	0	138	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	867	0	0
T2	15250	0	0	0
T3	25650	12	0	0
T6	686	0	0	0
T9	0	32	0	0
T18	10193	5	0	0
T19	760	0	0	0
T35	0	24	0	0
T42	0	15	0	0
T43	737	0	0	0
T49	0	10	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	27	0	0
T75	0	29	0	0
T89	0	28	0	0
T246	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6779687	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	5617	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6781858	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	5618	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	1581	0	0
T2	15250	0	0	0
T3	25650	12	0	0
T6	686	0	0	0
T9	0	32	0	0
T18	10193	5	0	0
T19	760	0	0	0
T35	0	24	0	0
T42	0	15	0	0
T43	737	0	0	0
T49	0	10	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	27	0	0
T72	0	19	0	0
T74	0	20	0	0
T75	0	29	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	1542	0	0
T2	15250	0	0	0
T3	25650	12	0	0
T6	686	0	0	0
T9	0	32	0	0
T18	10193	5	0	0
T19	760	0	0	0
T35	0	24	0	0
T42	0	15	0	0
T43	737	0	0	0
T49	0	10	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	27	0	0
T72	0	19	0	0
T74	0	20	0	0
T75	0	29	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	867	0	0
T2	15250	0	0	0
T3	25650	12	0	0
T6	686	0	0	0
T9	0	32	0	0
T18	10193	5	0	0
T19	760	0	0	0
T35	0	24	0	0
T42	0	15	0	0
T43	737	0	0	0
T49	0	10	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	27	0	0
T75	0	29	0	0
T89	0	28	0	0
T246	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	867	0	0
T2	15250	0	0	0
T3	25650	12	0	0
T6	686	0	0	0
T9	0	32	0	0
T18	10193	5	0	0
T19	760	0	0	0
T35	0	24	0	0
T42	0	15	0	0
T43	737	0	0	0
T49	0	10	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	27	0	0
T75	0	29	0	0
T89	0	28	0	0
T246	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	68445	0	0
T2	15250	0	0	0
T3	25650	909	0	0
T6	686	0	0	0
T9	0	2296	0	0
T18	10193	112	0	0
T19	760	0	0	0
T35	0	5670	0	0
T42	0	495	0	0
T43	737	0	0	0
T49	0	2987	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	1485	0	0
T75	0	2461	0	0
T89	0	2228	0	0
T246	0	135	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	745	0	0
T2	15250	0	0	0
T3	25650	8	0	0
T6	686	0	0	0
T9	0	26	0	0
T18	10193	5	0	0
T19	760	0	0	0
T35	0	21	0	0
T42	0	14	0	0
T43	737	0	0	0
T49	0	10	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	24	0	0
T75	0	26	0	0
T89	0	23	0	0
T246	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T2,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T2,T3
1	0	Covered	T1,T18,T2
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T2,T7,T34
1	0	Covered	T54,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T42
0	1	Covered	T3,T35,T116
1	0	Covered	T49,T54,T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T42
1	-	Covered	T3,T35,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T7
DetectSt	168	Covered	T2,T3,T7
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T9,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T7
DebounceSt->IdleSt	163	Covered	T2,T7,T116
DetectSt->IdleSt	186	Covered	T2,T7,T34
DetectSt->StableSt	191	Covered	T3,T9,T42
IdleSt->DebounceSt	148	Covered	T2,T3,T7
StableSt->IdleSt	206	Covered	T3,T9,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T7,T116
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T2,T7,T34
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T42
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T35,T49
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	881	0	0
CntIncr_A	7886385	49519	0	0
CntNoWrap_A	7886385	7228949	0	0
DetectStDropOut_A	7886385	97	0	0
DetectedOut_A	7886385	16036	0	0
DetectedPulseOut_A	7886385	315	0	0
DisabledIdleSt_A	7886385	6866869	0	0
DisabledNoDetection_A	7886385	6868548	0	0
EnterDebounceSt_A	7886385	465	0	0
EnterDetectSt_A	7886385	417	0	0
EnterStableSt_A	7886385	315	0	0
PulseIsPulse_A	7886385	315	0	0
StayInStableSt	7886385	15684	0	0
gen_high_level_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	274	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	881	0	0
T2	15250	15	0	0
T3	25650	8	0	0
T6	686	0	0	0
T7	17776	5	0	0
T9	0	10	0	0
T34	0	12	0	0
T35	0	6	0	0
T42	0	2	0	0
T44	56028	0	0	0
T49	0	4	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	6	0	0
T116	0	29	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	49519	0	0
T2	15250	810	0	0
T3	25650	276	0	0
T6	686	0	0	0
T7	17776	244	0	0
T9	0	340	0	0
T34	0	1054	0	0
T35	0	258	0	0
T42	0	59	0	0
T44	56028	0	0	0
T49	0	494	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	198	0	0
T116	0	1101	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7228949	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	97	0	0
T2	15250	7	0	0
T3	25650	0	0	0
T6	686	0	0	0
T7	17776	2	0	0
T34	0	6	0	0
T44	56028	0	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T222	0	10	0	0
T253	0	2	0	0
T259	0	1	0	0
T260	0	4	0	0
T261	0	4	0	0
T262	0	8	0	0
T263	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	16036	0	0
T3	25650	236	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T9	0	170	0	0
T35	0	846	0	0
T36	0	11	0	0
T42	0	52	0	0
T44	56028	0	0	0
T49	0	154	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	113	0	0
T75	0	243	0	0
T89	0	432	0	0
T116	0	452	0	0
T169	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	315	0	0
T3	25650	4	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T9	0	5	0	0
T35	0	3	0	0
T36	0	2	0	0
T42	0	1	0	0
T44	56028	0	0	0
T49	0	2	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	3	0	0
T75	0	3	0	0
T89	0	5	0	0
T116	0	13	0	0
T169	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6866869	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9670	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6868548	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9672	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	465	0	0
T2	15250	8	0	0
T3	25650	4	0	0
T6	686	0	0	0
T7	17776	3	0	0
T9	0	5	0	0
T34	0	6	0	0
T35	0	3	0	0
T42	0	1	0	0
T44	56028	0	0	0
T49	0	2	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	3	0	0
T116	0	16	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	417	0	0
T2	15250	7	0	0
T3	25650	4	0	0
T6	686	0	0	0
T7	17776	2	0	0
T9	0	5	0	0
T34	0	6	0	0
T35	0	3	0	0
T42	0	1	0	0
T44	56028	0	0	0
T49	0	2	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	3	0	0
T116	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	315	0	0
T3	25650	4	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T9	0	5	0	0
T35	0	3	0	0
T36	0	2	0	0
T42	0	1	0	0
T44	56028	0	0	0
T49	0	2	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	3	0	0
T75	0	3	0	0
T89	0	5	0	0
T116	0	13	0	0
T169	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	315	0	0
T3	25650	4	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T9	0	5	0	0
T35	0	3	0	0
T36	0	2	0	0
T42	0	1	0	0
T44	56028	0	0	0
T49	0	2	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	3	0	0
T75	0	3	0	0
T89	0	5	0	0
T116	0	13	0	0
T169	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	15684	0	0
T3	25650	232	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T9	0	160	0	0
T35	0	843	0	0
T36	0	9	0	0
T42	0	50	0	0
T44	56028	0	0	0
T49	0	152	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	108	0	0
T75	0	238	0	0
T89	0	422	0	0
T116	0	439	0	0
T169	422	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	274	0	0
T3	25650	4	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T44	56028	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	1	0	0
T75	0	1	0	0
T116	0	13	0	0
T169	422	0	0	0
T212	0	1	0	0
T214	0	1	0	0
T252	0	7	0	0
T264	0	5	0	0