Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T3,T9
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T3,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T3,T9
1	0	Covered	T18,T3,T9
1	1	Covered	T18,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T3,T9
0	1	Covered	T18,T247,T91
1	0	Covered	T18,T42,T89

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T35
0	1	Covered	T3,T9,T35
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T35
1	-	Covered	T3,T9,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T3,T9
DetectSt	168	Covered	T18,T3,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T9,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T3,T9
DebounceSt->IdleSt	163	Covered	T242,T54,T94
DetectSt->IdleSt	186	Covered	T18,T42,T89
DetectSt->StableSt	191	Covered	T3,T9,T35
IdleSt->DebounceSt	148	Covered	T18,T3,T9
StableSt->IdleSt	206	Covered	T3,T9,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T3,T9
0	1	Covered	T18,T3,T9
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T3,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T18,T3,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T3,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T242,T54,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T3,T9
DetectSt	-	-	-	-	1	-	-	Covered	T18,T42,T89
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T35
DetectSt	-	-	-	-	0	0	-	Covered	T18,T3,T9
StableSt	-	-	-	-	-	-	1	Covered	T3,T9,T35
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T35
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	2772	0	0
CntIncr_A	7886385	88358	0	0
CntNoWrap_A	7886385	7227058	0	0
DetectStDropOut_A	7886385	405	0	0
DetectedOut_A	7886385	61740	0	0
DetectedPulseOut_A	7886385	755	0	0
DisabledIdleSt_A	7886385	6786882	0	0
DisabledNoDetection_A	7886385	6789052	0	0
EnterDebounceSt_A	7886385	1404	0	0
EnterDetectSt_A	7886385	1368	0	0
EnterStableSt_A	7886385	755	0	0
PulseIsPulse_A	7886385	755	0	0
StayInStableSt	7886385	60905	0	0
gen_high_event_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_high_level_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	674	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	2772	0	0
T2	15250	0	0	0
T3	25650	34	0	0
T6	686	0	0	0
T9	0	12	0	0
T18	10193	50	0	0
T19	760	0	0	0
T35	0	22	0	0
T42	0	40	0	0
T43	737	0	0	0
T49	0	18	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	30	0	0
T72	0	46	0	0
T74	0	4	0	0
T75	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	88358	0	0
T2	15250	0	0	0
T3	25650	867	0	0
T6	686	0	0	0
T9	0	348	0	0
T18	10193	1969	0	0
T19	760	0	0	0
T35	0	616	0	0
T42	0	1142	0	0
T43	737	0	0	0
T49	0	2178	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	810	0	0
T72	0	1426	0	0
T74	0	88	0	0
T75	0	1110	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7227058	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9740	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	405	0	0
T2	15250	0	0	0
T3	25650	0	0	0
T6	686	0	0	0
T18	10193	13	0	0
T19	760	0	0	0
T43	737	0	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T54	0	1	0	0
T91	0	7	0	0
T92	0	14	0	0
T94	0	20	0	0
T113	0	24	0	0
T181	0	15	0	0
T247	0	3	0	0
T265	0	2	0	0
T266	0	16	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	61740	0	0
T3	25650	1054	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T9	0	238	0	0
T35	0	359	0	0
T44	56028	0	0	0
T49	0	5344	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	382	0	0
T72	0	2296	0	0
T74	0	1690	0	0
T75	0	224	0	0
T83	0	3279	0	0
T169	422	0	0	0
T246	0	415	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	755	0	0
T3	25650	17	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T9	0	6	0	0
T35	0	11	0	0
T44	56028	0	0	0
T49	0	9	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	15	0	0
T72	0	23	0	0
T74	0	2	0	0
T75	0	15	0	0
T83	0	21	0	0
T169	422	0	0	0
T246	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6786882	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	5631	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6789052	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	5632	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	1404	0	0
T2	15250	0	0	0
T3	25650	17	0	0
T6	686	0	0	0
T9	0	6	0	0
T18	10193	25	0	0
T19	760	0	0	0
T35	0	11	0	0
T42	0	20	0	0
T43	737	0	0	0
T49	0	9	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	15	0	0
T72	0	23	0	0
T74	0	2	0	0
T75	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	1368	0	0
T2	15250	0	0	0
T3	25650	17	0	0
T6	686	0	0	0
T9	0	6	0	0
T18	10193	25	0	0
T19	760	0	0	0
T35	0	11	0	0
T42	0	20	0	0
T43	737	0	0	0
T49	0	9	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T71	0	15	0	0
T72	0	23	0	0
T74	0	2	0	0
T75	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	755	0	0
T3	25650	17	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T9	0	6	0	0
T35	0	11	0	0
T44	56028	0	0	0
T49	0	9	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	15	0	0
T72	0	23	0	0
T74	0	2	0	0
T75	0	15	0	0
T83	0	21	0	0
T169	422	0	0	0
T246	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	755	0	0
T3	25650	17	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T9	0	6	0	0
T35	0	11	0	0
T44	56028	0	0	0
T49	0	9	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	15	0	0
T72	0	23	0	0
T74	0	2	0	0
T75	0	15	0	0
T83	0	21	0	0
T169	422	0	0	0
T246	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	60905	0	0
T3	25650	1034	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T9	0	231	0	0
T35	0	348	0	0
T44	56028	0	0	0
T49	0	5331	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	366	0	0
T72	0	2269	0	0
T74	0	1688	0	0
T75	0	208	0	0
T83	0	3258	0	0
T169	422	0	0	0
T246	0	402	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	674	0	0
T3	25650	14	0	0
T6	686	0	0	0
T7	17776	0	0	0
T8	489	0	0	0
T9	0	5	0	0
T35	0	11	0	0
T44	56028	0	0	0
T49	0	5	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	14	0	0
T72	0	19	0	0
T74	0	2	0	0
T75	0	14	0	0
T83	0	21	0	0
T169	422	0	0	0
T246	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T2,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T2,T3
1	0	Covered	T1,T18,T2
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T7,T116,T88
1	0	Covered	T54,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T10
0	1	Covered	T2,T3,T10
1	0	Covered	T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T10
1	-	Covered	T2,T3,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T7
DetectSt	168	Covered	T2,T3,T7
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T3,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T7
DebounceSt->IdleSt	163	Covered	T2,T7,T116
DetectSt->IdleSt	186	Covered	T7,T116,T88
DetectSt->StableSt	191	Covered	T2,T3,T10
IdleSt->DebounceSt	148	Covered	T2,T3,T7
StableSt->IdleSt	206	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T7,T116
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T7,T116,T88
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T10
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T10
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7886385	826	0	0
CntIncr_A	7886385	44805	0	0
CntNoWrap_A	7886385	7229004	0	0
DetectStDropOut_A	7886385	34	0	0
DetectedOut_A	7886385	15628	0	0
DetectedPulseOut_A	7886385	345	0	0
DisabledIdleSt_A	7886385	6861527	0	0
DisabledNoDetection_A	7886385	6863188	0	0
EnterDebounceSt_A	7886385	444	0	0
EnterDetectSt_A	7886385	383	0	0
EnterStableSt_A	7886385	345	0	0
PulseIsPulse_A	7886385	345	0	0
StayInStableSt	7886385	15257	0	0
gen_high_level_sva.HighLevelEvent_A	7886385	7232171	0	0
gen_not_sticky_sva.StableStDropOut_A	7886385	317	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	826	0	0
T2	15250	9	0	0
T3	25650	2	0	0
T6	686	0	0	0
T7	17776	15	0	0
T10	0	4	0	0
T34	0	6	0	0
T44	56028	0	0	0
T49	0	8	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	2	0	0
T72	0	9	0	0
T88	0	17	0	0
T116	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	44805	0	0
T2	15250	464	0	0
T3	25650	57	0	0
T6	686	0	0	0
T7	17776	779	0	0
T10	0	172	0	0
T34	0	441	0	0
T44	56028	0	0	0
T49	0	944	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	69	0	0
T72	0	303	0	0
T88	0	604	0	0
T116	0	935	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7229004	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9790	0	0
T19	760	359	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	34	0	0
T7	17776	7	0	0
T8	489	0	0	0
T9	20346	0	0	0
T25	2839	0	0	0
T28	507	0	0	0
T45	650	0	0	0
T46	678	0	0	0
T56	648	0	0	0
T70	506	0	0	0
T88	0	8	0	0
T96	0	3	0	0
T116	0	1	0	0
T169	422	0	0	0
T174	0	6	0	0
T255	0	1	0	0
T267	0	3	0	0
T268	0	1	0	0
T269	0	3	0	0
T270	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	15628	0	0
T2	15250	29	0	0
T3	25650	71	0	0
T6	686	0	0	0
T7	17776	0	0	0
T10	0	18	0	0
T34	0	87	0	0
T40	0	52	0	0
T44	56028	0	0	0
T49	0	344	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	35	0	0
T72	0	317	0	0
T74	0	253	0	0
T116	0	512	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	345	0	0
T2	15250	4	0	0
T3	25650	1	0	0
T6	686	0	0	0
T7	17776	0	0	0
T10	0	2	0	0
T34	0	3	0	0
T40	0	1	0	0
T44	56028	0	0	0
T49	0	4	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	1	0	0
T72	0	4	0	0
T74	0	1	0	0
T116	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6861527	0	0
T1	3823	1418	0	0
T4	502	101	0	0
T5	423	22	0	0
T13	801	400	0	0
T14	502	101	0	0
T15	406	5	0	0
T16	527	126	0	0
T17	782	381	0	0
T18	10193	9787	0	0
T19	760	359	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	6863188	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9789	0	0
T19	760	360	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	444	0	0
T2	15250	5	0	0
T3	25650	1	0	0
T6	686	0	0	0
T7	17776	8	0	0
T10	0	2	0	0
T34	0	3	0	0
T44	56028	0	0	0
T49	0	4	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	1	0	0
T72	0	5	0	0
T88	0	9	0	0
T116	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	383	0	0
T2	15250	4	0	0
T3	25650	1	0	0
T6	686	0	0	0
T7	17776	7	0	0
T10	0	2	0	0
T34	0	3	0	0
T44	56028	0	0	0
T49	0	4	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	1	0	0
T72	0	4	0	0
T88	0	8	0	0
T116	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	345	0	0
T2	15250	4	0	0
T3	25650	1	0	0
T6	686	0	0	0
T7	17776	0	0	0
T10	0	2	0	0
T34	0	3	0	0
T40	0	1	0	0
T44	56028	0	0	0
T49	0	4	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	1	0	0
T72	0	4	0	0
T74	0	1	0	0
T116	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	345	0	0
T2	15250	4	0	0
T3	25650	1	0	0
T6	686	0	0	0
T7	17776	0	0	0
T10	0	2	0	0
T34	0	3	0	0
T40	0	1	0	0
T44	56028	0	0	0
T49	0	4	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	1	0	0
T72	0	4	0	0
T74	0	1	0	0
T116	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	15257	0	0
T2	15250	25	0	0
T3	25650	70	0	0
T6	686	0	0	0
T7	17776	0	0	0
T10	0	16	0	0
T34	0	84	0	0
T40	0	51	0	0
T44	56028	0	0	0
T49	0	336	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	34	0	0
T72	0	313	0	0
T74	0	252	0	0
T116	0	506	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	7232171	0	0
T1	3823	1423	0	0
T4	502	102	0	0
T5	423	23	0	0
T13	801	401	0	0
T14	502	102	0	0
T15	406	6	0	0
T16	527	127	0	0
T17	782	382	0	0
T18	10193	9792	0	0
T19	760	360	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7886385	317	0	0
T2	15250	4	0	0
T3	25650	1	0	0
T6	686	0	0	0
T7	17776	0	0	0
T10	0	2	0	0
T34	0	3	0	0
T36	0	2	0	0
T40	0	1	0	0
T44	56028	0	0	0
T50	898	0	0	0
T51	522	0	0	0
T52	424	0	0	0
T53	424	0	0	0
T55	507	0	0	0
T71	0	1	0	0
T72	0	4	0	0
T74	0	1	0	0
T116	0	6	0	0