SYSRST_CTRL Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: `d09e282b26`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.650s	2.112ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	8.100s	2.470ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.770s	2.426ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	6.670s	2.546ms	4	5	80.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	15.640s	6.029ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.390s	2.061ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	3.678m	40.478ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	8.520s	2.396ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.780s	2.057ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.390s	2.061ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	8.520s	2.396ms	5	5	100.00
V1		TOTAL			164	165	99.39
V2	combo_detect	sysrst_ctrl_combo_detect	6.150m	152.272ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	6.515m	144.643ms	98	100	98.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	13.829m	307.691ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	11.530s	4.438ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.570s	2.511ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.910s	2.228ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	53.561m	1.266s	48	50	96.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.710s	2.612ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	12.517m	2.409s	44	50	88.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	54.830s	41.243ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	11.146m	260.138ms	49	50	98.00
V2	alert_test	sysrst_ctrl_alert_test	5.880s	2.013ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.030s	2.011ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	7.440s	2.113ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	7.440s	2.113ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	15.640s	6.029ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.390s	2.061ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	8.520s	2.396ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	29.200s	7.739ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	15.640s	6.029ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.390s	2.061ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	8.520s	2.396ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	29.200s	7.739ms	20	20	100.00
V2		TOTAL			681	692	98.41
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.827m	42.010ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.925m	42.355ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.925m	42.355ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	19.900s	7.772ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			918	932	98.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	15	15	11	73.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.78	99.35	96.73	100.00	96.79	98.82	99.52	86.28

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 5 failures:

Test sysrst_ctrl_ultra_low_pwr has 5 failures.

0.sysrst_ctrl_ultra_low_pwr.113315147450941848091532518373582697346399683021786372303048071278170006441193
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2179483207 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 2341983207 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 3826983207 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 3851540514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.sysrst_ctrl_ultra_low_pwr.65442567854780218908134796545723955527198502142726343504421112032000514117980
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2140124905 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 2182624905 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 4912624905 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 7107624905 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 7194657804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 3 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: * has 2 failures:

Test sysrst_ctrl_combo_detect_ec_rst_with_pre_cond has 1 failures.
- 4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.42921173157346053903760317817414990420083366066781182744219432976514966327515
  Line 560, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest/run.log
```
  UVM_ERROR @ 2291206620 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
  UVM_INFO @ 2505377470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test sysrst_ctrl_stress_all has 1 failures.

28.sysrst_ctrl_stress_all.85495232992511098807269786012229864353481955218669779626545159467406038773708
Line 560, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 4182172087 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
  UVM_INFO @ 4387842211 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_ultra_low_pwr_vseq
  UVM_INFO @ 6387114937 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:106) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Starting the body from ultra_low_pwr_vseq
  UVM_INFO @ 6657031929 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 30812031929 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:109) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (* [*] vs * [*]) has 2 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.

13.sysrst_ctrl_stress_all_with_rand_reset.57285012531338669243226824124337210240646987398032296931759150215824112479641
Line 590, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10426289194 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 10426289194 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 10426289194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.sysrst_ctrl_stress_all_with_rand_reset.100634712832158775362730182253593663931063320440559510564068455388239580240260
Line 587, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5594600191 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 5596628139 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 4/10
  UVM_INFO @ 5598450561 ps: (dv_base_reg.sv:332) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 5603365548 ps: (cip_base_vseq.sv:726) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 5/10

UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 2 failures:
- Test sysrst_ctrl_ec_pwr_on_rst has 2 failures.
  - 14.sysrst_ctrl_ec_pwr_on_rst.28985628646282505290088092831539775128003639105703008606243220668673223467581
    Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  UVM_FATAL @ 2560019000 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 2560019000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.sysrst_ctrl_ec_pwr_on_rst.75790992049171383628308005225112063829652412948641109542317871047017147725514
    Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  UVM_FATAL @ 3350403410 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 3350403410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:184) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_ultra_low_pwr has 1 failures.

7.sysrst_ctrl_ultra_low_pwr.97051745579865538161733313233116112477294155043036996299929782605084003572463
Line 559, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 3182431295 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:184) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 3183020810 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.wkup_status reset value: 0x0
  UVM_INFO @ 3183020810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

56.sysrst_ctrl_combo_detect_with_pre_cond.56515024512257562897787223570838265759253291537362456868890933327430142345319
Line 600, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/56.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 36703276801 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4
  UVM_INFO @ 36893276801 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 36913276801 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 46991727804 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x28
  UVM_INFO @ 46991966933 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0xc

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

67.sysrst_ctrl_combo_detect_with_pre_cond.18183014237696106825140804800877746094228927854971429883529955038704148075824
Line 580, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/67.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 48822745269 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 60293186489 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x119
  UVM_INFO @ 60293207323 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x29
  UVM_INFO @ 63942745269 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0
  UVM_INFO @ 63957745269 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 12