Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T21,T22
1	-	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	99455104	0	0
DstReqKnown_A	192694728	170598026	0	0
SrcAckBusyChk_A	2147483647	107390	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	99455104	0	0
T2	2032928	6864	0	0
T3	921663	25748	0	0
T6	4769577	427	0	0
T7	4253472	10064	0	0
T8	0	9871	0	0
T13	781560	0	0	0
T14	774552	0	0	0
T15	504693	459	0	0
T16	5403690	668	0	0
T17	97641	0	0	0
T22	1352560	0	0	0
T25	0	476	0	0
T27	595156	11879	0	0
T28	1884766	1125	0	0
T29	0	2992	0	0
T38	727300	0	0	0
T45	3647376	7640	0	0
T46	0	3720	0	0
T47	0	2848	0	0
T48	0	3581	0	0
T49	0	2934	0	0
T50	0	1092	0	0
T51	0	3830	0	0
T52	0	2563	0	0
T53	0	2872	0	0
T54	0	10977	0	0
T55	197450	0	0	0
T56	240830	0	0	0
T57	181636	0	0	0
T58	422838	0	0	0
T59	1247288	0	0	0
T60	647600	0	0	0
T61	103920	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192694728	170598026	0	0
T1	57494	43894	0	0
T2	454716	440980	0	0
T3	725390	711552	0	0
T4	17068	3468	0	0
T5	833340	819740	0	0
T6	156672	14280	0	0
T13	27676	14076	0	0
T14	13702	102	0	0
T15	15232	1632	0	0
T16	177480	163880	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	107390	0	0
T2	2032928	10	0	0
T3	921663	16	0	0
T6	4769577	1	0	0
T7	4253472	12	0	0
T8	0	6	0	0
T13	781560	0	0	0
T14	774552	0	0	0
T15	504693	1	0	0
T16	5403690	2	0	0
T17	97641	0	0	0
T22	1352560	0	0	0
T25	0	1	0	0
T27	595156	8	0	0
T28	1884766	3	0	0
T29	0	6	0	0
T38	727300	0	0	0
T45	3647376	4	0	0
T46	0	4	0	0
T47	0	2	0	0
T48	0	9	0	0
T49	0	7	0	0
T50	0	8	0	0
T51	0	7	0	0
T52	0	13	0	0
T53	0	7	0	0
T54	0	7	0	0
T55	197450	0	0	0
T56	240830	0	0	0
T57	181636	0	0	0
T58	422838	0	0	0
T59	1247288	0	0	0
T60	647600	0	0	0
T61	103920	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3808272	3805926	0	0
T2	8639944	8637088	0	0
T3	3481838	3480682	0	0
T4	8200460	8197604	0	0
T5	3916868	3916834	0	0
T6	18018402	17937890	0	0
T13	3321630	3318400	0	0
T14	3291846	3288956	0	0
T15	1906618	1903830	0	0
T16	20413940	20412036	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T18,T31,T62
1	-	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1025922	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1110	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1025922	0	0
T1	112008	953	0	0
T2	254116	2768	0	0
T3	102407	11495	0	0
T6	529953	0	0	0
T7	472608	4244	0	0
T8	0	3219	0	0
T10	0	16402	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	164	0	0
T22	0	1992	0	0
T32	0	692	0	0
T63	0	4455	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1110	0	0
T1	112008	1	0	0
T2	254116	4	0	0
T3	102407	7	0	0
T6	529953	0	0	0
T7	472608	5	0	0
T8	0	2	0	0
T10	0	16	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T32	0	2	0	0
T63	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T5,T2,T13

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T2,T13
1	1	Covered	T5,T2,T13

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T5,T2,T13

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T2,T13
1	1	Covered	T5,T2,T13

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T5,T2,T13
0	0	1	Covered	T5,T2,T13
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T5,T2,T13
0	0	1	Covered	T5,T2,T13
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1709426	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1923	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1709426	0	0
T1	112008	0	0	0
T2	254116	3200	0	0
T3	102407	12642	0	0
T5	115202	1871	0	0
T6	529953	404	0	0
T7	472608	4170	0	0
T8	0	4504	0	0
T13	97695	349	0	0
T14	96819	0	0	0
T15	56077	432	0	0
T16	600410	305	0	0
T45	0	3762	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1923	0	0
T1	112008	0	0	0
T2	254116	5	0	0
T3	102407	8	0	0
T5	115202	1	0	0
T6	529953	1	0	0
T7	472608	6	0	0
T8	0	3	0	0
T13	97695	1	0	0
T14	96819	0	0	0
T15	56077	1	0	0
T16	600410	1	0	0
T45	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T21,T22

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T21,T22
1	1	Covered	T1,T21,T22

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T21,T22

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T21,T22
1	1	Covered	T1,T21,T22

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T21,T22
0	0	1	Covered	T1,T21,T22
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T21,T22
0	0	1	Covered	T1,T21,T22
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1072612	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1066	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1072612	0	0
T1	112008	2639	0	0
T2	254116	0	0	0
T3	102407	0	0	0
T6	529953	0	0	0
T7	472608	0	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	325	0	0
T22	0	1995	0	0
T28	0	375	0	0
T41	0	1499	0	0
T49	0	362	0	0
T64	0	396	0	0
T65	0	1434	0	0
T66	0	1594	0	0
T67	0	356	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1066	0	0
T1	112008	3	0	0
T2	254116	0	0	0
T3	102407	0	0	0
T6	529953	0	0	0
T7	472608	0	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T28	0	1	0	0
T41	0	1	0	0
T49	0	1	0	0
T64	0	3	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T21,T22

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T21,T22
1	1	Covered	T1,T21,T22

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T21,T22

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T21,T22
1	1	Covered	T1,T21,T22

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T21,T22
0	0	1	Covered	T1,T21,T22
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T21,T22
0	0	1	Covered	T1,T21,T22
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1078722	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1078	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1078722	0	0
T1	112008	2633	0	0
T2	254116	0	0	0
T3	102407	0	0	0
T6	529953	0	0	0
T7	472608	0	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	297	0	0
T22	0	1993	0	0
T28	0	373	0	0
T41	0	1497	0	0
T49	0	359	0	0
T64	0	367	0	0
T65	0	1432	0	0
T66	0	1581	0	0
T67	0	354	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1078	0	0
T1	112008	3	0	0
T2	254116	0	0	0
T3	102407	0	0	0
T6	529953	0	0	0
T7	472608	0	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T28	0	1	0	0
T41	0	1	0	0
T49	0	1	0	0
T64	0	3	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T21,T22

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T21,T22
1	1	Covered	T1,T21,T22

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T21,T22

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T21,T22
1	1	Covered	T1,T21,T22

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T21,T22
0	0	1	Covered	T1,T21,T22
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T21,T22
0	0	1	Covered	T1,T21,T22
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1093159	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1092	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1093159	0	0
T1	112008	2627	0	0
T2	254116	0	0	0
T3	102407	0	0	0
T6	529953	0	0	0
T7	472608	0	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	280	0	0
T22	0	1991	0	0
T28	0	371	0	0
T41	0	1495	0	0
T49	0	350	0	0
T64	0	378	0	0
T65	0	1430	0	0
T66	0	1571	0	0
T67	0	352	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1092	0	0
T1	112008	3	0	0
T2	254116	0	0	0
T3	102407	0	0	0
T6	529953	0	0	0
T7	472608	0	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T28	0	1	0	0
T41	0	1	0	0
T49	0	1	0	0
T64	0	3	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T6,T23,T24

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T6,T23,T24
1	1	Covered	T6,T23,T24

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T6,T23,T24

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T23,T24
1	1	Covered	T6,T23,T24

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T6,T23,T24
0	0	1	Covered	T6,T23,T24
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T6,T23,T24
0	0	1	Covered	T6,T23,T24
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	2196653	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	2249	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	2196653	0	0
T6	529953	8180	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	3350	0	0
T23	0	8941	0	0
T24	0	32520	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T56	0	16906	0	0
T61	0	7246	0	0
T68	0	4141	0	0
T69	0	32984	0	0
T70	0	17384	0	0
T71	0	35005	0	0
T72	126682	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	2249	0	0
T6	529953	20	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	20	0	0
T23	0	20	0	0
T24	0	20	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T56	0	20	0	0
T61	0	20	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	126682	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T6,T26

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T6,T26
1	1	Covered	T4,T6,T26

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T6,T26

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T26
1	1	Covered	T4,T6,T26

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T4,T6,T26
0	0	1	Covered	T4,T6,T26
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T4,T6,T26
0	0	1	Covered	T4,T6,T26
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	3772743	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	4115	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3772743	0	0
T1	112008	0	0	0
T2	254116	0	0	0
T3	102407	0	0	0
T4	241190	35448	0	0
T5	115202	0	0	0
T6	529953	445	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	0	0	0
T23	0	390	0	0
T24	0	1891	0	0
T25	0	7845	0	0
T26	0	16488	0	0
T68	0	174	0	0
T73	0	4766	0	0
T74	0	4347	0	0
T75	0	34929	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	4115	0	0
T1	112008	0	0	0
T2	254116	0	0	0
T3	102407	0	0	0
T4	241190	20	0	0
T5	115202	0	0	0
T6	529953	1	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	20	0	0
T26	0	20	0	0
T68	0	1	0	0
T73	0	20	0	0
T74	0	20	0	0
T75	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T5,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T2
1	1	Covered	T4,T5,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T5,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T2
1	1	Covered	T4,T5,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T4,T5,T2
0	0	1	Covered	T4,T5,T2
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T4,T5,T2
0	0	1	Covered	T4,T5,T2
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	4598530	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	5088	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	4598530	0	0
T1	112008	0	0	0
T2	254116	3516	0	0
T3	102407	12944	0	0
T4	241190	35528	0	0
T5	115202	1878	0	0
T6	529953	902	0	0
T7	0	5253	0	0
T13	97695	353	0	0
T14	96819	0	0	0
T15	56077	481	0	0
T16	600410	344	0	0
T45	0	3832	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	5088	0	0
T1	112008	0	0	0
T2	254116	5	0	0
T3	102407	8	0	0
T4	241190	20	0	0
T5	115202	1	0	0
T6	529953	2	0	0
T7	0	6	0	0
T13	97695	1	0	0
T14	96819	0	0	0
T15	56077	1	0	0
T16	600410	1	0	0
T45	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T26,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T26,T25
1	1	Covered	T4,T26,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T26,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T26,T25
1	1	Covered	T4,T26,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T4,T26,T25
0	0	1	Covered	T4,T26,T25
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T4,T26,T25
0	0	1	Covered	T4,T26,T25
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	3724086	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	4053	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3724086	0	0
T1	112008	0	0	0
T2	254116	0	0	0
T3	102407	0	0	0
T4	241190	35488	0	0
T5	115202	0	0	0
T6	529953	0	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	0	0	0
T25	0	7885	0	0
T26	0	16528	0	0
T73	0	4907	0	0
T74	0	4387	0	0
T75	0	34969	0	0
T76	0	33377	0	0
T77	0	1966	0	0
T78	0	34795	0	0
T79	0	8652	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	4053	0	0
T1	112008	0	0	0
T2	254116	0	0	0
T3	102407	0	0	0
T4	241190	20	0	0
T5	115202	0	0	0
T6	529953	0	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	0	0	0
T25	0	20	0	0
T26	0	20	0	0
T73	0	20	0	0
T74	0	20	0	0
T75	0	20	0	0
T76	0	20	0	0
T77	0	20	0	0
T78	0	20	0	0
T79	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T6,T9,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T6,T9,T11
1	1	Covered	T6,T9,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T6,T9,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T9,T11
1	1	Covered	T6,T9,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T6,T9,T11
0	0	1	Covered	T6,T9,T11
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T6,T9,T11
0	0	1	Covered	T6,T9,T11
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1051191	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1105	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1051191	0	0
T6	529953	444	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T9	0	1970	0	0
T11	0	1464	0	0
T12	0	983	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T22	0	2000	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T28	0	12208	0	0
T38	0	1958	0	0
T39	0	487	0	0
T41	0	1499	0	0
T44	0	1917	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1105	0	0
T6	529953	1	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T22	0	1	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T28	0	28	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T15

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T2,T3,T15
1	1	Covered	T2,T3,T15

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T15

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T15
1	1	Covered	T2,T3,T15

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T15
0	0	1	Covered	T2,T3,T15
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T15
0	0	1	Covered	T2,T3,T15
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1720888	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1928	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1720888	0	0
T2	254116	3174	0	0
T3	102407	12626	0	0
T6	529953	826	0	0
T7	472608	4125	0	0
T8	0	4477	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	421	0	0
T16	600410	303	0	0
T17	10849	0	0	0
T25	0	470	0	0
T45	405264	3758	0	0
T46	0	1798	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1928	0	0
T2	254116	5	0	0
T3	102407	8	0	0
T6	529953	2	0	0
T7	472608	6	0	0
T8	0	3	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	1	0	0
T16	600410	1	0	0
T17	10849	0	0	0
T25	0	1	0	0
T45	405264	2	0	0
T46	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T27,T28,T29

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T27,T28,T29
1	1	Covered	T27,T28,T29

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T27,T28,T29

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T28,T29
1	1	Covered	T27,T28,T29

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T27,T28,T29
0	0	1	Covered	T27,T28,T29
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T27,T28,T29
0	0	1	Covered	T27,T28,T29
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1257274	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1252	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1257274	0	0
T22	676280	0	0	0
T27	297578	7378	0	0
T28	942383	750	0	0
T29	0	1499	0	0
T38	363650	0	0	0
T48	0	2392	0	0
T49	0	1727	0	0
T50	0	734	0	0
T51	0	2238	0	0
T52	0	1377	0	0
T53	0	1679	0	0
T54	0	6223	0	0
T56	120415	0	0	0
T57	90818	0	0	0
T58	211419	0	0	0
T59	623644	0	0	0
T60	323800	0	0	0
T61	51960	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1252	0	0
T22	676280	0	0	0
T27	297578	5	0	0
T28	942383	2	0	0
T29	0	3	0	0
T38	363650	0	0	0
T48	0	6	0	0
T49	0	4	0	0
T50	0	5	0	0
T51	0	4	0	0
T52	0	7	0	0
T53	0	4	0	0
T54	0	4	0	0
T56	120415	0	0	0
T57	90818	0	0	0
T58	211419	0	0	0
T59	623644	0	0	0
T60	323800	0	0	0
T61	51960	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T27,T28,T29

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T27,T28,T29
1	1	Covered	T27,T28,T29

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T27,T28,T29

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T28,T29
1	1	Covered	T27,T28,T29

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T27,T28,T29
0	0	1	Covered	T27,T28,T29
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T27,T28,T29
0	0	1	Covered	T27,T28,T29
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1145963	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1144	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1145963	0	0
T22	676280	0	0	0
T27	297578	4501	0	0
T28	942383	375	0	0
T29	0	1493	0	0
T38	363650	0	0	0
T48	0	1189	0	0
T49	0	1207	0	0
T50	0	358	0	0
T51	0	1592	0	0
T52	0	1186	0	0
T53	0	1193	0	0
T54	0	4754	0	0
T56	120415	0	0	0
T57	90818	0	0	0
T58	211419	0	0	0
T59	623644	0	0	0
T60	323800	0	0	0
T61	51960	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144	0	0
T22	676280	0	0	0
T27	297578	3	0	0
T28	942383	1	0	0
T29	0	3	0	0
T38	363650	0	0	0
T48	0	3	0	0
T49	0	3	0	0
T50	0	3	0	0
T51	0	3	0	0
T52	0	6	0	0
T53	0	3	0	0
T54	0	3	0	0
T56	120415	0	0	0
T57	90818	0	0	0
T58	211419	0	0	0
T59	623644	0	0	0
T60	323800	0	0	0
T61	51960	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T16,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T3,T16,T7
1	1	Covered	T3,T16,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T16,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T16,T7
1	1	Covered	T3,T16,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T16,T7
0	0	1	Covered	T3,T16,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T16,T7
0	0	1	Covered	T3,T16,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	6709255	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	7106	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	6709255	0	0
T3	102407	111244	0	0
T6	529953	0	0	0
T7	472608	59849	0	0
T8	664429	144353	0	0
T15	56077	0	0	0
T16	600410	20859	0	0
T17	10849	0	0	0
T26	120875	0	0	0
T32	0	20061	0	0
T45	405264	87713	0	0
T46	0	50149	0	0
T47	0	108345	0	0
T55	197450	0	0	0
T59	0	65674	0	0
T60	0	32201	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	7106	0	0
T3	102407	67	0	0
T6	529953	0	0	0
T7	472608	72	0	0
T8	664429	88	0	0
T15	56077	0	0	0
T16	600410	51	0	0
T17	10849	0	0	0
T26	120875	0	0	0
T32	0	58	0	0
T45	405264	52	0	0
T46	0	60	0	0
T47	0	65	0	0
T55	197450	0	0	0
T59	0	77	0	0
T60	0	79	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T16,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T3,T16,T7
1	1	Covered	T3,T16,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T16,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T16,T7
1	1	Covered	T3,T16,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T16,T7
0	0	1	Covered	T3,T16,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T16,T7
0	0	1	Covered	T3,T16,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	6550686	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	7034	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	6550686	0	0
T3	102407	110928	0	0
T6	529953	0	0	0
T7	472608	54599	0	0
T8	664429	102911	0	0
T15	56077	0	0	0
T16	600410	20649	0	0
T17	10849	0	0	0
T26	120875	0	0	0
T32	0	29176	0	0
T45	405264	122028	0	0
T46	0	60941	0	0
T47	0	105243	0	0
T55	197450	0	0	0
T59	0	68800	0	0
T60	0	30696	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	7034	0	0
T3	102407	67	0	0
T6	529953	0	0	0
T7	472608	68	0	0
T8	664429	63	0	0
T15	56077	0	0	0
T16	600410	51	0	0
T17	10849	0	0	0
T26	120875	0	0	0
T32	0	85	0	0
T45	405264	73	0	0
T46	0	74	0	0
T47	0	63	0	0
T55	197450	0	0	0
T59	0	81	0	0
T60	0	79	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T16,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T3,T16,T7
1	1	Covered	T3,T16,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T16,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T16,T7
1	1	Covered	T3,T16,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T16,T7
0	0	1	Covered	T3,T16,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T16,T7
0	0	1	Covered	T3,T16,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	6652393	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	7146	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	6652393	0	0
T3	102407	96780	0	0
T6	529953	0	0	0
T7	472608	43851	0	0
T8	664429	110706	0	0
T15	56077	0	0	0
T16	600410	20439	0	0
T17	10849	0	0	0
T26	120875	0	0	0
T32	0	24443	0	0
T45	405264	114568	0	0
T46	0	53899	0	0
T47	0	113671	0	0
T55	197450	0	0	0
T59	0	65093	0	0
T60	0	29930	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	7146	0	0
T3	102407	58	0	0
T6	529953	0	0	0
T7	472608	56	0	0
T8	664429	68	0	0
T15	56077	0	0	0
T16	600410	51	0	0
T17	10849	0	0	0
T26	120875	0	0	0
T32	0	75	0	0
T45	405264	68	0	0
T46	0	66	0	0
T47	0	69	0	0
T55	197450	0	0	0
T59	0	77	0	0
T60	0	79	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T16,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T3,T16,T7
1	1	Covered	T3,T16,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T16,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T16,T7
1	1	Covered	T3,T16,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T16,T7
0	0	1	Covered	T3,T16,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T16,T7
0	0	1	Covered	T3,T16,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	6438132	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	7104	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	6438132	0	0
T3	102407	110332	0	0
T6	529953	0	0	0
T7	472608	49520	0	0
T8	664429	100512	0	0
T15	56077	0	0	0
T16	600410	20229	0	0
T17	10849	0	0	0
T26	120875	0	0	0
T32	0	26687	0	0
T45	405264	104271	0	0
T46	0	60383	0	0
T47	0	132598	0	0
T55	197450	0	0	0
T59	0	79858	0	0
T60	0	28565	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	7104	0	0
T3	102407	67	0	0
T6	529953	0	0	0
T7	472608	64	0	0
T8	664429	63	0	0
T15	56077	0	0	0
T16	600410	51	0	0
T17	10849	0	0	0
T26	120875	0	0	0
T32	0	85	0	0
T45	405264	62	0	0
T46	0	74	0	0
T47	0	80	0	0
T55	197450	0	0	0
T59	0	96	0	0
T60	0	76	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T16,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T3,T16,T7
1	1	Covered	T3,T16,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T16,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T16,T7
1	1	Covered	T3,T16,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T16,T7
0	0	1	Covered	T3,T16,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T16,T7
0	0	1	Covered	T3,T16,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1357053	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1376	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1357053	0	0
T3	102407	12946	0	0
T6	529953	0	0	0
T7	472608	5312	0	0
T8	664429	5073	0	0
T15	56077	0	0	0
T16	600410	343	0	0
T17	10849	0	0	0
T26	120875	0	0	0
T32	0	1127	0	0
T45	405264	3838	0	0
T46	0	1878	0	0
T47	0	2876	0	0
T55	197450	0	0	0
T59	0	7827	0	0
T60	0	4076	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1376	0	0
T3	102407	8	0	0
T6	529953	0	0	0
T7	472608	6	0	0
T8	664429	3	0	0
T15	56077	0	0	0
T16	600410	1	0	0
T17	10849	0	0	0
T26	120875	0	0	0
T32	0	3	0	0
T45	405264	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T55	197450	0	0	0
T59	0	9	0	0
T60	0	10	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T16,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T3,T16,T7
1	1	Covered	T3,T16,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T16,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T16,T7
1	1	Covered	T3,T16,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T16,T7
0	0	1	Covered	T3,T16,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T16,T7
0	0	1	Covered	T3,T16,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1290427	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1354	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1290427	0	0
T3	102407	12866	0	0
T6	529953	0	0	0
T7	472608	5003	0	0
T8	664429	4918	0	0
T15	56077	0	0	0
T16	600410	333	0	0
T17	10849	0	0	0
T26	120875	0	0	0
T32	0	1014	0	0
T45	405264	3818	0	0
T46	0	1858	0	0
T47	0	2856	0	0
T55	197450	0	0	0
T59	0	7737	0	0
T60	0	3722	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1354	0	0
T3	102407	8	0	0
T6	529953	0	0	0
T7	472608	6	0	0
T8	664429	3	0	0
T15	56077	0	0	0
T16	600410	1	0	0
T17	10849	0	0	0
T26	120875	0	0	0
T32	0	3	0	0
T45	405264	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T55	197450	0	0	0
T59	0	9	0	0
T60	0	10	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T16,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T3,T16,T7
1	1	Covered	T3,T16,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T16,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T16,T7
1	1	Covered	T3,T16,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T16,T7
0	0	1	Covered	T3,T16,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T16,T7
0	0	1	Covered	T3,T16,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1270139	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1344	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1270139	0	0
T3	102407	12786	0	0
T6	529953	0	0	0
T7	472608	4695	0	0
T8	664429	4788	0	0
T15	56077	0	0	0
T16	600410	323	0	0
T17	10849	0	0	0
T26	120875	0	0	0
T32	0	885	0	0
T45	405264	3798	0	0
T46	0	1838	0	0
T47	0	2836	0	0
T55	197450	0	0	0
T59	0	7647	0	0
T60	0	3388	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1344	0	0
T3	102407	8	0	0
T6	529953	0	0	0
T7	472608	6	0	0
T8	664429	3	0	0
T15	56077	0	0	0
T16	600410	1	0	0
T17	10849	0	0	0
T26	120875	0	0	0
T32	0	3	0	0
T45	405264	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T55	197450	0	0	0
T59	0	9	0	0
T60	0	10	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T16,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T3,T16,T7
1	1	Covered	T3,T16,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T16,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T16,T7
1	1	Covered	T3,T16,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T16,T7
0	0	1	Covered	T3,T16,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T16,T7
0	0	1	Covered	T3,T16,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1275640	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1347	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1275640	0	0
T3	102407	12706	0	0
T6	529953	0	0	0
T7	472608	4394	0	0
T8	664429	4631	0	0
T15	56077	0	0	0
T16	600410	313	0	0
T17	10849	0	0	0
T26	120875	0	0	0
T32	0	1070	0	0
T45	405264	3778	0	0
T46	0	1818	0	0
T47	0	2816	0	0
T55	197450	0	0	0
T59	0	7557	0	0
T60	0	3653	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1347	0	0
T3	102407	8	0	0
T6	529953	0	0	0
T7	472608	6	0	0
T8	664429	3	0	0
T15	56077	0	0	0
T16	600410	1	0	0
T17	10849	0	0	0
T26	120875	0	0	0
T32	0	3	0	0
T45	405264	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T55	197450	0	0	0
T59	0	9	0	0
T60	0	10	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T15

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T2,T3,T15
1	1	Covered	T2,T3,T15

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T15

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T15
1	1	Covered	T2,T3,T15

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T15
0	0	1	Covered	T2,T3,T15
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T15
0	0	1	Covered	T2,T3,T15
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	7166560	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	7620	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	7166560	0	0
T2	254116	3586	0	0
T3	102407	111330	0	0
T6	529953	440	0	0
T7	472608	60408	0	0
T8	0	145133	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	471	0	0
T16	600410	20955	0	0
T17	10849	0	0	0
T25	0	478	0	0
T45	405264	87805	0	0
T46	0	50257	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	7620	0	0
T2	254116	5	0	0
T3	102407	67	0	0
T6	529953	1	0	0
T7	472608	72	0	0
T8	0	88	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	1	0	0
T16	600410	51	0	0
T17	10849	0	0	0
T25	0	1	0	0
T45	405264	52	0	0
T46	0	60	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	6985009	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	7539	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	6985009	0	0
T2	254116	3548	0	0
T3	102407	111014	0	0
T6	529953	0	0	0
T7	472608	55196	0	0
T8	0	103385	0	0
T10	0	17448	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	20745	0	0
T17	10849	0	0	0
T45	405264	122162	0	0
T46	0	61077	0	0
T47	0	105357	0	0
T63	0	7096	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	7539	0	0
T2	254116	5	0	0
T3	102407	67	0	0
T6	529953	0	0	0
T7	472608	68	0	0
T8	0	63	0	0
T10	0	17	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	51	0	0
T17	10849	0	0	0
T45	405264	73	0	0
T46	0	74	0	0
T47	0	63	0	0
T63	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	7074519	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	7666	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	7074519	0	0
T2	254116	3518	0	0
T3	102407	96848	0	0
T6	529953	0	0	0
T7	472608	44021	0	0
T8	0	111314	0	0
T10	0	17332	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	20535	0	0
T17	10849	0	0	0
T45	405264	114692	0	0
T46	0	54019	0	0
T47	0	113797	0	0
T63	0	7027	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	7666	0	0
T2	254116	5	0	0
T3	102407	58	0	0
T6	529953	0	0	0
T7	472608	56	0	0
T8	0	68	0	0
T10	0	17	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	51	0	0
T17	10849	0	0	0
T45	405264	68	0	0
T46	0	66	0	0
T47	0	69	0	0
T63	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	6805454	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	7580	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	6805454	0	0
T2	254116	3487	0	0
T3	102407	110418	0	0
T6	529953	0	0	0
T7	472608	49997	0	0
T8	0	101130	0	0
T10	0	17183	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	20325	0	0
T17	10849	0	0	0
T45	405264	104383	0	0
T46	0	60519	0	0
T47	0	132746	0	0
T63	0	6970	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	7580	0	0
T2	254116	5	0	0
T3	102407	67	0	0
T6	529953	0	0	0
T7	472608	64	0	0
T8	0	63	0	0
T10	0	17	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	51	0	0
T17	10849	0	0	0
T45	405264	62	0	0
T46	0	74	0	0
T47	0	80	0	0
T63	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T15

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T2,T3,T15
1	1	Covered	T2,T3,T15

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T15

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T15
1	1	Covered	T2,T3,T15

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T15
0	0	1	Covered	T2,T3,T15
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T15
0	0	1	Covered	T2,T3,T15
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1681120	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1870	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1681120	0	0
T2	254116	3444	0	0
T3	102407	12914	0	0
T6	529953	427	0	0
T7	472608	5185	0	0
T8	0	5004	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	459	0	0
T16	600410	339	0	0
T17	10849	0	0	0
T25	0	476	0	0
T45	405264	3830	0	0
T46	0	1870	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1870	0	0
T2	254116	5	0	0
T3	102407	8	0	0
T6	529953	1	0	0
T7	472608	6	0	0
T8	0	3	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	1	0	0
T16	600410	1	0	0
T17	10849	0	0	0
T25	0	1	0	0
T45	405264	2	0	0
T46	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1689833	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1853	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1689833	0	0
T2	254116	3420	0	0
T3	102407	12834	0	0
T6	529953	0	0	0
T7	472608	4879	0	0
T8	0	4867	0	0
T10	0	16953	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	329	0	0
T17	10849	0	0	0
T45	405264	3810	0	0
T46	0	1850	0	0
T47	0	2848	0	0
T63	0	6855	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1853	0	0
T2	254116	5	0	0
T3	102407	8	0	0
T6	529953	0	0	0
T7	472608	6	0	0
T8	0	3	0	0
T10	0	17	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	1	0	0
T17	10849	0	0	0
T45	405264	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T63	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1679228	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1858	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1679228	0	0
T2	254116	3388	0	0
T3	102407	12754	0	0
T6	529953	0	0	0
T7	472608	4589	0	0
T8	0	4721	0	0
T10	0	16846	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	319	0	0
T17	10849	0	0	0
T45	405264	3790	0	0
T46	0	1830	0	0
T47	0	2828	0	0
T63	0	6789	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1858	0	0
T2	254116	5	0	0
T3	102407	8	0	0
T6	529953	0	0	0
T7	472608	6	0	0
T8	0	3	0	0
T10	0	17	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	1	0	0
T17	10849	0	0	0
T45	405264	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T63	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1672190	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1856	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1672190	0	0
T2	254116	3350	0	0
T3	102407	12674	0	0
T6	529953	0	0	0
T7	472608	4252	0	0
T8	0	4573	0	0
T10	0	16732	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	309	0	0
T17	10849	0	0	0
T45	405264	3770	0	0
T46	0	1810	0	0
T47	0	2808	0	0
T63	0	6739	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1856	0	0
T2	254116	5	0	0
T3	102407	8	0	0
T6	529953	0	0	0
T7	472608	6	0	0
T8	0	3	0	0
T10	0	17	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	1	0	0
T17	10849	0	0	0
T45	405264	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T63	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T15

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T2,T3,T15
1	1	Covered	T2,T3,T15

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T15

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T15
1	1	Covered	T2,T3,T15

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T15
0	0	1	Covered	T2,T3,T15
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T15
0	0	1	Covered	T2,T3,T15
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1684823	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1869	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1684823	0	0
T2	254116	3320	0	0
T3	102407	12898	0	0
T6	529953	418	0	0
T7	472608	5132	0	0
T8	0	4974	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	450	0	0
T16	600410	337	0	0
T17	10849	0	0	0
T25	0	474	0	0
T45	405264	3826	0	0
T46	0	1866	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1869	0	0
T2	254116	5	0	0
T3	102407	8	0	0
T6	529953	1	0	0
T7	472608	6	0	0
T8	0	3	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	1	0	0
T16	600410	1	0	0
T17	10849	0	0	0
T25	0	1	0	0
T45	405264	2	0	0
T46	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1664926	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1859	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1664926	0	0
T2	254116	3287	0	0
T3	102407	12818	0	0
T6	529953	0	0	0
T7	472608	4817	0	0
T8	0	4834	0	0
T10	0	16501	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	327	0	0
T17	10849	0	0	0
T45	405264	3806	0	0
T46	0	1846	0	0
T47	0	2844	0	0
T63	0	6621	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1859	0	0
T2	254116	5	0	0
T3	102407	8	0	0
T6	529953	0	0	0
T7	472608	6	0	0
T8	0	3	0	0
T10	0	17	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	1	0	0
T17	10849	0	0	0
T45	405264	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T63	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1618689	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1826	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1618689	0	0
T2	254116	3263	0	0
T3	102407	12738	0	0
T6	529953	0	0	0
T7	472608	4520	0	0
T8	0	4689	0	0
T10	0	16400	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	317	0	0
T17	10849	0	0	0
T45	405264	3786	0	0
T46	0	1826	0	0
T47	0	2824	0	0
T63	0	6568	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1826	0	0
T2	254116	5	0	0
T3	102407	8	0	0
T6	529953	0	0	0
T7	472608	6	0	0
T8	0	3	0	0
T10	0	17	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	1	0	0
T17	10849	0	0	0
T45	405264	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T63	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1652631	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1877	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1652631	0	0
T2	254116	3237	0	0
T3	102407	12658	0	0
T6	529953	0	0	0
T7	472608	4205	0	0
T8	0	4537	0	0
T10	0	16287	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	307	0	0
T17	10849	0	0	0
T45	405264	3766	0	0
T46	0	1806	0	0
T47	0	2804	0	0
T63	0	6530	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1877	0	0
T2	254116	5	0	0
T3	102407	8	0	0
T6	529953	0	0	0
T7	472608	6	0	0
T8	0	3	0	0
T10	0	17	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	1	0	0
T17	10849	0	0	0
T45	405264	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T63	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T21,T22

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T21,T22
1	1	Covered	T1,T21,T22

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T21,T22
1	-	Covered	T1,T21,T22

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T21,T22

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T21,T22
1	1	Covered	T1,T21,T22

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T21,T22
0	0	1	Covered	T1,T21,T22
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T21,T22
0	0	1	Covered	T1,T21,T22
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1144834408	1089228	0	0
DstReqKnown_A	5667492	5017589	0	0
SrcAckBusyChk_A	1144834408	1103	0	0
SrcBusyKnown_A	1144834408	1144428958	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1089228	0	0
T1	112008	1915	0	0
T2	254116	0	0	0
T3	102407	0	0	0
T6	529953	0	0	0
T7	472608	0	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	321	0	0
T22	0	3992	0	0
T28	0	1365	0	0
T64	0	513	0	0
T65	0	2870	0	0
T80	0	3455	0	0
T81	0	225	0	0
T82	0	173	0	0
T83	0	866	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5667492	5017589	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1103	0	0
T1	112008	2	0	0
T2	254116	0	0	0
T3	102407	0	0	0
T6	529953	0	0	0
T7	472608	0	0	0
T13	97695	0	0	0
T14	96819	0	0	0
T15	56077	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	2	0	0
T22	0	2	0	0
T28	0	4	0	0
T64	0	4	0	0
T65	0	2	0	0
T80	0	2	0	0
T81	0	2	0	0
T82	0	2	0	0
T83	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1144428958	0	0
T1	112008	111939	0	0
T2	254116	254032	0	0
T3	102407	102373	0	0
T4	241190	241106	0	0
T5	115202	115201	0	0
T6	529953	527585	0	0
T13	97695	97600	0	0
T14	96819	96734	0	0
T15	56077	55995	0	0
T16	600410	600354	0	0