Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_detect_action_obj::sysrst_ctrl_combo_detect_action_cg
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Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_detect_action_obj::sysrst_ctrl_combo_detect_action_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

4 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_combo_detect_action_cg_0 100.00 1 100 1 64 64
sysrst_ctrl_combo_detect_action_cg_1 100.00 1 100 1 64 64
sysrst_ctrl_combo_detect_action_cg_2 100.00 1 100 1 64 64
sysrst_ctrl_combo_detect_action_cg_3 100.00 1 100 1 64 64




Group Instance : sysrst_ctrl_combo_detect_action_cg_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_combo_detect_action_cg_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 28 0 28 100.00


Variables for Group Instance sysrst_ctrl_combo_detect_action_cg_0
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_bat_disable 2 0 2 100.00 100 1 1 2
cp_ec_rst 2 0 2 100.00 100 1 1 2
cp_interrupt 2 0 2 100.00 100 1 1 2
cp_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_rst_req 2 0 2 100.00 100 1 1 2



Group Instance : sysrst_ctrl_combo_detect_action_cg_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_combo_detect_action_cg_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 28 0 28 100.00


Variables for Group Instance sysrst_ctrl_combo_detect_action_cg_1
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_bat_disable 2 0 2 100.00 100 1 1 2
cp_ec_rst 2 0 2 100.00 100 1 1 2
cp_interrupt 2 0 2 100.00 100 1 1 2
cp_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_rst_req 2 0 2 100.00 100 1 1 2



Group Instance : sysrst_ctrl_combo_detect_action_cg_2
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_combo_detect_action_cg_2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 28 0 28 100.00


Variables for Group Instance sysrst_ctrl_combo_detect_action_cg_2
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_bat_disable 2 0 2 100.00 100 1 1 2
cp_ec_rst 2 0 2 100.00 100 1 1 2
cp_interrupt 2 0 2 100.00 100 1 1 2
cp_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_rst_req 2 0 2 100.00 100 1 1 2



Group Instance : sysrst_ctrl_combo_detect_action_cg_3
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_combo_detect_action_cg_3

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 28 0 28 100.00


Variables for Group Instance sysrst_ctrl_combo_detect_action_cg_3
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_bat_disable 2 0 2 100.00 100 1 1 2
cp_ec_rst 2 0 2 100.00 100 1 1 2
cp_interrupt 2 0 2 100.00 100 1 1 2
cp_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_rst_req 2 0 2 100.00 100 1 1 2


Summary for Variable cp_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 496 1 T1 12 T3 4 T8 4
auto[1] 170 1 T19 1 T3 4 T13 3



Summary for Variable cp_bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_bat_disable

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 313 1 T3 4 T8 2 T11 8
auto[1] 353 1 T1 12 T19 1 T3 4



Summary for Variable cp_ec_rst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 345 1 T3 4 T8 2 T11 8
auto[1] 321 1 T1 12 T19 1 T3 4



Summary for Variable cp_interrupt

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_interrupt

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 353 1 T1 12 T19 1 T3 3
auto[1] 313 1 T3 5 T8 2 T11 1



Summary for Variable cp_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 503 1 T1 12 T19 1 T3 8
auto[1] 163 1 T13 3 T36 2 T64 1



Summary for Variable cp_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 536 1 T1 12 T3 8 T8 4
auto[1] 130 1 T19 1 T36 2 T78 2



Summary for Variable cp_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 510 1 T3 8 T8 4 T11 7
auto[1] 156 1 T1 12 T19 1 T11 1



Summary for Variable cp_precondition_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 578 1 T1 12 T19 1 T3 8
auto[1] 88 1 T8 4 T36 2 T78 2



Summary for Variable cp_precondition_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 602 1 T1 12 T19 1 T3 8
auto[1] 64 1 T11 1 T78 2 T79 3



Summary for Variable cp_precondition_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 631 1 T1 12 T19 1 T3 4
auto[1] 35 1 T3 4 T8 4 T79 3



Summary for Variable cp_precondition_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 603 1 T1 12 T19 1 T3 4
auto[1] 63 1 T3 4 T78 2 T79 3



Summary for Variable cp_precondition_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 624 1 T1 12 T19 1 T3 8
auto[1] 42 1 T78 2 T243 1 T361 6



Summary for Variable cp_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 497 1 T1 12 T3 4 T11 7
auto[1] 169 1 T19 1 T3 4 T8 4



Summary for Variable cp_rst_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rst_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 335 1 T3 2 T8 2 T11 7
auto[1] 331 1 T1 12 T19 1 T3 6


Summary for Variable cp_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 499 1 T1 2 T19 12 T3 3
auto[1] 151 1 T3 5 T13 1 T78 13



Summary for Variable cp_bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_bat_disable

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 298 1 T3 4 T8 2 T11 8
auto[1] 352 1 T1 2 T19 12 T3 4



Summary for Variable cp_ec_rst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 335 1 T1 2 T19 12 T3 4
auto[1] 315 1 T3 4 T8 2 T13 1



Summary for Variable cp_interrupt

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_interrupt

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 330 1 T19 12 T3 3 T8 2
auto[1] 320 1 T1 2 T3 5 T8 2



Summary for Variable cp_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 533 1 T19 12 T3 8 T8 4
auto[1] 117 1 T1 2 T35 3 T102 3



Summary for Variable cp_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 500 1 T19 12 T3 3 T8 4
auto[1] 150 1 T1 2 T3 5 T13 1



Summary for Variable cp_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 472 1 T19 12 T3 8 T8 4
auto[1] 178 1 T1 2 T13 1 T35 3



Summary for Variable cp_precondition_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 603 1 T1 2 T19 12 T3 8
auto[1] 47 1 T54 6 T137 6 T233 5



Summary for Variable cp_precondition_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 549 1 T1 2 T19 12 T3 3
auto[1] 101 1 T3 5 T78 13 T79 6



Summary for Variable cp_precondition_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 601 1 T1 2 T19 12 T3 8
auto[1] 49 1 T36 1 T102 3 T233 5



Summary for Variable cp_precondition_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 616 1 T1 2 T19 12 T3 8
auto[1] 34 1 T36 1 T134 11 T99 3



Summary for Variable cp_precondition_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 604 1 T1 2 T19 12 T3 3
auto[1] 46 1 T3 5 T99 3 T366 4



Summary for Variable cp_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 476 1 T3 8 T8 4 T11 8
auto[1] 174 1 T1 2 T19 12 T54 6



Summary for Variable cp_rst_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rst_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 274 1 T1 2 T19 12 T3 2
auto[1] 376 1 T3 6 T8 2 T11 1


Summary for Variable cp_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 522 1 T3 5 T8 4 T11 1
auto[1] 130 1 T1 5 T3 3 T11 7



Summary for Variable cp_bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_bat_disable

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 285 1 T3 4 T8 2 T11 8
auto[1] 367 1 T1 5 T3 4 T8 2



Summary for Variable cp_ec_rst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 329 1 T1 5 T3 4 T8 2
auto[1] 323 1 T3 4 T8 2 T13 1



Summary for Variable cp_interrupt

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_interrupt

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 293 1 T1 5 T3 3 T8 2
auto[1] 359 1 T3 5 T8 2 T11 1



Summary for Variable cp_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 497 1 T1 5 T3 5 T8 4
auto[1] 155 1 T3 3 T79 5 T64 5



Summary for Variable cp_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 495 1 T3 8 T11 8 T35 9
auto[1] 157 1 T1 5 T8 4 T13 1



Summary for Variable cp_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 485 1 T3 8 T8 4 T11 8
auto[1] 167 1 T1 5 T13 1 T36 2



Summary for Variable cp_precondition_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 579 1 T1 5 T3 8 T11 8
auto[1] 73 1 T8 4 T79 5 T161 1



Summary for Variable cp_precondition_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 596 1 T1 5 T3 8 T8 4
auto[1] 56 1 T36 2 T137 1 T161 1



Summary for Variable cp_precondition_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 601 1 T1 5 T3 5 T8 4
auto[1] 51 1 T3 3 T11 7 T36 2



Summary for Variable cp_precondition_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 600 1 T1 5 T3 5 T8 4
auto[1] 52 1 T3 3 T137 1 T361 3



Summary for Variable cp_precondition_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 618 1 T1 5 T3 5 T8 4
auto[1] 34 1 T3 3 T137 1 T103 2



Summary for Variable cp_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 476 1 T1 5 T3 8 T11 8
auto[1] 176 1 T8 4 T35 9 T79 5



Summary for Variable cp_rst_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rst_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 354 1 T1 5 T3 2 T8 2
auto[1] 298 1 T3 6 T8 2 T11 1


Summary for Variable cp_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 477 1 T1 3 T3 8 T8 4
auto[1] 148 1 T54 3 T36 3 T37 2



Summary for Variable cp_bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_bat_disable

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 303 1 T3 4 T8 2 T11 8
auto[1] 322 1 T1 3 T3 4 T8 2



Summary for Variable cp_ec_rst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 337 1 T1 3 T3 4 T8 2
auto[1] 288 1 T3 4 T8 2 T35 7



Summary for Variable cp_interrupt

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_interrupt

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 302 1 T1 3 T3 3 T8 2
auto[1] 323 1 T3 5 T8 2 T11 1



Summary for Variable cp_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 476 1 T3 3 T8 4 T11 8
auto[1] 149 1 T1 3 T3 5 T54 3



Summary for Variable cp_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 460 1 T3 3 T8 4 T11 8
auto[1] 165 1 T1 3 T3 5 T37 2



Summary for Variable cp_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 480 1 T1 3 T3 3 T8 4
auto[1] 145 1 T3 5 T35 7 T36 3



Summary for Variable cp_precondition_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 590 1 T1 3 T3 3 T8 4
auto[1] 35 1 T3 5 T243 3 T384 5



Summary for Variable cp_precondition_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 544 1 T1 3 T3 8 T8 4
auto[1] 81 1 T36 3 T78 13 T134 11



Summary for Variable cp_precondition_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 592 1 T1 3 T3 8 T8 4
auto[1] 33 1 T54 3 T137 6 T243 3



Summary for Variable cp_precondition_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 553 1 T1 3 T3 8 T8 4
auto[1] 72 1 T134 11 T233 3 T120 1



Summary for Variable cp_precondition_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 579 1 T1 3 T3 8 T8 4
auto[1] 46 1 T79 2 T137 6 T243 3



Summary for Variable cp_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 452 1 T3 8 T8 4 T11 8
auto[1] 173 1 T1 3 T35 7 T54 3



Summary for Variable cp_rst_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rst_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 291 1 T1 3 T3 2 T8 2
auto[1] 334 1 T3 6 T8 2 T11 1